JP2006041502A5 - - Google Patents
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- JP2006041502A5 JP2006041502A5 JP2005185380A JP2005185380A JP2006041502A5 JP 2006041502 A5 JP2006041502 A5 JP 2006041502A5 JP 2005185380 A JP2005185380 A JP 2005185380A JP 2005185380 A JP2005185380 A JP 2005185380A JP 2006041502 A5 JP2006041502 A5 JP 2006041502A5
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- release layer
- forming
- layer
- insulating film
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Claims (9)
前記第２の領域の前記剥離層を除去し、
前記第１の領域の前記剥離層上と前記第２の領域の前記基板上に、絶縁膜を形成し、
前記第１の領域の前記絶縁膜上に、複数の素子と導電層を形成し、
前記第１の領域の前記絶縁膜に、前記剥離層が露出される開口部を形成し、
前記第１の領域の前記開口部にエッチング剤を導入して、前記剥離層を除去することを特徴とする薄膜集積回路の作製方法。 Forming a release layer on the first region and the second region over the substrate having an insulating surface;
Removing the release layer in the second region;
Forming an insulating film on the release layer in the first region and on the substrate in the second region;
Forming a plurality of elements and a conductive layer on the insulating film in the first region;
Forming an opening through which the release layer is exposed in the insulating film of the first region;
A method for manufacturing a thin film integrated circuit, wherein an etchant is introduced into the opening in the first region to remove the release layer.
前記第１の領域の前記剥離層を選択的に除去し、
前記第２の領域の前記剥離層を除去し、
前記第１の領域と前記第２の領域の前記剥離層上に、絶縁膜を形成し、
前記第１の領域の前記絶縁膜上に、複数の素子と導電層を形成し、
前記第１の領域の前記絶縁膜に、前記剥離層が露出される開口部を形成し、
前記第１の領域の前記開口部にエッチング剤を導入して、前記剥離層を除去し、
前記第１の領域の前記剥離層を選択的に除去する工程では、前記第１の領域に含まれ前記複数の素子と前記導電層が設けられた第３の領域の前記剥離層は除去せず、前記第１の領域に含まれ前記開口部が設けられた第４の領域の前記剥離層は除去せず、前記第１の領域に含まれ前記第３の領域と前記第４の領域を除く第５の領域の前記剥離層を除去することを特徴とする薄膜集積回路の作製方法。 Forming a release layer on the first region and the second region over the substrate having an insulating surface;
Selectively removing the release layer in the first region;
Removing the release layer in the second region;
Forming an insulating film on the release layer of the first region and the second region;
Forming a plurality of elements and a conductive layer on the insulating film in the first region;
Forming an opening through which the release layer is exposed in the insulating film of the first region;
Introducing an etchant into the opening in the first region to remove the release layer;
In the step of selectively removing the release layer in the first region, the release layer in the third region included in the first region and provided with the plurality of elements and the conductive layer is not removed. the peeling layer in the fourth region in which the said opening is included in the first area is provided without removing, it included in the first region excluding the third region and the fourth region A method for manufacturing a thin film integrated circuit, wherein the release layer in the fifth region is removed.
前記第１の領域の前記剥離層を選択的に除去し、
前記第２の領域の前記剥離層を除去し、
前記第１の領域と前記第２の領域の前記剥離層上に、絶縁膜を形成し、
前記第１の領域の前記絶縁膜上に、複数の素子と導電層を形成し、
前記第１の領域の前記絶縁膜に、前記剥離層が露出される開口部を形成し、
前記第１の領域の前記開口部にエッチング剤を導入して、前記剥離層を除去し、
前記第１の領域の前記剥離層を選択的に除去する工程では、前記第１の領域に含まれ前記複数の素子と前記導電層が設けられた第３の領域の前記剥離層は除去せず、前記第１の領域に含まれ前記開口部が設けられた第４の領域の前記剥離層は除去せず、前記第１の領域に含まれ前記第３の領域と前記第４の領域を除く第５の領域の前記剥離層を選択的に除去することを特徴とする薄膜集積回路の作製方法。 Forming a release layer on the first region and the second region over the substrate having an insulating surface;
Selectively removing the release layer in the first region;
Removing the release layer in the second region;
Forming an insulating film on the release layer of the first region and the second region;
Forming a plurality of elements and a conductive layer on the insulating film in the first region;
Forming an opening through which the release layer is exposed in the insulating film of the first region;
Introducing an etchant into the opening in the first region to remove the release layer;
In the step of selectively removing the release layer in the first region, the release layer in the third region included in the first region and provided with the plurality of elements and the conductive layer is not removed. the peeling layer in the fourth region in which the said opening is included in the first area is provided without removing, it included in the first region excluding the third region and the fourth region A method for manufacturing a thin film integrated circuit, wherein the peeling layer in a fifth region is selectively removed.
前記第１の領域の前記剥離層を選択的に除去し、
前記第２の領域の前記剥離層を除去し、
前記第１の領域と前記第２の領域の前記剥離層上に、絶縁膜を形成し、
前記第１の領域の前記絶縁膜上に、複数の素子と導電層を形成し、
前記第１の領域の前記絶縁膜に、前記剥離層が露出される開口部を形成し、
前記第１の領域の前記開口部にエッチング剤を導入して、前記剥離層を除去し、
前記第１の領域の前記剥離層を選択的に除去する工程では、前記第１の領域に含まれ前記複数の素子と前記導電層が設けられた第３の領域の前記剥離層を選択的に除去し、前記第１の領域に含まれ前記開口部が設けられた第４の領域の前記剥離層を除去しないことを特徴とする薄膜集積回路の作製方法。 Forming a release layer on the first region and the second region over the substrate having an insulating surface;
Selectively removing the release layer in the first region;
Removing the release layer in the second region;
Forming an insulating film on the release layer of the first region and the second region;
Forming a plurality of elements and a conductive layer on the insulating film in the first region;
Forming an opening through which the release layer is exposed in the insulating film of the first region;
Introducing an etchant into the opening in the first region to remove the release layer;
In the step of selectively removing the release layer in the first region, the release layer in the third region included in the first region and provided with the plurality of elements and the conductive layer is selectively selected. A method for manufacturing a thin film integrated circuit, wherein the peeling layer is not removed and the peeling layer in the fourth region included in the first region and provided with the opening is not removed.
前記第２の領域の前記剥離層を選択的に除去することを特徴とする薄膜集積回路の作製方法。A method for manufacturing a thin film integrated circuit, wherein the peeling layer in the second region is selectively removed.
前記絶縁膜は、前記第１の領域の前記剥離層と前記第２の領域の前記基板に接するように、形成されることを特徴とする薄膜集積回路の作製方法。 In claim 1 ,
The method for manufacturing a thin film integrated circuit, wherein the insulating film is formed so as to be in contact with the peeling layer in the first region and the substrate in the second region.
前記絶縁膜は、前記第１の領域の前記基板及び前記剥離層と、前記第２の領域の前記基板に接するように、形成されることを特徴とする薄膜集積回路の作製方法。 In any one of Claims 2 thru | or 4 ,
The method for manufacturing a thin film integrated circuit, wherein the insulating film is formed so as to be in contact with the substrate and the release layer in the first region and the substrate in the second region.
前記エッチング剤は、フッ化ハロゲンを含む気体又は液体であることを特徴とする薄膜集積回路の作製方法。 In any one of Claims 1 thru | or 7 ,
The method for manufacturing a thin film integrated circuit, wherein the etching agent is a gas or a liquid containing halogen fluoride.
前記導電層は、アンテナとして機能することを特徴とする薄膜集積回路の作製方法。 In any one of Claims 1 thru | or 8 ,
The method for manufacturing a thin film integrated circuit, wherein the conductive layer functions as an antenna.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005185380A JP4912627B2 (en) | 2004-06-24 | 2005-06-24 | Method for manufacturing thin film integrated circuit |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004186543 | 2004-06-24 | ||
| JP2004186543 | 2004-06-24 | ||
| JP2005185380A JP4912627B2 (en) | 2004-06-24 | 2005-06-24 | Method for manufacturing thin film integrated circuit |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2006041502A JP2006041502A (en) | 2006-02-09 |
| JP2006041502A5 true JP2006041502A5 (en) | 2008-05-15 |
| JP4912627B2 JP4912627B2 (en) | 2012-04-11 |
Family
ID=35906104
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005185380A Expired - Fee Related JP4912627B2 (en) | 2004-06-24 | 2005-06-24 | Method for manufacturing thin film integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4912627B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5204959B2 (en) | 2006-06-26 | 2013-06-05 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| JP5264016B2 (en) * | 2006-06-30 | 2013-08-14 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| WO2008036837A2 (en) * | 2006-09-20 | 2008-03-27 | The Board Of Trustees Of The University Of Illinois | Release strategies for making transferable semiconductor structures, devices and device components |
| CN111758156A (en) * | 2017-12-22 | 2020-10-09 | 德克萨斯大学系统董事会 | Nanoscale aligned three-dimensional stacked integrated circuits |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4748859B2 (en) * | 2000-01-17 | 2011-08-17 | 株式会社半導体エネルギー研究所 | Method for manufacturing light emitting device |
| WO2003010825A1 (en) * | 2001-07-24 | 2003-02-06 | Seiko Epson Corporation | Transfer method, method of manufacturing thin film element, method of manufacturing integrated circuit, circuit substrate and method of manufacturing the circuit substrate, electro-optic device and method of manufacturing the electro-optic device, and ic card and electronic equipmen |
-
2005
- 2005-06-24 JP JP2005185380A patent/JP4912627B2/en not_active Expired - Fee Related
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