JP2006121060A5 - - Google Patents

Download PDF

Info

Publication number
JP2006121060A5
JP2006121060A5 JP2005275070A JP2005275070A JP2006121060A5 JP 2006121060 A5 JP2006121060 A5 JP 2006121060A5 JP 2005275070 A JP2005275070 A JP 2005275070A JP 2005275070 A JP2005275070 A JP 2005275070A JP 2006121060 A5 JP2006121060 A5 JP 2006121060A5
Authority
JP
Japan
Prior art keywords
layer
substrate
thin film
conductive layer
film transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2005275070A
Other languages
Japanese (ja)
Other versions
JP5072208B2 (en
JP2006121060A (en
Filing date
Publication date
Application filed filed Critical
Priority to JP2005275070A priority Critical patent/JP5072208B2/en
Priority claimed from JP2005275070A external-priority patent/JP5072208B2/en
Publication of JP2006121060A publication Critical patent/JP2006121060A/en
Publication of JP2006121060A5 publication Critical patent/JP2006121060A5/ja
Application granted granted Critical
Publication of JP5072208B2 publication Critical patent/JP5072208B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Claims (7)

第1の基板上に剥離層を選択的に形成し、Selectively forming a release layer on the first substrate;
前記第1の基板及び前記剥離層に接するように第1の絶縁層を形成し、Forming a first insulating layer in contact with the first substrate and the release layer;
前記第1の絶縁層上に第1の薄膜トランジスタ及び第2の薄膜トランジスタを形成し、Forming a first thin film transistor and a second thin film transistor on the first insulating layer;
前記第1の薄膜トランジスタ及び前記第2の薄膜トランジスタ上に第2の絶縁層を形成し、Forming a second insulating layer on the first thin film transistor and the second thin film transistor;
前記第1の絶縁層及び前記第2の絶縁層に、前記第1の基板に達する第1の開口部を形成し、Forming a first opening reaching the first substrate in the first insulating layer and the second insulating layer;
前記第2の絶縁層に、前記第1の薄膜トランジスタに達する第2の開口部と、前記第2の薄膜トランジスタに達する第3の開口部と、を形成し、Forming a second opening reaching the first thin film transistor and a third opening reaching the second thin film transistor in the second insulating layer;
前記第1の開口部及び前記第2の開口部に第1の導電層を形成し、Forming a first conductive layer in the first opening and the second opening;
前記第3の開口部に第2の導電層を形成し、Forming a second conductive layer in the third opening;
前記第1の絶縁層及び前記第2の絶縁層に、前記剥離層に達する第4の開口部を形成し、Forming a fourth opening reaching the release layer in the first insulating layer and the second insulating layer;
前記第4の開口部にエッチング剤を導入して前記剥離層を除去し、Introducing an etchant into the fourth opening to remove the release layer;
前記第2の導電層と、第2の基板上に設けられた第3の導電層とが電気的に接続するように、前記第1の基板と前記第2の基板とを貼り合わせ、The first substrate and the second substrate are bonded together so that the second conductive layer and the third conductive layer provided on the second substrate are electrically connected.
前記第1の基板を剥離して、前記第2の基板に前記第1の薄膜トランジスタ及び前記第2の薄膜トランジスタを転置し、Peeling off the first substrate and transferring the first thin film transistor and the second thin film transistor to the second substrate;
前記第1の導電層と、第3の基板上に設けられた第4の導電層とが電気的に接続するように、前記第2の基板と前記第3の基板とを貼り合わせることを特徴とする半導体装置の作製方法。The second substrate and the third substrate are bonded to each other so that the first conductive layer and a fourth conductive layer provided on the third substrate are electrically connected to each other. A method for manufacturing a semiconductor device.
請求項1において、
前記剥離層として、タングステン又はモリブデンを含む層を形成することを特徴とする半導体装置の作製方法。
Oite to claim 1,
A method for manufacturing a semiconductor device, wherein a layer containing tungsten or molybdenum is formed as the separation layer.
請求項1又は請求項2において、
前記エッチング剤はフッ化ハロゲンを含む気体又は液体であることを特徴とする半導体装置の作製方法。
In claim 1 or claim 2,
The method for manufacturing a semiconductor device, wherein the etchant is a gas or a liquid containing halogen fluoride.
薄膜集積回路と、第1のアンテナ又はセンサを有する第1の基板と、第2のアンテナを有する第2の基板を有し、
前記薄膜集積回路は、前記第1の基板と前記第2の基板に挟持されていることを特徴とする半導体装置。
A thin film integrated circuit, a first substrate having a first antenna or sensor, a second substrate having a second antenna,
Wherein the thin film integrated circuit, a semiconductor device characterized by being sandwiched between the front Symbol first substrate and the front Stories second substrate.
請求項において、
前記薄膜集積回路は、前記第1のアンテナ又は前記センサ、及び前記第2のアンテナと、導電性粒子によって電気的に接続されていることを特徴とする半導体装置。
In claim 4 ,
The thin film integrated circuit, said first antenna or said sensor, and a semiconductor device, wherein said second antenna, that are electrically connected by the conductive particles.
第1の基板上に設けられた第1の導電層と、前記第1の導電層を覆う第1の絶縁層と、前記第1の絶縁層上に設けられた第1の薄膜トランジスタ及び第2の薄膜トランジスタと、前記第1の薄膜トランジスタ及び前記第2の薄膜トランジスタを覆う第2の絶縁層と、前記第2の絶縁層上に設けられた第2の導電層及び第3の導電層と、第2の基板上に設けられた第4の導電層を有し、
前記第2の導電層は、前記第2の絶縁層に設けられた第1の開口部を介して前記第1の薄膜トランジスタに電気的に接続され、且つ前記第1の絶縁層及び前記第2の絶縁層に設けられた第2の開口部を介して前記第1の導電層に電気的に接続され
前記第3の導電層は、前記第2の絶縁層に設けられた第3の開口部を介して前記第2の薄膜トランジスタに電気的に接続され、且つ前記第4の導電層に電気的に接続されていることを特徴とする半導体装置。
A first conductive layer provided on the first substrate; a first insulating layer covering the first conductive layer; a first thin film transistor provided on the first insulating layer; A thin film transistor; a second insulating layer covering the first thin film transistor and the second thin film transistor; a second conductive layer and a third conductive layer provided on the second insulating layer; A fourth conductive layer provided on the substrate;
The second conductive layer, said second electrically connected to said first thin film transistor motor via a first opening provided in the insulating layer, and the first insulating layer and the first Electrically connected to the first conductive layer through a second opening provided in the two insulating layers ;
Said third conductive layer, the third is the opening electrically connected to the second thin film transistor motor via, and electrically to said fourth conductive layer provided on the second insulating layer wherein a that it is connected to.
請求項6において、In claim 6,
前記第1の基板と前記第1の絶縁層との間には第1の樹脂層が設けられ、前記第1の樹脂層に含まれる導電性粒子によって前記第1の導電層と前記第2の導電層とが電気的に接続されており、A first resin layer is provided between the first substrate and the first insulating layer, and the first conductive layer and the second layer are formed by conductive particles contained in the first resin layer. The conductive layer is electrically connected,
前記第2の基板と前記第2の絶縁層との間には第2の樹脂層が設けられ、前記第2の樹脂層に含まれる導電性粒子によって前記第3の導電層と前記第4の導電層とが電気的に接続されていることを特徴とする半導体装置。A second resin layer is provided between the second substrate and the second insulating layer, and the third conductive layer and the fourth conductive layer are formed by conductive particles contained in the second resin layer. A semiconductor device, wherein the conductive layer is electrically connected.
JP2005275070A 2004-09-24 2005-09-22 Method for manufacturing semiconductor device Expired - Fee Related JP5072208B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005275070A JP5072208B2 (en) 2004-09-24 2005-09-22 Method for manufacturing semiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2004278548 2004-09-24
JP2004278548 2004-09-24
JP2005275070A JP5072208B2 (en) 2004-09-24 2005-09-22 Method for manufacturing semiconductor device

Publications (3)

Publication Number Publication Date
JP2006121060A JP2006121060A (en) 2006-05-11
JP2006121060A5 true JP2006121060A5 (en) 2008-11-06
JP5072208B2 JP5072208B2 (en) 2012-11-14

Family

ID=36538601

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005275070A Expired - Fee Related JP5072208B2 (en) 2004-09-24 2005-09-22 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP5072208B2 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101385039B (en) * 2006-03-15 2012-03-21 株式会社半导体能源研究所 Semiconductor device
JP5052079B2 (en) * 2006-09-08 2012-10-17 株式会社半導体エネルギー研究所 Sensor device and containers having the same
JP5210613B2 (en) * 2006-12-27 2013-06-12 株式会社半導体エネルギー研究所 Semiconductor device
JP5179858B2 (en) 2007-01-06 2013-04-10 株式会社半導体エネルギー研究所 Semiconductor device
US8816484B2 (en) * 2007-02-09 2014-08-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2008217776A (en) * 2007-02-09 2008-09-18 Semiconductor Energy Lab Co Ltd Semiconductor device
EP1970951A3 (en) * 2007-03-13 2009-05-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
TWI476927B (en) * 2007-05-18 2015-03-11 Semiconductor Energy Lab Methdo for manufacturing semiconductor device
EP2001047A1 (en) * 2007-06-07 2008-12-10 Semiconductor Energy Laboratory Co, Ltd. Semiconductor device
JP5072709B2 (en) * 2008-05-20 2012-11-14 京セラドキュメントソリューションズ株式会社 Image forming apparatus and consumable unit
JP5586920B2 (en) * 2008-11-20 2014-09-10 株式会社半導体エネルギー研究所 Method for manufacturing flexible semiconductor device
JP6580863B2 (en) 2014-05-22 2019-09-25 株式会社半導体エネルギー研究所 Semiconductor devices, health management systems

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4748859B2 (en) * 2000-01-17 2011-08-17 株式会社半導体エネルギー研究所 Method for manufacturing light emitting device
JP2002353235A (en) * 2001-05-23 2002-12-06 Matsushita Electric Ind Co Ltd Active matrix substrate, display using the same, and its manufacturing method
JP4244120B2 (en) * 2001-06-20 2009-03-25 株式会社半導体エネルギー研究所 Light emitting device and manufacturing method thereof
JP3972825B2 (en) * 2003-01-28 2007-09-05 セイコーエプソン株式会社 Manufacturing method of active matrix display device

Similar Documents

Publication Publication Date Title
JP2006121060A5 (en)
JP2009158939A5 (en)
JP2008181493A5 (en)
JP2006019717A5 (en)
WO2006124295A3 (en) Backside method and system for fabricating semiconductor components with conductive interconnects
JP2006189853A5 (en)
WO2007133302A3 (en) Semiconductor components and systems having encapsulated through wire interconnects (twi) and wafer level methods of fabrication
EP1337136A3 (en) Connecting member between wiring films, manufacturing method thereof, and manufacturing method of multilayer wiring substrate
JP2010087494A5 (en) Semiconductor device
JP2005228304A5 (en)
TW200704582A (en) Semiconductor composite device and method of manufacturing the same
JP2013229584A5 (en) SIGNAL PROCESSING DEVICE, DISPLAY DEVICE MANUFACTURING METHOD, DRIVE CIRCUIT, SIGNAL PROCESSING DEVICE, DISPLAY DEVICE
WO2009023349A3 (en) Integrated nanotube and cmos devices for system-on-chip (soc) applications and method for forming the same
JP2009038358A5 (en)
JP2010015550A5 (en)
WO2009020240A3 (en) Semiconductor device and method for manufacturing the same
JP2005311333A5 (en)
EP1953842A3 (en) Phase change memory device and method for fabricating the same
WO2006036751A3 (en) Integrated circuit and method for manufacturing
JP2007157787A5 (en)
JP2009532874A5 (en)
JP2006309738A5 (en)
JP2007096277A5 (en)
JP2006173596A5 (en)
TWI265570B (en) Semiconductor device with composite etch stop layer and fabrication method thereof