JP2006041256A - Semiconductor device and its manufacturing process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device exhibiting excellent reliability by preventing fatigue fracture without increasing power consumption and without increasing manufacturing cost due to increase in man-hour. <P>SOLUTION: The semiconductor device 1 comprises a semiconductor element 2, a circuit metal plate 5 and an insulating plate 7 wherein the semiconductor element 2 is bonded to one major surface of the circuit metal plate 5 through braze filler, the insulating plate 7 is bonded to the other major surface of the circuit metal plate 5 through braze filler, a first braze filler layer 4 is formed between the semiconductor element 2 and the circuit metal plate 5, and a second braze filler layer 6 is formed between the circuit metal plate 5 and the insulating plate 7. Furthermore, a rigid plate 3 having an opening 3a capable of surrounding the semiconductor element 2 is provided and bonded to one major surface of the circuit metal plate 5 through braze filler while surrounding the semiconductor element 2 by the opening 3a. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device in which a semiconductor element is brazed to one main surface of a circuit metal plate and an insulating plate is brazed to the other main surface of the circuit metal plate, and a method for manufacturing the semiconductor device. .

  Conventional semiconductor elements have been used to control a current of about several mA as a signal, but in recent years, they have played a role as a high-speed switch that controls a current of several hundred A. As a result, the amount of heat generated by the semiconductor element increases, and the thermal stress applied to the junction between the semiconductor element and the circuit metal plate tends to increase. And it is easy to generate | occur | produce the fatigue failure of a semiconductor device by applying this thermal stress repeatedly.

  The cause of such thermal stress is that there is a large difference between the thermal expansion coefficient of the semiconductor element and the thermal expansion coefficient of the brazing material to which the element is bonded and the thermal expansion coefficient of the circuit metal plate to which the element is bonded. This is because there exists. Specifically, the thermal expansion coefficient of the semiconductor element is 2.6 ppm / K for a silicon (Si) semiconductor and 3.5 ppm / K for a silicon carbide (SiC) semiconductor, for example. As the expansion coefficient, for example, Pb-63Sn solder alloy is 24.7 ppm / K, and as the thermal expansion coefficient of the circuit metal plate, for example, copper (Cu) is 17 ppm / K and aluminum (Al) is 24 ppm / K. .

  In order to relieve the thermal stress accompanying such thermal expansion, low thermal expansion such as Fe-Ni alloy, molybdenum (Mo), tungsten (W), etc. having an intermediate thermal expansion coefficient between the semiconductor element and the circuit metal plate There are known technologies for joining a stress buffer plate made of a metal material with a coefficient between a semiconductor element and a circuit metal plate and for suppressing the temperature rise around the element by improving the heat dissipation capability of the semiconductor device. ing.

  However, in the technique using the stress buffer plate, the electric power consumed by the semiconductor element increases because the electric resistance of the low thermal expansion coefficient metal material itself constituting the buffer plate is high. In addition, since molybdenum and tungsten are expensive themselves, there is a problem that they are not suitable for mass production.

On the other hand, as a specific technique for improving the heat dissipation capability, a method in which the portion immediately below the element of the metal support plate of the semiconductor device is made of a metal material having high thermal conductivity and the other portion is made of another metal material having high rigidity. Is known (see, for example, Patent Document 1). However, in this method, since two or more kinds of metal members are used for the metal support plate, man-hours for joining them are required, and the production cost increases.
JP-A-9-82858

An object of the present invention is to provide a semiconductor device excellent in reliability by preventing fatigue failure without increasing power consumption or increasing production costs due to an increase in man-hours, and a method for manufacturing the semiconductor device. .
In order to achieve the above object, according to the present invention, there is provided a semiconductor element, a circuit metal plate, and an insulating plate, and the semiconductor element is joined to one main surface of the circuit metal plate by a brazing material, A semiconductor device in which the insulating plate is joined to the other main surface of the plate by a brazing material, and further includes a rigid plate in which an opening having a shape capable of surrounding the periphery of the semiconductor element is formed, The rigid plate is provided with a semiconductor device joined to one main surface of the circuit metal plate by a brazing material while surrounding the periphery of the semiconductor element by the opening.

  In the present invention, a rigid plate having an opening that can surround the periphery of a semiconductor element is joined to a circuit metal plate with a brazing material, and the circuit metal plate is sandwiched between the rigid plate and the insulating plate. , Mechanically constrain the brazing material layer made of the brazing material and the circuit metal plate. As a result, the thermal expansion of the circuit metal plate and the brazing material layer is suppressed, and the stress concentration caused by the thermal expansion is alleviated, so that fatigue breakdown of the semiconductor device is prevented and the reliability is improved.

BEST MODE FOR CARRYING OUT THE INVENTION

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
FIG. 1 is a top plan view showing a semiconductor device according to the first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II in FIG.

  As shown in FIGS. 1 and 2, the semiconductor device 1 according to the first embodiment of the present invention has a semiconductor element 2 such as a transistor element or a diode element, and the semiconductor element 2 joined to one main surface with a brazing material. The circuit metal plate 5, the insulating plate 7 joined to the other main surface of the circuit metal plate 5 with a brazing material, and the surface opposite to the surface joined to the circuit metal plate 5 of the insulating plate 7. A first heat sink material layer 4 between the semiconductor element 2 and the circuit metal plate 5, and a second heat sink material between the circuit metal plate 5 and the insulating plate 7. A layer 6 is formed, and a third brazing material layer 8 is formed between the insulating plate 7 and the heat sink 9.

  Although not particularly shown in FIG. 2, it is a bonding interface between the semiconductor element 2, a rigid plate 3, a circuit metal plate 5, an insulating plate 7, and a heat sink 9, which will be described later, and is weakly bonded to the brazing material. Is subjected to metallization treatment by a technique such as vapor deposition, plating or sputtering, as necessary.

  The circuit metal plate 5 is made of a material having low electrical resistance, such as a metal such as copper, aluminum, iron or silver, or an alloy containing at least one of these metals.

  In order to dissipate heat from the semiconductor element 2, the heat sink 9 is made of a material having excellent thermal conductivity such as a metal such as iron, copper, aluminum, or silver, or an alloy containing at least one of these metals. .

On the other hand, the insulating plate 7 is made of, for example, aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), silicon carbide (SiC), or the like in order to insulate the conductive circuit metal plate 5 from the heat sink 9. It is comprised with the material excellent in electrical insulation, such as a composite material containing.

  Furthermore, the semiconductor device 1 according to the present embodiment has a rigid plate 3 as shown in FIGS. As shown in the figure, the rigid plate 3 is a flat plate member in which an opening 3 a having a shape capable of surrounding the periphery of the semiconductor element 2 is formed. The rigid plate 3 is joined to one main surface of the circuit metal plate 5 by a brazing material while surrounding the periphery of the semiconductor element 2 by the opening 3a, and between the rigid plate 3 and the circuit metal plate 5, The above-mentioned first brazing material layer 4 is formed so as to spread. The shape of the opening 3a is not particularly limited as long as it can surround the periphery of the semiconductor element 2, and is circular (see the opening 3a at the top of FIG. 1) as shown in FIG. Alternatively, it may have a rectangular shape (see the opening 3a in the lower part of FIG. 1).

  Thus, in the present embodiment, the first metal layer 4, the circuit metal plate 5, and the second metal layer 6 are formed by sandwiching the circuit metal plate 5 between the rigid plate 3 and the insulating plate 7. Since it is mechanically restrained and thermal expansion of the circuit metal plate 5 and the brazing material layers 4 and 6 is suppressed, fatigue failure of the semiconductor device 1 is prevented.

The rigid plate 3 is made of the same material as the insulating plate 7 such as aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), silicon carbide (SiC), or a composite material containing them. By configuring the rigid plate 3 with the same material as the insulating plate 7, the occurrence of warpage caused by the difference between the thermal expansion coefficient of the material constituting the rigid plate 3 and the thermal expansion coefficient of the material constituting the insulating plate 7 is suppressed. I can do it. Note that the rigid plate 3 is not required to have electrical insulation like the insulating plate 7, and may be made of a conductive material such as an Fe-Ni alloy.

  In addition, the rigid plate 3 has a function of suppressing thermal expansion by sandwiching the circuit metal plate 5 and the brazing material layers 4 and 6 between the insulating plate 7 as described above. It is preferable that the Young's modulus is greater than that of the first and second brazing material layers 4 and 6 and that the coefficient of thermal expansion is smaller than that of the circuit metal plate 5 and the first and second brazing material layers 4 and 6.

  In the present embodiment, as shown in FIG. 2, since the periphery of the semiconductor element 2 is surrounded by the rigid plate 3, the first main surface of the circuit metal plate 5 and the rigid plate 3 are joined together. The thickness of the non-contact portion 4 a that is not in contact with the rigid plate 3 in the saddle material layer 4 can be relatively increased with respect to the thickness of the contact portion 4 b that is in contact with the rigid plate 3. It has become.

  As a result, the non-contact portion 4a of the first brazing material layer 4 located immediately below and around the semiconductor element 2 by the opening 3a of the rigid plate 3 joined to the circuit metal plate 5 is formed by the opening 3a of the rigid plate 3. Since it is enclosed, thermal expansion of the non-contact portion 4a is suppressed, and stress concentration caused by thermal expansion is alleviated.

  Further, since the stress buffering action generally increases as the thickness of the brazing material layer increases, in the present embodiment, the first contact layer 4a of the first brazing material layer 4 is made thicker than the contact portion 4b. Since the stress buffering action of the brazing material layer 4 is enhanced, the non-contact portion 4a of the semiconductor element 2 or the first brazing material layer 4 even when the circuit metal plate 5 is thermally expanded or warped due to a temperature change. The stress concentration on is relaxed. Even if the thickness of the non-contact portion 4a is increased in this way, the density of the semiconductor element 2 is larger than the density of the brazing material and is inferior in wettability, so that the semiconductor element 2 is buried in the brazing material during brazing. And is joined to the circuit metal plate 5 in a state of floating on the surface of the brazing material.

  Furthermore, in the present embodiment, the thickness of the non-contact portion 4 a of the first brazing material layer 4 is set to be relatively small with respect to the thickness of the rigid plate 3 within the operating temperature of the semiconductor element 2. Has been. Specifically, the thickness of the first brazing material layer 4a and the thickness of the rigid plate 3 are set so as to satisfy the following formula (1).

T _max · (α _r · L _r −α _g · L _g ) <(L _g −L _r ) (1)
However, in the above formula (1), T _max is the maximum operating temperature of the semiconductor element 2, L _r is a non-contact portion 4a of the first brazing filler metal layer 4 at room temperature thick, alpha _r is the brazing filler metal heat The expansion coefficient, L _g is the thickness of the rigid plate 3 at normal temperature, and α _g is the thermal expansion coefficient of the rigid plate 3.

  As described above, the brazing material constituting the first brazing material layer 4 has a larger coefficient of thermal expansion than that of the rigid plate 3, so that when the temperature becomes high, the thickness of the non-contact portion 4a of the first brazing material layer 4 is the rigid plate. In some cases, the non-contact portion 4 a of the first brazing material layer 4 protrudes from the upper surface of the rigid plate 3. In this case, since the non-contact portion 4a of the first brazing material layer 4 is not restrained by the opening 3a of the rigid plate 3, thermal expansion of the non-contact portion 4a is not suppressed.

  On the other hand, in the present embodiment, the thickness of the non-contact portion 4a of the first brazing material layer 4 is always set smaller than the thickness of the rigid plate 3 within the operating temperature of the semiconductor element 2 as described above. Thus, since the brazing material of the non-contact portion 4a can be always restrained by the opening 3a of the rigid plate 3, the thermal expansion of the non-contact portion 4a of the first brazing material layer 4 is suppressed, and the heat Stress concentration due to expansion is alleviated.

  The specific thickness of the non-contact portion 4a of the first brazing material layer 4 can be set to about several millimeters, which is a limit for increasing the stress buffering effect, but is several in consideration of the electrical resistance of the brazing material. It is good also as about 100 micrometers-1 mm.

  The brazing material constituting the first brazing material layer 4 is made of a material having a low Young's modulus, a low electrical resistance and a low thermal resistance, such as an aluminum brazing, a silver brazing, and solder.

  The brazing material constituting the second brazing material layer 6 is preferably the same as the brazing material constituting the first brazing material layer 4, but may be a different material as long as the solid phase temperature is approximately the same. As a result, as will be described later, the semiconductor element 2, the rigid plate 3, the circuit metal plate 5, and the insulating plate 7 can be brazed simultaneously at the time of manufacturing the semiconductor device 1.

  The Young's modulus of the brazing material constituting the first brazing material layer 4 and the second brazing material layer 6 is preferably not more than the Young's modulus of the circuit metal plate 5. As a result, the stress buffering action is enhanced, so that the stress concentration can be relaxed when the circuit metal plate 5 is thermally expanded or warped due to a temperature change.

  The manufacturing method of the semiconductor device 1 described above will be described. First, before performing brazing, an electrode is formed in advance on the opposite surface of the surface of the semiconductor element 2 to which the brazing material is bonded, such as aluminum. In some cases, the predetermined bonding interface is metallized by a technique such as vapor deposition, plating, or sputtering.

  Next, the sheet-like brazing material is sandwiched between the semiconductor element 2 and the rigid plate 3 and the circuit metal plate 5 and is also sandwiched between the circuit metal plate 5 and the insulating plate 7. Layer 6, circuit metal plate 5, first brazing material layer 4, semiconductor element 2, and rigid plate 3 are laminated in this order. At this time, in order to thicken the non-contact portion 4a of the first brazing material layer 4, a sheet-like brazing material corresponding to the shape of the opening 3a of the rigid plate 3 is previously laid directly under and around the semiconductor element 2. deep.

  Next, a pressing force is applied to the rigid plate 3 from above, and the ambient temperature is raised to the solid phase temperature of the first brazing material layer 4 and the second brazing material layer 6 while maintaining the state. When the brazing material is melted, the temperature is lowered and the pressing force applied to the rigid plate 3 is released. Thereafter, the sheet-shaped brazing material is sandwiched between the insulating plate 7 and the heat sink 9 to melt the brazing material to form the third brazing material layer 8, whereby the semiconductor device 1 is manufactured.

  Thus, the brazing of the semiconductor element 2 and the rigid plate 3 and the circuit metal plate 5 and the brazing of the circuit metal plate 5 and the insulating plate 7 are performed at the same time, so that the brazing that is normally performed twice is performed. Since it can be reduced at once, the cost can be reduced by reducing man-hours.

  Further, when the circuit metal plate 5 is brazed one side at a time, warpage occurs. However, by curling both surfaces of the circuit metal plate 5 at the same time, the warpage is reduced, and the stress generated by the warpage is reduced.

  Further, since the pressing force is applied to the rigid plate 3 and the insulating plate 7 along the direction substantially orthogonal to the circuit metal plate 5, the thickness of the first brazing material layer 4 that is thicker than other portions is not increased. The brazing material of the contact portion 4a does not enter the contact portion 4b and the non-contact portion 4a is not thinned.

  In addition to being directly brazed to the insulating plate 7, the heat sink 9 may be mechanically fixed to the supporting plate by bolting or the like by interposing a supporting plate or the like between the insulating plate 7 and the like. .

[Second Embodiment]
FIG. 3 is a view corresponding to FIG. 2 for explaining the second embodiment of the present invention, and the same reference numerals denote the same parts as those described in the first embodiment.

 In the present embodiment, as shown in FIG. 3, only the metallized surface 4 b substantially parallel to the circuit metal plate 5 among the surfaces to which the first brazing material layer 4 of the rigid plate 3 is joined is subjected to vapor deposition treatment or Metallization is performed by a technique such as plating or sputtering, and the other surfaces, particularly the inner wall surface of the opening 3a, are not metallized.

  For example, the rigid plate 3 made of ceramics, Fe—Ni alloy, molybdenum, tungsten, or the like may not be bonded to a brazing material such as an aluminum rod, a silver plate, or solder unless the bonding surface is metallized. Even if it joins, it becomes easy to peel. For this reason, by not intentionally metallizing the inner wall surface of the opening 3a, the non-contact portion 4a of the first brazing material layer 4 expands and contracts relatively freely along the vertical direction with respect to the circuit metal plate 5. Therefore, compared with the case where the entire joining surface of the rigid plate 3 is metallized, the thermal stress generated in the first brazing material layer 4 is reduced.

[Third Embodiment]
FIG. 4 is a view corresponding to FIG. 2 for explaining the third embodiment of the present invention, and the same reference numerals denote the same parts as those described in the first embodiment.

 In the present embodiment, as shown in FIG. 4, the peripheral edge 3 c on the circuit metal plate 5 side is formed in a curved shape at the peripheral edge of the opening 3 a formed in the rigid plate 3. If there is a pointed corner at the joint interface between the rigid plate 3 and the first brazing material layer 4, stress tends to concentrate there, but in this embodiment, a curved surface is formed around the opening 3 a of the rigid plate 3. The stress concentration is relaxed by forming the curved surface portion 3c and eliminating the corner portion.

  The embodiment described above is described for facilitating the understanding of the present invention, and is not described for limiting the present invention. Therefore, each element disclosed in the above embodiment is intended to include all design changes and equivalents belonging to the technical scope of the present invention.

1 is an upper plan view showing a semiconductor device according to a first embodiment of the present invention. It is sectional drawing along the II-II line of FIG. It is sectional drawing which shows the semiconductor device which concerns on 2nd Embodiment of this invention. It is sectional drawing which shows the semiconductor device which concerns on 3rd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 2 ... Semiconductor element 3 ... Rigid board 3a ... Opening 3b ... Metallized surface 3c ... Curved surface part 4 ... 1st brazing material layer 4a ... Non-contact part 4b ... Contact part 5 ... Circuit metal plate 6 ... 2nd Brazing material layer 7 ... Insulating plate 8 ... Third brazing material layer 9 ... Heat sink

Claims (8)

A semiconductor element, a circuit metal plate, and an insulating plate, wherein the semiconductor element is bonded to one main surface of the circuit metal plate with a brazing material, and the insulating plate is bonded to the other main surface of the circuit metal plate with a brazing material. A bonded semiconductor device comprising:
A rigid plate formed with an opening having a shape capable of surrounding the periphery of the semiconductor element;
The rigid plate is a semiconductor device that is joined to one main surface of the circuit metal plate by a brazing material while surrounding the periphery of the semiconductor element by the opening.   The thickness of the non-contact portion that is not in contact with the rigid plate out of the brazing material layer made of the brazing material joining the one main surface of the circuit metal plate and the rigid plate is in contact with the rigid plate. The semiconductor device according to claim 1, wherein the thickness of the contact portion is relatively large with respect to the thickness of the contact portion.   The semiconductor device according to claim 1, wherein the rigid plate has a Young's modulus larger than that of the circuit metal plate and a thermal expansion coefficient smaller than that of the circuit metal plate.   4. The semiconductor device according to claim 2, wherein a thickness of a non-contact portion of the brazing material layer is relatively smaller than a thickness of the rigid plate within an operating temperature of the semiconductor element.   At least one of the brazing material joining one main surface of the circuit metal plate and the rigid plate, or the joining material joining the other main surface of the circuit metal plate and the insulating plate, The semiconductor device according to claim 1, which has a Young's modulus smaller than that of the circuit metal plate.   6. The semiconductor device according to claim 1, wherein only a surface substantially parallel to the circuit metal plate among the surfaces bonded to the brazing material of the rigid plate is metallized.   The semiconductor device according to claim 1, wherein a periphery of the opening formed in the rigid plate is formed in a curved shape. A method for manufacturing a semiconductor device for manufacturing the semiconductor device according to claim 1,
While applying a pressing force to the rigid plate and the insulating plate along a direction substantially perpendicular to the main surface of the circuit metal plate, one of the semiconductor element, the rigid plate, and the circuit metal plate A method for manufacturing a semiconductor device, wherein the brazing with the main surface and the brazing between the other main surface of the circuit metal plate and the insulating plate are performed simultaneously.

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