JP2006014088A - 伝送線路基板および半導体パッケージ - Google Patents
伝送線路基板および半導体パッケージ Download PDFInfo
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- JP2006014088A JP2006014088A JP2004190315A JP2004190315A JP2006014088A JP 2006014088 A JP2006014088 A JP 2006014088A JP 2004190315 A JP2004190315 A JP 2004190315A JP 2004190315 A JP2004190315 A JP 2004190315A JP 2006014088 A JP2006014088 A JP 2006014088A
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Abstract
【解決手段】半導体デバイスに接続される駆動制御信号の信号線路を2つの等位相の信号線路に分配する分配器51と、分配された信号線路の一方につながり、不要波の基板内実効波長の略1/2の長さを有する信号線路を有する遅延器52と、遅延器52および分配された信号線路の他方につながり、不要波が互いに逆位相となる平行の2つの信号線路を有する平行2線路53と、平行2線路53上に配置され、平行の2つの信号線路間を接続する抵抗体55と、平行2線路53の2つの信号線路を合成する信号線路を有し、合成信号を外部に出力する合成器54とを有する不要波抑制回路50を備える。
【選択図】 図6−1
Description
図1〜図3はこの発明にかかる半導体パッケージ1を示すものである。この発明は、任意の周波数帯で動作する半導体デバイス(半導体IC)が搭載された半導体パッケージに適用可能であるが、ここではマイクロ波帯、ミリ波帯などの高周波帯で動作する複数の高周波半導体デバイス(MMIC、以下高周波デバイスと略す)が搭載される半導体パッケージ(以下、高周波パッケージという)1に本発明を適用した場合を示している。半導体パッケージ1は、例えば、FM−CWレーダに適用して好適である。
図8は実施の形態2の高周波パッケージ95を示すものである。実施の形態2においては、図8に示すように、実施の形態1の不要波抑制回路50(50a〜50c)を複数個、縦続接続するようにしており、これにより不要波の減衰率,吸収率を向上させるようにしている。
つぎに、図9〜図12を用いてこの発明の実施の形態3について説明する。この実施の形態3の高周波パッケージ100においては、図9および図10に示すように、内層信号線路45には、不要波の基板内実効波長λgの1/4の長さを有する先端開放スタブ70を設けるとともに、この先端開放スタブ70と内層信号線路45との接続位置の上層及び下層、あるいは上下層のいずれか一方の内層接地導体35に不要波の基板内実効波長λgの1/2の長さを有する結合スロット(内層接地導体35の抜き部分)75を形成し、この結合スロット75上に抵抗体(印刷抵抗)80を形成するようにしている。図9の場合は、先端開放スタブ70が形成された内層信号線路45の上層にのみ結合スロット75を形成し、この結合スロット75に抵抗体80を塗布するようにしている。このように実施の形態3の不要波抑制回路90は、先端開放スタブ70、結合スロット75および抵抗体80によって構成されている。
2 多層誘電体基板
3 高周波デバイス(半導体デバイス、半導体IC)
4 シールリング
5 カバー
6 IC搭載凹部
6a 側壁
7 フィードスルー
8 マイクロストリップ線路
10 内部導体パッド
11 導体パッド
12 ワイヤ
15 外部導体パッド
16 グランド面
17 半田
18 グランドパターン
20 キャリア
30,30b,30c グランドビア
30a 側壁グランドビア
33 キャビティ
35 内層接地導体
40,40a,40b 信号ビア
45,45a,45b 内層信号線路
50,50a,50b,50c 不要波抑制回路
51 分配器
52 遅延器
53 平行2線路
54 合成器
55 抵抗体
60 誘電体
70 先端開放スタブ
75 結合スロット
80 抵抗体
85 結合スロット
85a スロット線路
90 不要波抑制回路
Claims (11)
- 半導体デバイスに入出力される信号を伝送する伝送線路基板において、
前記半導体デバイスに接続される信号線路を2つの等位相の信号線路に分配する分配器と、
前記分配された信号線路の一方につながり、不要波の基板内実効波長の略1/2の長さを有する信号線路を有する遅延器と、
前記遅延器および前記分配された信号線路の他方につながり、不要波が互いに逆位相となる平行の2つの信号線路を有する平行2線路と、
前記平行2線路上に配置され、平行の2つの信号線路間を接続する抵抗体と、
前記平行2線路の2つの信号線路を合成する合成器と、
を有する不要波抑制回路を備えることを特徴とする伝送線路基板。 - 前記分配器、遅延器、平行2線路および合成器は、上下の接地導体層間に信号線路が形成されるトリプレート線路により構成されることを特徴とする請求項1に記載の伝送線路基板。
- 前記不要波抑制回路を複数個、縦続接続し、前記複数の不要波抑制回路の各遅延器の信号線路の長さを、異なる周波数を持つ複数の不要波の基板内実効波長の略1/2となるように、それぞれ異ならせたことを特徴とする請求項1または2に記載の伝送線路基板。
- 半導体デバイスに入出力される信号を伝送する伝送線路を有し、信号線路の上下層に接地導体を配置したトリプレート線路として伝送線路を形成した伝送線路基板において、
前記信号線路に並列に接続され、不要波の基板内実効波長の略1/4の奇数倍の長さを有する先端開放スタブと、
該先端開放スタブと信号線路との接続位置の上下層、あるいは上下層のいずれか一方の接地導体に形成され、前記接続位置の周辺で定在波分布が開放となって前記信号線路と結合する結合スロットと、
該結合スロット上の少なくとも一部に設けられた抵抗体と、
を備えることを特徴とする伝送線路基板。 - 半導体デバイスに入出力される信号を伝送する伝送線路を有し、信号線路の上下層に接地導体を配置したトリプレート線路として伝送線路を形成した伝送線路基板において、
前記信号線路に並列に接続されるラジアルスタブと、
該ラジアルスタブと信号線路との接続位置の上下層、あるいは上下層のいずれか一方の接地導体に形成され、前記接続位置の周辺で定在波分布が開放となって前記信号線路と結合する結合スロットと、
該結合スロット上の少なくとも一部に設けられた抵抗体と、
を備えることを特徴とする伝送線路基板。 - 前記結合スロットは、前記接続位置から一方が不要波の基板内実効波長の略1/4の奇数倍の長さを有し、前記接続位置から他方が少なくとも前記基板内実効波長の略1/4の長さを有することを特徴とする請求項4または5に記載の伝送線路基板。
- 前記結合スロットは、前記接続位置に開放点が一致するように配置され、不要波の基板内実効波長の略1/2の長さを有し、前記抵抗体は該結合スロット上の全面に形成されることを特徴とする請求項4または5に記載の伝送線路基板。
- 前記スタブと結合スロットとを有する不要波抑制回路を、複数個、縦続接続し、当該複数の不要波抑制回路における結合スロットの長さを、異なる周波数を持つ複数の不要波の基板内実効波長の略1/2となるように、それぞれ異ならせたことを特徴とする請求項4〜7のいずれか一つに記載の伝送線路基板。
- 前記信号線路が不要波の基板内実効波長の1/4以下の間隔で配置される複数のグランドビアで囲まれていることを特徴とする請求項1〜8のいずれか一つに記載の伝送線路基板。
- 1〜複数の半導体デバイスを収容するために用いられ、請求項1〜9のいずれか一つに記載の伝送線路基板を、前記半導体デバイスの駆動制御信号端子と外部端子との接続経路に設けたことを特徴とする半導体パッケージ。
- 1〜複数の半導体デバイスと、
請求項1〜9のいずれか一つに記載の伝送線路基板と、
を備え、該伝送線路基板を、前記半導体デバイスの駆動制御信号端子と外部端子との接続経路に設けたことを特徴とする半導体パッケージ。
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EP12153563A EP2463953B1 (en) | 2004-06-28 | 2005-06-24 | Transmission line substrate and semiconductor package |
EP05765133.3A EP1777775B1 (en) | 2004-06-28 | 2005-06-24 | Transmission line substrate and semiconductor package |
PCT/JP2005/011649 WO2006001388A1 (ja) | 2004-06-28 | 2005-06-24 | 伝送線路基板および半導体パッケージ |
EP12153560.3A EP2463952B1 (en) | 2004-06-28 | 2005-06-24 | Transmission line substrate and semiconductor package |
US11/631,108 US7498907B2 (en) | 2004-06-28 | 2005-06-24 | Transmission line substrate and semiconductor package |
EP17167803.0A EP3229310A3 (en) | 2004-06-28 | 2005-06-24 | Transmission line substrate and semiconductor package |
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EP2463953B1 (en) | 2013-01-16 |
EP3252866A1 (en) | 2017-12-06 |
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EP3229310A3 (en) | 2018-01-10 |
EP2463953A1 (en) | 2012-06-13 |
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