JP2005515442A - セルフテスト回路を備えた集積回路 - Google Patents
セルフテスト回路を備えた集積回路 Download PDFInfo
- Publication number
- JP2005515442A JP2005515442A JP2003560576A JP2003560576A JP2005515442A JP 2005515442 A JP2005515442 A JP 2005515442A JP 2003560576 A JP2003560576 A JP 2003560576A JP 2003560576 A JP2003560576 A JP 2003560576A JP 2005515442 A JP2005515442 A JP 2005515442A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- test
- application circuit
- application
- test pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3187—Built-in tests
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318544—Scanning methods, algorithms and patterns
- G01R31/318547—Data generators or compressors
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (4)
- テスト対象であるアプリケーション回路と、前記アプリケーション回路をテストするため設けられ、疑似ランダムテストパターンを生成するセルフテスト回路と、を具備し、
前記疑似ランダムテストパターンは、第1の論理ゲートと当該ゲートに外部から供給された信号とによって、テスト目的のため前記アプリケーション回路へ供給される決定論的なテストベクトルに変換可能であり、
前記テストパターンに応じて前記アプリケーション回路を介して生じる出力信号はシグネチャレジスタによって推定され、
第2の論理ゲートと当該ゲートに外部から供給された信号とによって、前記アプリケーション回路の前記出力信号のビットの中で前記アプリケーション回路の回路構成のために不確定の状態を有するビットがテスト中に阻止される、
集積回路。 - 前記セルフテスト回路内に、疑似ランダムテストパターンを生成するリニアフィードバックシフトレジスタが設けられ、前記疑似ランダムテストパターンは、前記第1の論理ゲートによって、予め決定可能な決定論的なテストパターンに変換されることを特徴とする、請求項1に記載の集積回路。
- 前記第2の論理ゲートは、前記アプリケーション回路の前記出力信号のビットの中で、アナログ動作および/または蓄積動作を有する前記アプリケーション回路の回路素子による影響を受けるビットを阻止することを特徴とする、請求項1に記載の集積回路。
- 前記第1の論理ゲート及び前記第2の論理ゲートへ外部から供給される信号は、当該集積回路の外部に設けられたテスト装置から発生することを特徴とする、請求項1に記載の集積回路。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10201554A DE10201554A1 (de) | 2002-01-17 | 2002-01-17 | Integrierter Schaltkreis mit Selbsttest-Schaltung |
PCT/IB2003/000053 WO2003060534A2 (en) | 2002-01-17 | 2003-01-14 | Integrated circuit with self-testing circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2005515442A true JP2005515442A (ja) | 2005-05-26 |
Family
ID=7712336
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003560576A Pending JP2005515442A (ja) | 2002-01-17 | 2003-01-14 | セルフテスト回路を備えた集積回路 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7039844B2 (ja) |
EP (1) | EP1472552A2 (ja) |
JP (1) | JP2005515442A (ja) |
AU (1) | AU2003201066A1 (ja) |
DE (1) | DE10201554A1 (ja) |
WO (1) | WO2003060534A2 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008505310A (ja) * | 2004-06-30 | 2008-02-21 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 回路装置、及び、前記回路装置に設けられたアプリケーション回路の試験方法 |
EP2030145A2 (de) | 2006-05-30 | 2009-03-04 | Nxp B.V. | Verfahren zu kryptographischen authentikation |
US8843797B2 (en) * | 2012-06-27 | 2014-09-23 | International Business Machines Corporation | Signature compression register instability isolation and stable signature mask generation for testing VLSI chips |
CN104538060B (zh) * | 2014-12-27 | 2017-12-26 | 西安紫光国芯半导体有限公司 | 一种dram芯片的晶圆级测试结构和测试方法 |
CN105930237A (zh) * | 2016-04-13 | 2016-09-07 | 广州小微电子技术有限公司 | 一种芯片安全检测方法、芯片结构、芯片模块 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5574733A (en) * | 1995-07-25 | 1996-11-12 | Intel Corporation | Scan-based built-in self test (BIST) with automatic reseeding of pattern generator |
US5831992A (en) * | 1995-08-17 | 1998-11-03 | Northern Telecom Limited | Methods and apparatus for fault diagnosis in self-testable systems |
US5774477A (en) * | 1995-12-22 | 1998-06-30 | Lucent Technologies Inc. | Method and apparatus for pseudorandom boundary-scan testing |
US6370664B1 (en) * | 1998-10-29 | 2002-04-09 | Agere Systems Guardian Corp. | Method and apparatus for partitioning long scan chains in scan based BIST architecture |
US6557129B1 (en) | 1999-11-23 | 2003-04-29 | Janusz Rajski | Method and apparatus for selectively compacting test responses |
DE10038327A1 (de) * | 2000-08-05 | 2002-02-14 | Philips Corp Intellectual Pty | Integrierter Schaltkreis mit Selbsttest-Schaltung |
-
2002
- 2002-01-17 DE DE10201554A patent/DE10201554A1/de not_active Withdrawn
-
2003
- 2003-01-14 US US10/501,796 patent/US7039844B2/en not_active Expired - Lifetime
- 2003-01-14 JP JP2003560576A patent/JP2005515442A/ja active Pending
- 2003-01-14 WO PCT/IB2003/000053 patent/WO2003060534A2/en active Application Filing
- 2003-01-14 AU AU2003201066A patent/AU2003201066A1/en not_active Abandoned
- 2003-01-14 EP EP03729519A patent/EP1472552A2/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
WO2003060534A3 (en) | 2003-11-13 |
US7039844B2 (en) | 2006-05-02 |
WO2003060534A2 (en) | 2003-07-24 |
DE10201554A1 (de) | 2003-08-21 |
AU2003201066A1 (en) | 2003-07-30 |
AU2003201066A8 (en) | 2003-07-30 |
EP1472552A2 (en) | 2004-11-03 |
US20050050420A1 (en) | 2005-03-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100206128B1 (ko) | 선형 궤환 쉬프트레지스터, 다중 입력기호 레지스터 및 이들을 이용한 내장 자기 진단회로 | |
US6701476B2 (en) | Test access mechanism for supporting a configurable built-in self-test circuit and method thereof | |
US5617426A (en) | Clocking mechanism for delay, short path and stuck-at testing | |
US4733405A (en) | Digital integrated circuit | |
US8145964B2 (en) | Scan test circuit and scan test control method | |
US8671320B2 (en) | Integrated circuit comprising scan test circuitry with controllable number of capture pulses | |
JPH02168176A (ja) | 試験装置 | |
US5239262A (en) | Integrated circuit chip with built-in self-test for logic fault detection | |
US6789221B2 (en) | Integrated circuit with self-test circuit | |
US6789220B1 (en) | Method and apparatus for vector processing | |
US20040117705A1 (en) | Method and system for disabling a scanout line of a register flip-flop | |
JPH0786526B2 (ja) | 複数モードのテスト装置 | |
US7406639B2 (en) | Scan chain partition for reducing power in shift mode | |
JP2005515442A (ja) | セルフテスト回路を備えた集積回路 | |
JPH04313119A (ja) | 疑似乱数パタン発生器 | |
US7139953B2 (en) | Integrated circuit with test circuit | |
US4894800A (en) | Reconfigurable register bit-slice for self-test | |
JP2004004047A (ja) | 集積回路のための入力/出力特徴付けチェーン | |
JPWO2008120389A1 (ja) | メモリテスト回路、半導体集積回路およびメモリテスト方法 | |
KR100444763B1 (ko) | 내장된 자체테스트 기법을 위한 결정패턴 생성기 | |
JP5453981B2 (ja) | Lsi、及びそのテストデータ設定方法 | |
JPH0682148B2 (ja) | テストパターン発生器 | |
JPH04359175A (ja) | 半導体集積回路 | |
JP2001159663A (ja) | 集積回路におけるスキャンテスト回路 | |
JP2001174515A (ja) | 自己診断型論理集積回路の診断方法及び自己診断型論理集積回路 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20060112 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20070125 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20070130 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20070501 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20070510 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20070727 |