JP2005322852A - Tape carrier, semiconductor device and manufacturing method thereof - Google Patents

Tape carrier, semiconductor device and manufacturing method thereof Download PDF

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Publication number
JP2005322852A
JP2005322852A JP2004141401A JP2004141401A JP2005322852A JP 2005322852 A JP2005322852 A JP 2005322852A JP 2004141401 A JP2004141401 A JP 2004141401A JP 2004141401 A JP2004141401 A JP 2004141401A JP 2005322852 A JP2005322852 A JP 2005322852A
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Prior art keywords
hole
tape carrier
holes
semiconductor
sprocket
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JP2004141401A
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JP4070135B2 (en
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Yoshikazu Takahashi
高橋　　義和
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Oki Electric Industry Co Ltd
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Oki Electric Industry Co Ltd
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Priority to JP2004141401A priority Critical patent/JP4070135B2/en
Priority to US11/073,766 priority patent/US20050252828A1/en
Priority to KR1020050021315A priority patent/KR101162939B1/en
Priority to CN2005100548375A priority patent/CN1697164B/en
Publication of JP2005322852A publication Critical patent/JP2005322852A/en
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Publication of JP4070135B2 publication Critical patent/JP4070135B2/en
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49565—Side rails of the lead frame, e.g. with perforations, sprocket holes
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a means of increasing the number of semiconductor units manufacturable by a roll of tape carrier. <P>SOLUTION: A plurality of first holes 3 arranged at a prescribed pitch and second holes 17, 19 formed between the first holes are provided to edge regions 2a of a long base film 2, and the second holes are lined up on the same processions as the first holes at the same pitch. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体ユニット等の小型の電子部品を連続的に製造するときに用いるテープキャリア、半導体装置の製造方法および半導体装置に関する。   The present invention relates to a tape carrier, a semiconductor device manufacturing method, and a semiconductor device that are used when continuously manufacturing small electronic components such as semiconductor units.

従来のテープキャリアは、長尺のベースフィルムの両方の縁領域に、複数のスプロケットホールを所定のピッチで配列したテープキャリアのスプロケットホールの列の外側に群ごとに区切ったパイロットホールを穿孔し、このパイロットホールを位置決めの基準として半導体ユニット等の電子部品の製造に用いている（例えば、特許文献１参照。）。
特開２００１−１７９６９３号公報（主に第３頁段落００１２−段落００１８、第３図） In the conventional tape carrier, pilot holes that are divided into groups on the outside of a row of sprocket holes of the tape carrier in which a plurality of sprocket holes are arranged at a predetermined pitch are drilled in both edge regions of the long base film, This pilot hole is used for the manufacture of electronic parts such as a semiconductor unit with reference to positioning (for example, see Patent Document 1).
Japanese Patent Laid-Open No. 2001-179893 (mainly, page 3, paragraphs 0012-0018, FIG. 3)

しかしながら、上述した従来の技術においては、群ごとに区切ったパイロットホールにより位置決めをして半導体ユニットを製造しているため、群の間に半導体ユニットの製造のために用いることができない領域が存在し、テープキャリアに無駄が生じて１巻のテープキャリアで製造できる半導体ユニットの数が減少し、テープキャリアの交換頻度が増加して半導体ユニットの生産性が低下するという問題がある。   However, in the above-described conventional technology, the semiconductor unit is manufactured by positioning with the pilot holes divided for each group. Therefore, there is an area that cannot be used for manufacturing the semiconductor unit between the groups. There is a problem that the tape carrier is wasted and the number of semiconductor units that can be manufactured with one roll of tape carrier is reduced, the frequency of replacement of the tape carrier is increased, and the productivity of the semiconductor unit is lowered.

本発明は、上記の問題点を解決するためになされたもので、１巻のテープキャリアで製造できる半導体ユニットの数を増加させる手段を提供することを目的とする。   The present invention has been made to solve the above-described problems, and an object of the present invention is to provide means for increasing the number of semiconductor units that can be manufactured with one tape carrier.

本発明は、上記課題を解決するために、長尺のベースフィルムの縁領域に、所定のピッチで配列された複数の第１の孔と、該第１の孔の間に形成された第２の孔とを備え、該第２の孔が、前記第１の孔と同列に、かつ同一ピッチで形成されていることを特徴とする。   In order to solve the above problems, the present invention provides a plurality of first holes arranged at a predetermined pitch in an edge region of a long base film, and a second formed between the first holes. And the second holes are formed in the same row and at the same pitch as the first holes.

これにより、本発明は、半導体ユニットの配置を短い間隔で連続的に設定することができ、テープキャリアの全長を短縮してそのコストの削減を図ることができると共に、テープキャリアの交換頻度を減少させて半導体ユニットの生産性の向上を図ることができるという効果が得られる。   As a result, the present invention can continuously set the arrangement of the semiconductor units at short intervals, can reduce the overall length of the tape carrier, reduce its cost, and reduce the replacement frequency of the tape carrier. As a result, it is possible to improve the productivity of the semiconductor unit.

以下に、図面を参照して本発明によるテープキャリアの実施例について説明する。   Embodiments of a tape carrier according to the present invention will be described below with reference to the drawings.

図１は実施例１のテープキャリアを示す正面図、図２は図１のＡ−Ａ断面図である。
１はテープキャリアであり、比較的耐熱性の高いポリイミド等の樹脂材料で製作された長尺のベースフィルム２と、ベースフィルム２の両方の縁領域２ａに図示しない駆動装置で駆動されるスプロケットの歯に嵌合してテープキャリア１の図１に示す送り方向の移動やその位置決めを行うために所定のピッチＰ（本実施例では４．７５ｍｍである。このピッチＰ＝４．７５ｍｍは規格で定められた値である。）でそれぞれ１列に穿孔された複数の第１の孔であるスプロケットホール３等により構成される。 FIG. 1 is a front view showing a tape carrier of Example 1, and FIG. 2 is a cross-sectional view taken along line AA of FIG.
Reference numeral 1 denotes a tape carrier, which is a long base film 2 made of a resin material such as polyimide having a relatively high heat resistance, and a sprocket driven by a driving device (not shown) on both edge regions 2a of the base film 2. A predetermined pitch P (4.75 mm in the present embodiment. This pitch P = 4.75 mm is a standard) for moving the tape carrier 1 in the feeding direction shown in FIG. It is configured by a plurality of first holes sprocket holes 3 or the like perforated in one row.

本実施例の駆動装置の駆動モータはパルスモータであり、１パルスあたりに一定の角度回転するように設定されたモータであって、供給するパルス数によりその回転角度を制御することができるモータである。
また、駆動装置にはスプロケットの回転を停止させるための摩擦式等のブレーキが装備されている。 The drive motor of the drive device of this embodiment is a pulse motor, a motor set to rotate at a constant angle per pulse, and a motor whose rotation angle can be controlled by the number of pulses supplied. is there.
Further, the drive device is equipped with a friction type brake for stopping the rotation of the sprocket.

本実施例のスプロケットホール３は、ベースフィルム２の長手方向（単に長手方向という。）の長さを図１に示すＢとした略四角形の孔として形成されている。
なお、スプロケットホール３の形状は、略四角形に限らず、スプロケットの歯と嵌合してテープキャリア１を送り方向へ移動させる機能を有する形状であればどのような形状、例えば円形等であってもよい。 The sprocket hole 3 of the present embodiment is formed as a substantially rectangular hole whose length in the longitudinal direction (simply referred to as the longitudinal direction) of the base film 2 is B shown in FIG.
Note that the shape of the sprocket hole 3 is not limited to a substantially square shape, and any shape, for example, a circle or the like, may be used as long as it has a function of fitting the sprocket teeth and moving the tape carrier 1 in the feeding direction. Also good.

４は半導体ユニットとしてのＴＣＰ（Ｔａｐｅ Ｃａｒｒｉｅｒ Ｐａｃｋａｇｅ）型半導体ユニットであり、ベースフィルム２の両方の縁領域２ａの間の半導体搭載領域２ｂのカットエリア５をテープキャリア１から打抜いて形成される。
ＴＣＰ型半導体ユニット４は、カットエリア５で打抜いた後の位置合わせに用いるアライメントホール６、入力端子側アウターリード７、出力端子側アウターリード８、回路素子およびこの回路素子に電気的に接続されたボンディングパッドに形成された電極としてのバンブ電極９を有する半導体素子１０、バンブ電極９と入力端子側アウターリード７および出力端子側アウターリード８とを接続する配線パターンであるインナーリード１１、インナーリード１１による配線パターンを保護するためのソルダーレジスト１２、半導体素子１０とインナーリード１１を保護するための封止樹脂１３、入力端子側アウターリード７および出力端子側アウターリード８をベースフィルム２に貼付するための接着剤１４により構成される。 Reference numeral 4 denotes a TCP (Tape Carrier Package) type semiconductor unit as a semiconductor unit, which is formed by punching a cut area 5 of a semiconductor mounting region 2b between both edge regions 2a of the base film 2 from the tape carrier 1.
The TCP type semiconductor unit 4 is electrically connected to the alignment hole 6, the input terminal side outer lead 7, the output terminal side outer lead 8, the circuit element, and the circuit element used for alignment after punching in the cut area 5. A semiconductor element 10 having a bump electrode 9 as an electrode formed on the bonding pad, an inner lead 11 which is a wiring pattern for connecting the bump electrode 9 to the input terminal side outer lead 7 and the output terminal side outer lead 8; A solder resist 12 for protecting the wiring pattern by 11, a sealing resin 13 for protecting the semiconductor element 10 and the inner lead 11, an input terminal side outer lead 7 and an output terminal side outer lead 8 are affixed to the base film 2. It is comprised by the adhesive agent 14 for.

１５はテストパッドであり、出力端子側アウターリード８に接続してテープキャリア１上でのＴＣＰ型半導体ユニット４の電気検査に用いられる。
１７は第２の孔としての補助割出孔であり、テープキャリア１の送り方向の位置決めを細かく行うためにスプロケットホール３の間に設けられた図１に太い実線で示す略四角形の孔であって、スプロケットホール３と同列で、長手方向の長さを同一の長さＢにして形成されており、補助割出孔１７間のピッチはスプロケットホール３のピッチＰと同一に設定されている。 A test pad 15 is connected to the output terminal side outer lead 8 and used for electrical inspection of the TCP type semiconductor unit 4 on the tape carrier 1.
Reference numeral 17 denotes an auxiliary index hole as a second hole, which is a substantially rectangular hole shown by a thick solid line in FIG. 1 provided between the sprocket holes 3 in order to finely position the tape carrier 1 in the feed direction. The sprocket holes 3 are formed in the same row with the same length B in the longitudinal direction, and the pitch between the auxiliary index holes 17 is set to be the same as the pitch P of the sprocket holes 3.

本実施例の補助割出孔１７は、スプロケットホール３間の中央、つまりスプロケットホール３と補充割出孔１７との距離がピッチＰの半分（本実施例では２．３７５ｍｍ）になるように形成されている。
１８はエッジ検出センサであり、図示しない製造装置の作業台等に設けられた発光部と受光部とをスプロケットホール３の列上でテープキャリア１を挟んで対向させた光学式のセンサ等であって、スプロケットホール３または補助割出孔１７のテープキャリア１の送り方向の前縁が発光部からの光を透過させたことを受光部が検知してスプロケットホール３または補助割出孔１７の前縁を検知する。 The auxiliary index hole 17 in this embodiment is formed so that the distance between the sprocket holes 3, that is, the distance between the sprocket holes 3 and the supplementary index holes 17 is half the pitch P (2.375 mm in this embodiment). Has been.
Reference numeral 18 denotes an edge detection sensor, which is an optical sensor or the like in which a light emitting portion and a light receiving portion provided on a work table or the like of a manufacturing apparatus (not shown) are opposed to each other on a row of sprocket holes 3 with the tape carrier 1 interposed therebetween. The light receiving part detects that the front edge of the sprocket hole 3 or the auxiliary indexing hole 17 in the feeding direction of the tape carrier 1 transmits light from the light emitting part, and the front of the sprocket hole 3 or the auxiliary indexing hole 17 is detected. Detect edges.

上記のＴＣＰ型半導体ユニット４をテープキャリア１の半導体搭載領域２ｂに連続的に配置する場合は、ＴＣＰ型半導体ユニット４の製品としての縦幅Ｃの中心線（図１に断面線Ａ−Ａとして示す一点鎖線）をスプロケットホール３または補助割出孔１７の長手方向の長さＢの中央と一致させて半導体搭載領域２ｂの第１の位置に配置（縦幅Ｃの中心線にその長手方向の長さＢの中央が一致しているスプロケットホール３または補助割出孔１７を基準孔１９という。）し、次のＴＣＰ型半導体ユニット４も同様にして基準孔１９の中央に縦幅Ｃの中心線を一致させて配置する。   When the above-described TCP type semiconductor unit 4 is continuously arranged in the semiconductor mounting region 2b of the tape carrier 1, the center line of the vertical width C as a product of the TCP type semiconductor unit 4 (as a sectional line AA in FIG. 1). Is arranged at the first position of the semiconductor mounting region 2b so that it coincides with the center of the longitudinal length B of the sprocket hole 3 or auxiliary indexing hole 17 (the longitudinal line C is centered in the longitudinal direction). The sprocket hole 3 or the auxiliary indexing hole 17 whose length B is in the center is referred to as a reference hole 19), and the next TCP type semiconductor unit 4 is similarly formed in the center of the reference hole 19 with the center of the vertical width C. Arrange the lines to match.

このとき、次のＴＣＰ型半導体ユニット４は、縦幅Ｃにテストパッド１５の長さを加えたＴＣＰ型半導体ユニット４のテープキャリア１上の縦幅Ｔが互いに重ならない半導体搭載領域２ｂ上の最も近い第２の位置、つまり隣り合うＴＣＰ型半導体ユニット４の縦幅Ｔ間の距離が最小となる位置に配置し、このときの第１および第２の位置のＴＣＰ型半導体ユニット４の中心線間の間隔、つまり基準孔１９間の間隔をＬとする。   At this time, the next TCP type semiconductor unit 4 is the longest on the semiconductor mounting region 2b where the vertical width T on the tape carrier 1 of the TCP type semiconductor unit 4 obtained by adding the length of the test pad 15 to the vertical width C does not overlap each other. It arrange | positions in the near 2nd position, ie, the position where the distance between the vertical widths T of the adjacent TCP type semiconductor units 4 becomes the minimum, and the center line of the TCP type semiconductor unit 4 of the 1st and 2nd position at this time , That is, the interval between the reference holes 19 is L.

また、エッジ検出センサ１８は、基準孔１９の送り方向の前縁をエッジ検出センサ１８が検知した時に基準孔１９の長手方向の中央が図示しない製造装置の所定の位置、つまりＴＣＰ型半導体ユニット４が所定の位置に位置する場所に設置する。
上記の構成の作用について説明する。
本実施例のＴＣＰ型半導体ユニット４の製造工程においては、スプロケットホール３および補助割出孔１７をベースフィルム２の両方の縁領域２ａに穿孔して長尺のテープキャリア１を形成し、その表面に銅箔を貼付け、これを上記の第１および第２の位置の間隔Ｌごととになるとように設定した両側の基準孔１９の中央に半導体素子１０を設置する窓部の中央を一致させて窓部を穿孔し、その周囲にフォトエッチング等によりインナーリード１１による配線パターンやそれぞれのインナーリード１１に接続する入力端子側アウターリード７、出力端子側アウターリード８および出力端子側アウターリード８にそれぞれ接続するテストパッド１５を形成する。 Further, the edge detection sensor 18 has a center in the longitudinal direction of the reference hole 19 when the edge detection sensor 18 detects the leading edge of the reference hole 19 in the feeding direction, that is, a predetermined position of a manufacturing apparatus (not shown), that is, the TCP type semiconductor unit 4. Is installed in a place where is located at a predetermined position.
The operation of the above configuration will be described.
In the manufacturing process of the TCP type semiconductor unit 4 of the present embodiment, the sprocket hole 3 and the auxiliary indexing hole 17 are drilled in both edge regions 2a of the base film 2 to form the long tape carrier 1, and its surface A copper foil is affixed to the center of the reference hole 19 on both sides which is set to be at intervals L between the first and second positions. A window portion is perforated, and a wiring pattern formed by the inner leads 11 by photo etching or the like around the window portion, and the input terminal side outer leads 7, the output terminal side outer leads 8, and the output terminal side outer leads 8 connected to the inner leads 11, respectively. A test pad 15 to be connected is formed.

次いで、複数の半導体素子１０を準備し、第１の半導体素子１０を第１の位置の窓部に、次のつまり第２の半導体素子１０を第２の位置の窓部に配置し、それぞれの半導体素子１０のバンブ電極９を配線パターンであるインナーリード１１に接触させて搭載し、超音波溶接等により接続して配線する。
そして、アライメントホール６の穿孔等を行い、テープキャリア１の半導体搭載領域２ｂに順次にＴＣＰ型半導体ユニット４を配置した半導体装置を形成する。 Next, a plurality of semiconductor elements 10 are prepared, and the first semiconductor element 10 is disposed in the window portion at the first position, and the next, that is, the second semiconductor element 10 is disposed in the window portion at the second position. The bump electrode 9 of the semiconductor element 10 is mounted in contact with the inner lead 11 that is a wiring pattern, and is connected and wired by ultrasonic welding or the like.
Then, the alignment hole 6 is drilled, and the semiconductor device in which the TCP type semiconductor units 4 are sequentially arranged in the semiconductor mounting region 2b of the tape carrier 1 is formed.

上記の各工程においては、基準孔１９を基準として各工程の加工や処理を行う。
すなわち、図示しない製造装置の制御部は、テープキャリア１の交換後の作業者等による基準孔１９の初期設定において最初の基準孔１９の位置を記憶し、テープキャリア１の最上流に設定されているカットエリア５でその工程の作業を行い、その工程が終了すると次のカットエリア５で作業を行うために図示しない駆動モータにパルスを供給してテープキャリア１を送り方向へ移動させる。 In each process described above, each process is processed and processed with reference to the reference hole 19.
That is, the control unit of the manufacturing apparatus (not shown) stores the position of the first reference hole 19 in the initial setting of the reference hole 19 by an operator or the like after replacement of the tape carrier 1 and is set as the most upstream of the tape carrier 1. The work of the process is performed in the cut area 5, and when the process is completed, a pulse is supplied to a drive motor (not shown) to perform the work in the next cut area 5 to move the tape carrier 1 in the feeding direction.

この時、制御部はエッジ検出センサ１８によりスプロケットホール３および補助割出孔１７の前縁を検出しながらそのコマ数を計数し、スプロケットの歯が噛合っているスプロケットホール３または補助割出孔１７の急停止による損傷を防止するために間隔Ｌとして設定されているコマ数の少し手前、例えば１コマ手前からフィードフォワード制御によりブレーキをかけながら送り速度を減速させ、間隔Ｌとして設定されているコマ数の前縁を検出した時、つまり基準孔１９の前縁を検出した時にブレーキによりテープキャリア１を停止させて次のカットエリア５の作業を行う。   At this time, the control unit counts the number of frames while detecting the leading edge of the sprocket hole 3 and the auxiliary index hole 17 by the edge detection sensor 18, and the sprocket hole 3 or the auxiliary index hole in which the teeth of the sprocket are engaged. In order to prevent damage due to 17 sudden stops, the feed speed is decelerated while applying the brake by feedforward control slightly before the number of frames set as the interval L, for example, one frame before, and is set as the interval L. When the leading edge of the number of frames is detected, that is, when the leading edge of the reference hole 19 is detected, the tape carrier 1 is stopped by the brake and the next cut area 5 is operated.

このようにして、スプロケットホール３および補助割出孔１７の前縁のコマ数を計数しながら順次に工程を進めてＴＣＰ型半導体ユニット４のテープキャリア１上での作業を全て終了すると図示しないポンチとダイス等のカッタによりＴＣＰ型半導体ユニット４のカットエリア５を打抜いてＴＣＰ型半導体ユニット４の製品または半製品を製造する。
この場合に、複数のＴＣＰ型半導体ユニット４を連ねた短冊状にテープキャリア１を切断して電子機器の製造メーカ等でカットエリア５を打抜くようにしてもよい。 In this way, when the work on the tape carrier 1 of the TCP type semiconductor unit 4 is completed by sequentially proceeding while counting the number of frames at the front edge of the sprocket hole 3 and the auxiliary index hole 17, a punch (not shown) is shown. Then, a cut area 5 of the TCP type semiconductor unit 4 is punched out with a cutter such as a die to manufacture a product or a semi-finished product of the TCP type semiconductor unit 4.
In this case, the tape carrier 1 may be cut into a strip shape in which a plurality of TCP type semiconductor units 4 are connected, and the cut area 5 may be punched out by an electronic device manufacturer or the like.

なお、本実施例の製造装置のスプロケットは、製造装置の作業部位と別の部位に配置されており、エッジ検出センサ１８による前縁の検出に支障を起こすことはない。
また、スプロケットの歯は標準の場合と同様に形成されており、本実施例のスプロケットホール３または補助割出孔１７とは１つおきに噛合っている。
上記のようなテープキャリア１の半導体搭載領域２ｂにＴＣＰ型半導体ユニット４を順次に配置した半導体装置の製造において、例えば、縦幅Ｔ＝１４．６ｍｍのＴＣＰ型半導体ユニット４の半導体装置を製造する場合に標準のテープキャリア１、つまり４．７５ｍｍのピッチＰでスプロケットホール３のみが配列されているテープキャリア１の場合は、スプロケットホール３の４コマごと（スプロケットホール３と補助割出孔１７のコマ数に換算して８コマごと）に配置（基準孔１９間の間隔Ｌ＝１９ｍｍ）しなければならないが、本実施例のスプロケットホール３と補助割出孔１７を２．３７５ｍｍごとに穿孔したテープキャリアを用いれば、基準孔１９の間隔Ｌをスプロケットホール３と補助割出孔１７の７コマ（Ｌ＝１６．６２５ｍｍ）ごとに配置すればよく、同一の個数を製造する場合にテープキャリア１の全長を１２．５％短縮することができ、テープキャリア１のコストの削減を図ることができる。 Note that the sprocket of the manufacturing apparatus according to the present embodiment is arranged in a part different from the work part of the manufacturing apparatus, and does not cause a problem in the detection of the leading edge by the edge detection sensor 18.
Further, the sprocket teeth are formed in the same manner as in the standard case, and every other sprocket hole 3 or auxiliary indexing hole 17 is engaged.
In manufacturing the semiconductor device in which the TCP type semiconductor units 4 are sequentially arranged in the semiconductor mounting region 2b of the tape carrier 1 as described above, for example, the semiconductor device of the TCP type semiconductor unit 4 having a vertical width T = 14.6 mm is manufactured. In the case of the standard tape carrier 1, that is, the tape carrier 1 in which only the sprocket holes 3 are arranged at the pitch P of 4.75 mm, every four frames of the sprocket holes 3 (the sprocket holes 3 and the auxiliary index holes 17 (Each 8 frames in terms of the number of frames) must be arranged (interval L between the reference holes 19 = 19 mm), but the sprocket hole 3 and the auxiliary indexing hole 17 of this embodiment were drilled every 2.375 mm. If a tape carrier is used, the distance L between the reference holes 19 is set to 7 frames (L = 16.625 m) between the sprocket holes 3 and the auxiliary index holes 17. ) May be disposed for each, when producing the same number of the total length of the tape carrier 1 can be reduced by 12.5%, it is possible to reduce the cost of the tape carrier 1.

また、標準化された全長を有するテープキャリア１の場合は、例えば１巻の全長を４０ｍとすると、標準のテープキャリア１の場合は１巻のテープキャリア１で約２０００個（４００００ｍｍ×９５％（テープ歩留まり）／（４．７５ｍｍ×４コマ））しか製造できないが、本実施例のテープキャリア１を用いれば１巻のテープキャリア１で約２２８５個（４００００ｍｍ×９５％（テープ歩留まり）／（２．３７５ｍｍ×７コマ））を製造することができ、１巻あたり約１４％多く製造することができるので、テープキャリア３の交換頻度を減少させて作業効率を向上させることができ、ＴＣＰ型半導体ユニット４の半導体装置の生産性の向上を図ることができる。   In the case of the tape carrier 1 having a standardized total length, for example, if the total length of one roll is 40 m, in the case of the standard tape carrier 1, about 2000 (40000 mm × 95% (tape) (Yield) / (4.75 mm × 4 frames)), but if the tape carrier 1 of this embodiment is used, about 2285 tapes 1 (40000 mm × 95% (tape yield) / (2. 375 mm × 7 frames)), and about 14% more can be manufactured per roll, so that the frequency of replacement of the tape carrier 3 can be reduced and work efficiency can be improved. The productivity of the semiconductor device 4 can be improved.

なお、本実施例では、補助割出孔１７はスプロケットホール３と略同形状の正方形として図示したが、補助割出孔１７の形状は長方形、円形等であってもよい。要は長手方向の長さＢ（円形の場合はその円の直径）が同一であり、エッジ検出センサ１８によりその前縁を検出できる形状であればどのような形状であってもよい。
また、本実施例では説明の都合上、補助割出孔１７とスプロケットホール３とを区別して説明したが、補助割出孔１７をスプロケットホール３と同形状またはスプロケットの歯と嵌合してテープキャリア１を送り方向へ移動させる機能を有する形状とすれば補助割出孔１７はスプロケットホール３と同一のピッチＰとして形成してあるので、テープキャリア１の交換時に補助割出孔１７とスプロケットホール３とを区別せずにテープキャリア３の交換作業を行うことができ、テープキャリア１の交換後の基準孔１９の初期設定を行うのみでテープキャリア３の交換作業の迅速化を図ることができる。 In the present embodiment, the auxiliary indexing hole 17 is illustrated as a square having substantially the same shape as the sprocket hole 3, but the auxiliary indexing hole 17 may be rectangular, circular, or the like. In short, the length B in the longitudinal direction (in the case of a circle, the diameter of the circle) is the same, and any shape may be used as long as the leading edge can be detected by the edge detection sensor 18.
Further, in this embodiment, the auxiliary index hole 17 and the sprocket hole 3 are distinguished from each other for convenience of explanation. However, the auxiliary index hole 17 has the same shape as the sprocket hole 3 or is fitted with the sprocket teeth to form a tape. Since the auxiliary index holes 17 are formed at the same pitch P as the sprocket holes 3 if the carrier 1 has a function of moving in the feed direction, the auxiliary index holes 17 and the sprocket holes are replaced when the tape carrier 1 is replaced. The tape carrier 3 can be replaced without distinguishing it from the tape carrier 3, and the replacement of the tape carrier 3 can be speeded only by initial setting of the reference hole 19 after replacement of the tape carrier 1. .

この場合に、本実施例において第１の孔はスプロケットホール３、第２の孔は補助割出孔１７として説明したが、補助割出孔１７にスプロケットの歯が嵌合している場合には、第１の孔は補助割出孔１７、第２の孔はスプロケットホール３であって、それぞれの機能を入れ替えて機能することになる。要はスプロケットの歯が嵌合する孔が第１の孔であり、その間に同列に、同一ピッチＰで形成された孔が第２の孔である。   In this case, the first hole has been described as the sprocket hole 3 and the second hole as the auxiliary index hole 17 in this embodiment, but when the sprocket teeth are fitted in the auxiliary index hole 17, The first hole is the auxiliary indexing hole 17 and the second hole is the sprocket hole 3, which function by exchanging their functions. In short, the holes into which the sprocket teeth are fitted are the first holes, and the holes formed in the same row and at the same pitch P are the second holes.

以上説明したように、本実施例では、長尺のベースフィルムの両方の縁領域に所定のピッチで設けた複数のスプロケットホール間に、スプロケットホールと同列に同一ピッチで長手方向の長さＢを同一とした補助割出孔を設けたことによって、ＴＣＰ型半導体ユニット等の半導体ユニットの配置を短い間隔Ｌで連続的に設定することができ、テープキャリアの全長を短縮してそのコストの削減を図ることができると共に、テープキャリアの交換頻度を減少させて半導体装置の生産性の向上を図ることができる。   As described above, in this embodiment, the length B in the longitudinal direction at the same pitch in the same row as the sprocket holes is provided between the plurality of sprocket holes provided at a predetermined pitch in both edge regions of the long base film. By providing the same auxiliary indexing holes, the arrangement of the semiconductor units such as TCP type semiconductor units can be set continuously with a short interval L, and the total length of the tape carrier can be shortened to reduce its cost. In addition, the productivity of the semiconductor device can be improved by reducing the replacement frequency of the tape carrier.

また、標準化されたテープキャリア幅や長さ、スプロケットホールはそのままにして、スプロケットホールの同列上に補助割出孔を設けるようにしたことによって、製造装置のスプロケットの形状やエッジ検出センサの位置等を変更することなく本発明を適用することができ、本発明のテープキャリアの早期の実現を図ることが可能になる。
更に、標準化されたベースフィルムに標準に従ったスプロケットホールを穿孔した場合にはスプロケットホールの外側の領域が非常に狭くなるため、例えば上記特許文献１に示されたパイロットホールを配列するには困難があり、ベースフィルムの幅を標準より広くしなければならないという懸念があるが、本実施例では補助割出孔をスプロケットホールの同列上に設けるようにしたので、この懸念を払拭して標準化されたベースフィルムを用いて生産性が高く、かつ現行の製造装置へそのまま適用できる安価なテープキャリアを容易に得ることができる。 In addition, by keeping the standard tape carrier width and length, sprocket holes as they are, and by providing auxiliary index holes on the same row of sprocket holes, the shape of the sprocket of the manufacturing equipment, the position of the edge detection sensor, etc. The present invention can be applied without changing the above, and the tape carrier of the present invention can be realized at an early stage.
Furthermore, when a sprocket hole according to the standard is drilled in a standardized base film, the area outside the sprocket hole becomes very narrow, so that it is difficult to arrange the pilot holes disclosed in Patent Document 1, for example. There is a concern that the width of the base film must be wider than the standard, but in this example, the auxiliary index holes were provided on the same row of sprocket holes, so this concern was standardized. In addition, it is possible to easily obtain an inexpensive tape carrier that has high productivity and can be directly applied to an existing manufacturing apparatus.

なお、本実施例では、スプロケットホールや補助割出孔をベースフィルムの両方の縁領域に穿孔して形成するとして説明したが、片側の縁領域のみに形成するようにしても上記と同様の効果を得ることができる。
また、本実施例では、テープキャリアを停止させる位置の検出は、エッジ検出センサによりスプロケットホールおよび補助割出孔の前縁を検出しながらそのコマ数を計数して基準孔を検出するとして説明したが、エッジ検出センサに替えてＣＣＤカメラ等の画像センサを設け、画像センサが撮影したスプロケットホールおよび補助割出孔の画像の画像認識によりその中心位置を検出しながらコマ数を計数して基準孔の中心位置を検出するようにしてもよい。これにより補助割出孔の形状は中心位置を検出できる形状であれば足り、補助割出孔の長手方向の長さＢを同一とする必要がなくなるので補助割出孔の形成を更に容易に行うことができる。 In the present embodiment, the sprocket hole and the auxiliary index hole are described as being formed by drilling in both edge regions of the base film. Can be obtained.
Further, in this embodiment, the detection of the position where the tape carrier is stopped is described as detecting the reference hole by counting the number of frames while detecting the front edge of the sprocket hole and the auxiliary index hole by the edge detection sensor. However, an image sensor such as a CCD camera is provided in place of the edge detection sensor, and the reference hole is counted by detecting the center position by image recognition of the sprocket hole and auxiliary index hole images taken by the image sensor. You may make it detect the center position of. As a result, it is sufficient if the shape of the auxiliary index hole is such that the center position can be detected, and it is not necessary to make the length B in the longitudinal direction of the auxiliary index hole the same, so that the auxiliary index hole can be formed more easily. be able to.

図３は実施例２のテープキャリアを示す正面図、図４は図３のＤ−Ｄ断面図である。
なお、上記実施例１と同様の部分は、同一の符号を付してその説明を省略する。
２１は半導体ユニットとしてのＣＯＦ（Ｃｈｉｐ Ｏｎ Ｆｉｌｍ）型半導体ユニットであり、ベースフィルム２の半導体搭載領域２ｂのカットエリア５をテープキャリア１から打抜いて形成される。 FIG. 3 is a front view showing the tape carrier of Example 2, and FIG. 4 is a sectional view taken along the line DD of FIG.
In addition, the same part as the said Example 1 attaches | subjects the same code | symbol, and abbreviate | omits the description.
Reference numeral 21 denotes a COF (Chip On Film) type semiconductor unit as a semiconductor unit, which is formed by punching the cut area 5 of the semiconductor mounting area 2 b of the base film 2 from the tape carrier 1.

本実施例のＣＯＦ型半導体ユニット２１は、テープキャリア１に窓部を穿孔せずに、その片面に直接半導体素子１０を載置して半導体装置が製造されため、バンブ電極９等の配置が上記実施例１のＴＣＰ型半導体ユニット４と異なっているが、その半導体素子１０のバンブ電極９インナーリード１１へ接触させて搭載して配線する等の機能は実質的に同様である。   In the COF type semiconductor unit 21 of this embodiment, a semiconductor device is manufactured by directly mounting the semiconductor element 10 on one side of the tape carrier 1 without perforating the window portion. Although different from the TCP type semiconductor unit 4 of the first embodiment, functions such as mounting and wiring in contact with the bump electrode 9 inner lead 11 of the semiconductor element 10 are substantially the same.

なお、本実施例の半導体素子１０を実施例１で説明した半導体搭載領域２ｂの第１および第２の位置に搭載する場合は設定された基準孔１９を基に第１および第２の半導体素子１０を配置する。
上記のようなＣＯＦ型半導体ユニット２１の半導体装置のテープキャリア１を用いた製造においても、本実施例のスプロケットホール３と補助割出孔１７を２．３７５ｍｍごとに穿孔したテープキャリアを用いれば、例えば、縦幅Ｔ＝１４．６ｍｍのＣＯＦ型半導体ユニット２１を製造する場合に、上記実施例１と同様に同一の個数を製造する場合のテープキャリア１の全長を１２．５％短縮することができ、テープキャリア１のコストの削減を図ることができる。 When the semiconductor element 10 of the present embodiment is mounted at the first and second positions of the semiconductor mounting area 2b described in the first embodiment, the first and second semiconductor elements are based on the set reference holes 19. 10 is arranged.
Even in the manufacture of the semiconductor device of the COF type semiconductor unit 21 using the tape carrier 1 as described above, if the tape carrier in which the sprocket hole 3 and the auxiliary indexing hole 17 of this embodiment are formed every 2.375 mm is used, For example, when manufacturing a COF type semiconductor unit 21 having a vertical width T = 14.6 mm, the total length of the tape carrier 1 when manufacturing the same number as in the first embodiment may be shortened by 12.5%. The cost of the tape carrier 1 can be reduced.

また、標準化された全長を有するテープキャリア１場合は、例えば１巻の全長を４０ｍとすると、ＣＯＦ型半導体ユニット２１を１巻あたり約１４％多く製造することができるので、テープキャリア１の交換頻度を減少させて作業効率を向上させることができ、ＣＯＦ型半導体ユニット２１の半導体装置の生産性の向上を図ることができる。
このように、ＣＯＦ型半導体ユニットの半導体装置の製造においても、上記実施例１と同様の効果を奏することができる。 Further, in the case of the tape carrier 1 having a standardized total length, for example, if the total length of one roll is 40 m, about 14% more COF type semiconductor units 21 can be manufactured per roll. As a result, the working efficiency can be improved and the productivity of the semiconductor device of the COF type semiconductor unit 21 can be improved.
Thus, also in the manufacture of the semiconductor device of the COF type semiconductor unit, the same effect as in the first embodiment can be obtained.

図５は実施例３のテープキャリアを示す正面図、図６は図５のＥ−Ｅ断面図である。
なお、上記実施例１と同様の部分は、同一の符号を付してその説明を省略する。
３１は半導体ユニットとしてのＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）型半導体ユニットであり、ベースフィルム２の半導体搭載領域２ｂのカットエリア５をテープキャリア１から打抜いて形成される。 FIG. 5 is a front view showing the tape carrier of Example 3, and FIG. 6 is a cross-sectional view taken along line EE of FIG.
In addition, the same part as the said Example 1 attaches | subjects the same code | symbol, and abbreviate | omits the description.
Reference numeral 31 denotes a BGA (Ball Grid Array) type semiconductor unit as a semiconductor unit, which is formed by punching the cut area 5 of the semiconductor mounting area 2 b of the base film 2 from the tape carrier 1.

ＢＧＡ型半導体ユニット３１は、回路素子およびこの回路素子に電気的に接続された電極としてのボンディングパッド３２を有する半導体素子１０、テープキャリア１上の配線パターンであるボンディングパッド３３、ボンディングパッド３２、３３間を接続するボンディングワイヤ３４、テープキャリア１上のボンディングパッド３３の反対側に設けられたランド３５、配線パターンを保護するためのソルダーレジスト３６、半導体素子１０とボンディングワイヤ３４を保護するための封止樹脂３７、テープキャリア１上のボンディングパッド３３とランド３５をベースフィルム２に貼付するための接着剤３８、半導体素子１０をテープキャリア１に固定するための接着剤３９、図示しない外部基板と接続するボール電極４０により構成される。   The BGA type semiconductor unit 31 includes a semiconductor element 10 having a circuit element and a bonding pad 32 as an electrode electrically connected to the circuit element, a bonding pad 33 which is a wiring pattern on the tape carrier 1, and bonding pads 32, 33. A bonding wire 34 for connecting between them, a land 35 provided on the opposite side of the bonding pad 33 on the tape carrier 1, a solder resist 36 for protecting the wiring pattern, and a seal for protecting the semiconductor element 10 and the bonding wire 34. Stop resin 37, adhesive 38 for bonding the bonding pad 33 and land 35 on the tape carrier 1 to the base film 2, adhesive 39 for fixing the semiconductor element 10 to the tape carrier 1, and connection to an external substrate (not shown) Constituted by a ball electrode 40 That.

４１はボール電極４０をテープキャリア１を貫通してＢＧＡ型半導体ユニット３１に取付けるためのランドホールである。
本実施例のＢＧＡ型半導体ユニット３１は、横幅が狭いために図５に示すようにテープキャリア１の幅方向に２個並置され、並置される２個のＢＧＡ型半導体ユニット３１の半導体素子１０を一組にし、これを第１および第２の半導体素子として上記実施例１で説明した半導体搭載領域２ｂの第１および第２の位置に配置して搭載され、この配置に従ってテープキャリア１にランドホール４１を穿孔したテープキャリア１を用いてＢＧＡ型半導体ユニット３１の半導体装置が製造される。この場合に電極であるボンディングパッド３２と配線パターンであるボンディングパッド３３とは半導体素子１０のテープキャリア１への搭載後にボンディングワイヤ３４で接続される。 Reference numeral 41 denotes a land hole for attaching the ball electrode 40 to the BGA type semiconductor unit 31 through the tape carrier 1.
Since the BGA type semiconductor unit 31 of this embodiment has a narrow lateral width, two BGA type semiconductor units 31 are juxtaposed in the width direction of the tape carrier 1 as shown in FIG. One set is mounted as the first and second semiconductor elements at the first and second positions of the semiconductor mounting region 2b described in the first embodiment, and the land holes are mounted on the tape carrier 1 according to this arrangement. The semiconductor device of the BGA type semiconductor unit 31 is manufactured using the tape carrier 1 having 41 perforated. In this case, the bonding pad 32 as an electrode and the bonding pad 33 as a wiring pattern are connected by a bonding wire 34 after the semiconductor element 10 is mounted on the tape carrier 1.

上記のＢＧＡ型半導体ユニット３１は小型であるために、その縦幅ＴはＴ＝１１．１８９ｍｍ（ＢＧＡ型半導体ユニット３１の半導体装置の製造においてはテストパッド１５が不要であるので、製品としての縦幅Ｃと縦幅Ｔは同一である。）となっている。
このようなＢＧＡ型半導体ユニット３１の半導体装置のテープキャリア１を用いた製造において、標準のテープキャリア１では、スプロケットホール３の３コマごと（スプロケットホール３と補助割出孔１７のコマ数に換算して６コマごと）に配置（基準孔１９間の間隔Ｌ＝１４．２５ｍｍ）しなければならないが、本実施例のスプロケットホール３と補助割出孔１７を２．３７５ｍｍごとに穿孔したテープキャリア１を用いれば、基準孔１９の間隔Ｌをスプロケットホール３と補助割出孔１７の５コマ（Ｌ＝１１．８７５ｍｍ）ごとに配置すればよく、同一の個数を製造する場合にテープキャリア１の全長を１６．７％短縮することができ、テープキャリア１のコストの削減を図ることができる。 Since the BGA type semiconductor unit 31 is small in size, its vertical width T is T = 11.189 mm (the test pad 15 is not necessary in the manufacture of the semiconductor device of the BGA type semiconductor unit 31, so that the vertical length as a product is The width C and the vertical width T are the same).
In the manufacture of the semiconductor device of such a BGA type semiconductor unit 31 using the tape carrier 1, the standard tape carrier 1 converts every three frames of the sprocket hole 3 (converted into the number of frames of the sprocket hole 3 and the auxiliary index hole 17. (The interval between the reference holes 19 is L = 14.25 mm), but the sprocket hole 3 and the auxiliary indexing hole 17 of this embodiment are drilled every 2.375 mm. 1 is used, the interval L between the reference holes 19 may be arranged for every 5 frames (L = 11.875 mm) of the sprocket hole 3 and the auxiliary indexing hole 17, and when the same number is manufactured, the tape carrier 1 The total length can be shortened by 16.7%, and the cost of the tape carrier 1 can be reduced.

また、標準化された全長を有するテープキャリア１の場合は、例えば１巻の全長を４０ｍとすると、標準のテープキャリア１の場合は１巻のテープキャリア１で約５３３２個（（４００００ｍｍ×９５％（テープ歩留まり）／（４．７５ｍｍ×３コマ））×２個取り）しか製造できないが、本実施例のテープキャリア１を用いれば１巻のテープキャリア１で約６４００個（（４００００ｍｍ×９５％（テープ歩留まり）／（２．３７５ｍｍ×５コマ））×２個取り）を製造することができ、１巻あたり約２０％多く製造することができるので、テープキャリア３の交換頻度を減少させて作業効率を向上させることができ、ＢＧＡ型半導体ユニット３１の半導体装置の生産性の向上を図ることができる。   In the case of the tape carrier 1 having a standardized total length, for example, if the total length of one roll is 40 m, in the case of the standard tape carrier 1, about 5332 pieces ((40000 mm × 95% ( Tape yield) / (4.75 mm × 3 frames)) × 2 picks), but if the tape carrier 1 of this embodiment is used, about 6400 pieces ((40000 mm × 95% ( Tape yield) / (2.375mm x 5 frames)) x 2)), and about 20% more can be produced per roll, so the frequency of replacing the tape carrier 3 can be reduced. The efficiency can be improved, and the productivity of the semiconductor device of the BGA type semiconductor unit 31 can be improved.

このように、ＢＧＡ型半導体ユニットの半導体装置の製造においても、上記実施例１と同様の効果を奏することができる。
なお、上記各実施例では、補助割出孔はスプロケットホール間の中央に設けるとして説明したが、スプロケットホール間を複数に等分して配置するようにすれば、更に細かく基準孔間の間隔を設定することが可能になり、テープキャリアのコストの削減または半導体ユニットの生産性の向上を更に図ることができる。 Thus, also in the manufacture of the semiconductor device of the BGA type semiconductor unit, the same effect as in the first embodiment can be obtained.
In each of the above embodiments, the auxiliary indexing hole is described as being provided at the center between the sprocket holes. However, if the sprocket holes are equally divided into a plurality of spaces, the spacing between the reference holes can be further reduced. This makes it possible to further reduce the cost of the tape carrier or improve the productivity of the semiconductor unit.

また、上記各実施例の各図示においては、スプロケットホールを最初に設けるように図示したが、補助割出孔を最初に設けてスプロケットホールと交互に形成するようにしても各実施例の効果を損なうものではない。
更に、基準孔の前縁の検出によるテープキャリアの停止は、エッジ検出センサが検出したコマ数によりブレーキをかけて停止させるとして説明したが、ラチェット式等のテープ送りの割出装置を備えた製造装置においては、割出装置の割出角度を変更して本発明のテープキャリアを適用すれば上記と同様の効果を得ることができる。 Further, in each illustration of each of the above embodiments, the sprocket hole is shown to be provided first, but the effect of each embodiment can be obtained even if the auxiliary indexing hole is provided first and alternately formed with the sprocket hole. There is no loss.
Furthermore, the tape carrier stoppage by detecting the leading edge of the reference hole has been described as being stopped by applying a brake based on the number of frames detected by the edge detection sensor. However, manufacturing with a tape feed indexing device such as a ratchet type In the apparatus, the same effect as described above can be obtained by changing the indexing angle of the indexing apparatus and applying the tape carrier of the present invention.

実施例１のテープキャリアを示す正面図Front view showing the tape carrier of Example 1 図１のＡ−Ａ断面図AA sectional view of FIG. 実施例２のテープキャリアを示す正面図Front view showing a tape carrier of Example 2 図３のＤ−Ｄ断面図DD sectional view of FIG. 実施例３のテープキャリアを示す正面図Front view showing a tape carrier of Example 3 図５のＥ−Ｅ断面図EE sectional view of FIG.

符号の説明Explanation of symbols

１ テープキャリア
２ ベースフィルム
２ａ 縁領域
２ｂ 半導体搭載領域
３ スプロケットホール
４ ＴＣＰ型半導体ユニット
５ カットエリア
６ アライメントホール
７ 入力端子側アウターリード
８ 出力端子側アウターリード
９ バンブ電極
１０ 半導体素子
１１ インナーリード
１２、３６ ソルダーレジスト
１３、３７ 封止樹脂
１４、３８、３９ 接着剤
１５ テストパッド
１７ 補助割出孔
１８ エッジ検出センサ
１９ 基準孔
２１ ＣＯＦ型半導体ユニット
３１ ＢＧＡ型半導体ユニット
３２、３３ ボンディングパッド
３４ ボンディングワイヤ
３５ ランド
４０ ボール電極
４１ ランドホール DESCRIPTION OF SYMBOLS 1 Tape carrier 2 Base film 2a Edge area 2b Semiconductor mounting area 3 Sprocket hole 4 TCP type semiconductor unit 5 Cut area 6 Alignment hole 7 Input terminal side outer lead 8 Output terminal side outer lead 9 Bump electrode 10 Semiconductor element 11 Inner lead 12, 36 Solder resist 13, 37 Sealing resin 14, 38, 39 Adhesive 15 Test pad 17 Auxiliary index hole 18 Edge detection sensor 19 Reference hole 21 COF type semiconductor unit 31 BGA type semiconductor unit 32, 33 Bonding pad 34 Bonding wire 35 Land 40 Ball electrode 41 Land hole

Claims (12)

長尺のベースフィルムの縁領域に、所定のピッチで配列された複数の第１の孔と、該第１の孔の間に形成された第２の孔とを備え、
該第２の孔が、前記第１の孔と同列に、かつ同一ピッチで形成されていることを特徴とするテープキャリア。 A plurality of first holes arranged at a predetermined pitch in the edge region of the long base film, and a second hole formed between the first holes,
The tape carrier, wherein the second holes are formed in the same row and at the same pitch as the first holes. 請求項１において、
前記ベースフィルムの長手方向に対応する前記第２の孔の長さは、前記ベースフィルムの長手方向に対応する前記第１の孔の長さと同一であることを特徴とするテープキャリア。 In claim 1,
The tape carrier according to claim 1, wherein the length of the second hole corresponding to the longitudinal direction of the base film is the same as the length of the first hole corresponding to the longitudinal direction of the base film. 請求項１または請求項２において、
前記第１の孔と前記第２の孔との間の間隔は、等しく設定されていることを特徴とするテープキャリア。 In claim 1 or claim 2,
The tape carrier according to claim 1, wherein a distance between the first hole and the second hole is set to be equal. 請求項３において、
前記第１の孔と前記第２の孔との間隔は、２．３７５ｍｍであることを特徴とするテープキャリア。 In claim 3,
The tape carrier according to claim 1, wherein a distance between the first hole and the second hole is 2.375 mm. 請求項１または請求項２において、
前記第２の孔は、前記第１の孔の間で複数に等分して配置されていることを特徴とするテープキャリア。 In claim 1 or claim 2,
The tape carrier, wherein the second hole is equally divided into a plurality of portions between the first holes. 請求項１から請求項４または請求項５において、
前記所定のピッチは、４．７５ｍｍであることを特徴とするテープキャリア。 In claim 1 to claim 4 or claim 5,
The tape carrier according to claim 1, wherein the predetermined pitch is 4.75 mm. （ａ）縁領域と、該縁領域の間の半導体搭載領域と、前記縁領域に所定のピッチで配列された複数の第１の孔と、該第１の孔の間に該第１の孔と同列に前記所定のピッチで配列された第２の孔とを有するテープキャリアを形成する工程と、
（ｂ）回路素子と、該回路素子に電気的に接続された電極とを有する第１および第２の半導体素子を準備する工程と、
（ｃ）前記第１の半導体素子を、前記第１の孔を基準として前記半導体搭載領域の第１の位置に搭載する工程と、
（ｄ）前記第２の半導体素子を、前記第２の孔を基準として前記半導体搭載領域の第２の位置に搭載する工程とを備えることを特徴とする半導体装置の製造方法。 (A) an edge region, a semiconductor mounting region between the edge regions, a plurality of first holes arranged at a predetermined pitch in the edge region, and the first hole between the first holes Forming a tape carrier having the second holes arranged in the same row at the predetermined pitch;
(B) preparing first and second semiconductor elements having circuit elements and electrodes electrically connected to the circuit elements;
(C) mounting the first semiconductor element at a first position of the semiconductor mounting region with respect to the first hole;
(D) mounting the second semiconductor element at a second position of the semiconductor mounting region with the second hole as a reference, and a method for manufacturing a semiconductor device. 請求項７において、
前記（ｃ）および（ｄ）の工程で、前記第１および第２の半導体素子は、実質的に前記テープキャリアに形成された配線パターンに前記電極が接触するように搭載されることを特徴とする半導体装置の製造方法。 In claim 7,
In the steps (c) and (d), the first and second semiconductor elements are mounted so that the electrodes are substantially in contact with a wiring pattern formed on the tape carrier. A method for manufacturing a semiconductor device. 請求項７において、
前記（ｃ）および（ｄ）の工程で、前記第１および第２の半導体素子は、前記テープキャリアに形成された配線パターンと前記電極とがボンディングワイヤによって接続されるように搭載されることを特徴とする半導体装置の製造方法。 In claim 7,
In the steps (c) and (d), the first and second semiconductor elements are mounted so that the wiring pattern formed on the tape carrier and the electrode are connected by a bonding wire. A method of manufacturing a semiconductor device. 縁領域と、該縁領域の間の半導体搭載領域と、前記縁領域に所定のピッチで配列された第１の孔と、該第１の孔の間に、該第１の孔と同列に前記所定のピッチで配列された第２の孔とを有するテープキャリアと、
回路素子と、該回路素子に電気的に接続された電極とを有し、前記第１の孔を基準として前記半導体搭載領域の第１の位置に搭載された第１の半導体素子と、
回路素子と、該回路素子に電気的に接続された電極とを有し、第２の孔を基準として前記半導体搭載領域の第２の位置に搭載された第１の半導体素子とを備えることを特徴とする半導体装置。 An edge region, a semiconductor mounting region between the edge regions, a first hole arranged in the edge region at a predetermined pitch, and the first hole between the first hole and the first hole. A tape carrier having second holes arranged at a predetermined pitch;
A first semiconductor element having a circuit element and an electrode electrically connected to the circuit element, the first semiconductor element being mounted at a first position of the semiconductor mounting region with respect to the first hole;
A circuit element and an electrode electrically connected to the circuit element, and a first semiconductor element mounted at a second position of the semiconductor mounting region with respect to the second hole. A featured semiconductor device. 請求項１０において、
前記第１の孔と前記第２の孔との間の間隔は、等しく設定されていることを特徴とする半導体装置。 In claim 10,
A distance between the first hole and the second hole is set to be equal. 請求項１０または請求項１１において、
前記所定のピッチは、４．７５ｍｍであることを特徴とする半導体装置。 In claim 10 or claim 11,
The semiconductor device according to claim 1, wherein the predetermined pitch is 4.75 mm.
JP2004141401A 2004-05-11 2004-05-11 Tape carrier, semiconductor device manufacturing method, and semiconductor device Expired - Lifetime JP4070135B2 (en)

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US11/073,766 US20050252828A1 (en) 2004-05-11 2005-03-08 Carrier tape, a method of manufacturing an electronic device with the carrier tape, and a tape carrier package with the carrier tape
KR1020050021315A KR101162939B1 (en) 2004-05-11 2005-03-15 A carrier tape, a method of manufacturing an electronic device with the carrier tape, and a tape carrier package with the carrier tape
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JP3398106B2 (en) 1999-12-24 2003-04-21 株式会社鈴木 Drilling method for film for electronic parts
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JP3994809B2 (en) * 2002-07-09 2007-10-24 株式会社日立ハイテクノロジーズ Electronic circuit component punching device and its supply reel replacement method
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