CN103187385A - Substrate for chip-on-film (COF) package - Google Patents
Substrate for chip-on-film (COF) package Download PDFInfo
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- CN103187385A CN103187385A CN2011104543037A CN201110454303A CN103187385A CN 103187385 A CN103187385 A CN 103187385A CN 2011104543037 A CN2011104543037 A CN 2011104543037A CN 201110454303 A CN201110454303 A CN 201110454303A CN 103187385 A CN103187385 A CN 103187385A
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Abstract
The invention discloses a substrate, in particular to the substrate for a chip-on-film (COF) package. The substrate comprises a flexible film, a plurality of driving holes and a plurality of first chip setting regions. The plurality of driving holes are formed in two sides of the flexible film along a first direction. The plurality of first chip setting regions are formed on the flexible film along the first direction, and each of the plurality of first chip setting regions is provided with at least one test module, an input module, a chip and an output module along a second direction. The first direction is perpendicular to the second direction.
Description
Technical field
The present invention relates to a kind of substrate of membrane of flip chip encapsulation, relate in particular to a kind of substrate of the membrane of flip chip encapsulation that can significantly reduce production costs.
Background technology
LCD screen (Liquid Crystal Display, LCD) have that external form is frivolous, characteristic such as low power consumption and low radiation, be widely used on the information products such as calculator system, mobile phone, PDA(Personal Digital Assistant), digital camera and dull and stereotyped calculator.Generally speaking, the driving chip of LCD screen (Driving chip) can utilize membrane of flip chip encapsulation (Chip on Film, COF), winding encapsulation (Tape Carrier Package, TCP) and glass flip chip encapsulation (Chip on Glass, COG) etc. technology will drive chip and be arranged on a display, to dwindle required circuit area.Be compared to winding encapsulation technology and glass flip chip encapsulation technology, the membrane of flip chip encapsulation need not form component holes and can directly be engaged to winding, preferable pin intensity can be provided and use trickleer pin-pitch; Moreover two layers of soft materials of no glue are used in the membrane of flip chip encapsulation, will provide preferable pliability and more frivolous size, and the juncture of inter-module also provide and more driving components, passive component or many integration conveniences that drive chip chamber.
Please refer to Fig. 1, Fig. 1 is a substrate 10 schematic diagrames of known film chip package.Be that the substrate 10 of 48 millimeters membrane of flip chip encapsulation is example with width traditionally, as shown in Figure 1, substrate 10 comprises a plurality of driving holes 100 and a plurality of chips setting area 102 on the XY plane.Driving hole 100 is to prolong the Y direction setting, and uniformly-spaced the position is in the both sides of substrate 10.102 of each chip setting areas are used for arranging a chip 1020, an input module 1022, an output module 1024 and at least one test module 1026 at the adjacent driving hole 100 in the central area and the left and right sides of substrate 10.In addition, as shown in Figure 1, chip setting area 102 is to be set parallel to each other along Y direction, and chip 1020, input module 1022, output module 1024 and test module 1026 also be arranged in parallel along Y direction.If deduction driving hole 100 is behind the width of substrate 10 both sides, chip setting area 102 actual width that can use on X-direction only is 41 millimeters, and the number of pins of corresponding output module 1024 is 1100, and pin-pitch (Pin pitch) is 37 microns.Yet along with the lifting of the quality of image and the consideration of cost, suitable driving chip pin number must significantly increase, and is 1440 as improving number of pins, and in the case, pin-pitch must be dwindled again, to satisfy the limited chip setting area of area.Therefore, if in limited chip setting area, increase number of pins simultaneously and reduce pin-pitch, to cause each pin widths more and more thin, except pin intensity descends and the pin place of display also need the better interconnection technique of arranging in pairs or groups, so will increase production cost.
Therefore, when increasing number of pins along with pursuit high image quality image is corresponding, provide a kind of more effective arrangements of chips mode, in limited chip setting area, need not sacrifice pin-pitch, become the important issue of this area.
Summary of the invention
Therefore, main purpose of the present invention namely is to disclose a kind of substrate of membrane of flip chip encapsulation, need not sacrifice pin-pitch to reach, can increase the purpose of number of pins simultaneously again in limited chip setting area.
The present invention discloses a kind of substrate, includes a pliability film; A plurality of driving holes are formed on the both sides of this pliability film along a first direction; And a plurality of first chip setting areas, be formed on this pliability film along this first direction, each first chip setting area of these a plurality of first chip setting areas is provided with at least one test module, an input module, a chip and an output module along a second direction; Wherein, this first direction is vertical with this second direction.
Description of drawings
Fig. 1 is the substrate schematic diagram of known film chip package.
Fig. 2 is the substrate schematic diagram of embodiment of the invention membrane of flip chip encapsulation.
Fig. 3 is the substrate schematic diagram of another embodiment of the present invention membrane of flip chip encapsulation.
Fig. 4 is the variation schematic diagram of substrate shown in Figure 3.
Fig. 5 is the preserving type schematic diagram of membrane of flip chip encapsulation technology of the present invention.
Wherein, description of reference numerals is as follows:
10,20,30,40 substrates
100,202 driving holes
102 chip setting areas
1020,2044,3044 chips
1022,2042,3042 input modules
1024,2046,3046 output modules
1026,2040,3040 test modules
200 pliability films
204 first chip setting areas
210 first chip modules
304 second chip setting areas
4040 share test module
50 preserve substrate
The H first chip setting area height
Embodiment
Please refer to Fig. 2, Fig. 2 is a substrate 20 schematic diagrames of embodiment of the invention membrane of flip chip encapsulation.Be compared to the substrate 10 of Fig. 1, substrate 20 of the present invention also has similar constituent components, yet, both but have diverse technical characterictic at the arrangement mode of constituent components, when increasing to solve pin number, in limited chip setting area, but can keep script or preferable pin-pitch, and utilize identical process work bench collocation to change the fabrication steps of a little, to reach identical membrane of flip chip encapsulation technology.
As shown in Figure 2, substrate 20 prolongs Y direction and extends on the XY plane, for purpose of brevity, only shows substrate 20 with finite length at this.In addition, as well known to the skilled person, the XY plane is common coordinate setting mode, in order to the plane of representing that two vertical direction (X-direction, Y direction) extend.Specifically, substrate 20 includes a pliability film 200, a plurality of driving hole 202 and a plurality of first chip setting area 204.Pliability film 200 is the chip carrier of a flexible printer circuit film (Flexible printed circuit film), preferably comprising double-layer structure is a paper tinsel (PI) layer and a bronze medal (CU) layer, by rubbing method (Casting), pressing method (Laminate), sputter/galvanoplastic (Sputtering/Plating), or have similar glutinous/mode of applying effect pastes to form the flexible characteristic mutually, and adjusts its material size or processing procedure mode according to different demands; Because non-major technique feature of the present invention does not add detailed description at this.Moreover driving hole 202 parallel Y-axis are formed on the both sides of pliability film 200, uniformly-spaced arrange each other, carry out winding (reel-to-reel) processing so that pliability film 200 conveniently to be provided.
In addition, as shown in Figure 2, the first chip setting area 204 is formed on the pliability film 200, and arranges in regular turn along Y direction.X-direction be arranged in parallel two test modules 2040, an input module 2042, a chip 2044 and an output module 2046 are prolonged in arbitrary first chip setting area 204, namely the first chip setting area 204 can be cut into a plurality of parallel long rectangles, and those long rectangles are test module 2040, input module 2042, chip 2044 and output module 2046, the putting position of those long rectangles only is illustrative among Fig. 2, can adjust according to the different demands of user.Wherein, pin engaged that (Inner lead bonding is ILB) to the printed circuit (not being shown among the figure) of display in input module 2042 provided; Output module 2046 provides outer pin to engage that (Outer lead bonding is OLB) to the glass substrate (not being shown among the figure) of display; Test module 2040 also is electrically connected to chip 2044 by a plurality of pins, in order to check whether chip 2044 can normal operation.For chip 2044, by any combination or independent the use as laminating types such as eutectic joint, anisotropy conducting film or non-conductive glue, chip 2044 can be fixed on the pliability film 200, form the complex root pin by a plurality of wafer bumps again, common is golden projection (Gold bumping) or Solder Bumps (Solder bumping), can be electrically connected to through hot pressing on the corresponding pin of test module 2040, input module 2042 and output module 2046.After but module 2040 is tested normal operations after tested as if chip 2044, a plurality of first chip setting areas 204 are the mode by die-cut (Punch) again, be cut into the first single chip setting area 204 one by one, it will keep input module 2042, chip 2044 and output module 2046 and form one first chip module (not shown), and the end product of membrane of flip chip encapsulation technology is provided.
In simple terms, the first chip setting area 204 as shown in Figure 2 is compared to known technology, the number of pins of input module 2042 and output module 2046 will no longer be subject to the substrate width, for example be 48 millimeters, and can be according to different user's demands, extend in the first chip setting area height H of Y direction arbitrarily, count demand to satisfy more pins, form the arrangement mode of a kind of more effective chip setting area.
Please refer to Fig. 3, Fig. 3 is a substrate 30 schematic diagrames of another embodiment of the present invention membrane of flip chip encapsulation.Be compared to substrate shown in Figure 2 20, substrate 30 shown in Figure 3 is also by the identical assembly of forming, and only substrate 30 more provides a plurality of second chip setting areas 304, and for purpose of brevity, the quantity that Fig. 3 shows is reduced to one group.Specifically, the second chip setting area 304 and the first chip setting area 204 have identical composition assembly and structure are set, namely the second chip setting area 304 also includes at least one test module 3040, an input module 3042, a chip 3044 and an output module 3046, and the second chip setting area 304 corresponds to a side of the first chip setting area 204, and it is adjacent one another are to prolong X-direction by test module 2040,3040.In other words, substrate 30 prolongs X-direction can see that the first chip setting area 204 and the second chip setting area 304 arrange in regular turn, only is illustrative at this number of the arrangement and sequencing.
In the application, substrate 30 is also continued to use the identical die-cut mode of substrate 20, keep input module 2042 (3042), chip 2044 (3044) and output module 2046 (3046), the first chip setting area 204 (the second chip setting area 304) is punched to the first single chip setting area 204 (the second chip setting area 304), to form first chip module (second chip module).In other words, the user can be according to different demands, and cost not only can be saved in a plurality of chip setting area side by side under the first identical chip setting area height H, more can form the another kind of effectively arrangement mode of chip setting area.In the case, the quantity side by side of chip setting area only is illustrative, and is non-in order to limit category of the present invention.
Please refer to Fig. 4, Fig. 4 is the variation schematic diagram of the substrate 30 of Fig. 3.As shown in Figure 4, the test module 2040 of the first chip setting area 204 and the test module 3040 of the second chip setting area 304 in the substrate 40 further integration maps 3, the second chip setting area, 304 1 angles, 180 degree in the rotation diagram 3, forming a mirror arranges, namely put upside down the second chip setting area 304 and prolong the constituent components of X-direction, share test module 4040 in order to form one.Share the identical characteristics of test module 4040 continuity test modules 2040 (3040), can carry out the adjustment of area size according to the different demands of user, can can distinguish measuring chip 2044,3044 normal operation, also under the limited area of substrate 40, increase its service efficiency, another kind of more effective arrangements of chips mode is provided.In the case, substrate 40 is also undertaken die-cut by sharing test module 4040, the first chip setting area 204 and the second chip setting area 304 are punched to the first single chip module and second chip module so that independent running to be provided, except the arrangement mode that forms another kind of effectively chip setting area, again under the first identical chip setting area height H side by side a plurality of chip setting area to save cost.
Noticeable, the present invention is except utilizing a plurality of driving holes 202 that winding (reel-to-reel) Punching Technology is provided, above-mentioned substrate 20,30,40 can not preserved by the mode of a left and right sides folding before the Punching Technology as yet, as shown in Figure 5, a kind of substrate preserving type that can corresponding membrane of flip chip encapsulation technology of the present invention, and preserve substrate 50 after die-cut, a plurality of first chip modules 210 be can form, and input module 2042, chip 2044 and output module 2046 remained with.
Certainly, the arrangement mode of chip setting area proposed by the invention only is illustrative, the user can be according to developed width or the different demand of pliability film, preferably adjust the arrangement mode of chip setting area in regular turn, as long as it is parallel to each other that its test module of maintenance, input module, chip and output module prolong X-direction, arrange in pairs or groups again different quantity side by side and die-cut mode, need not sacrifice pin-pitch in order to reach, simultaneously can in limited chip setting area, increase number of pins again, all belong to category of the present invention.
In sum, the present invention is by proposing the arrangement mode of different chip setting areas, being compared to known technology chips setting area prolongs X-direction and only sees single constituent components, X-direction is prolonged in chip of the present invention setting area can see that many fabrics become assembly, and adjacent position each other more can be adjusted to fitting property in a plurality of chips setting area, preferably, when the left and right sides, a plurality of chips setting area is adjacent, except sharing constituent components (as sharing test module), more can be considered as symmetry axis with sharing constituent components, form identical structure arranged or mirror structure arranged, in order in limited chip setting area, need not sacrifice pin-pitch, but can increase number of pins to increase the area utilization ratio of chip setting area.For the user, can significantly reduce production costs, satisfy the display demand of high image quality image.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. substrate includes:
One pliability film;
A plurality of driving holes are formed on the both sides of this pliability film along a first direction; And
A plurality of first chip setting areas are formed on this pliability film along this first direction, and each first chip setting area of these a plurality of first chip setting areas is provided with at least one survey along a second direction
Die trial piece, an input module, a chip and an output module;
Wherein, this first direction is vertical with this second direction.
2. substrate as claimed in claim 1, it is characterized in that, this substrate also comprises a plurality of second chip setting areas, be formed on this pliability film along this first direction, and be formed on a side of these a plurality of first chip setting areas along this second direction, each second chip setting area of these a plurality of second chip setting areas is provided with at least one test module, an input module, a chip and an output module along this second direction.
3. substrate as claimed in claim 2 is characterized in that, a test module of a test module of one second chip setting area and adjacent one first chip setting area is incorporated into one and shares test module in these a plurality of second chip setting areas.
4. substrate as claimed in claim 1 is characterized in that, this test module, this input module and this output module electric property coupling are at this chip.
5. substrate as claimed in claim 4 is characterized in that, whether this chip can normal operation by this test module inspection.
6. substrate as claimed in claim 4 is characterized in that, this input module and this output module are electrically coupled to a display and drive this chip.
7. substrate as claimed in claim 1 is characterized in that, this pliability film comprises double-layer structure, is respectively a paper tinsel layer and a bronze medal layer.
8. substrate as claimed in claim 1 is characterized in that, these a plurality of first chip setting areas are punched to single first chip module in order to independent running.
9. substrate as claimed in claim 2 is characterized in that, these a plurality of second chip setting areas are punched to single second chip module in order to independent running.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011104543037A CN103187385A (en) | 2011-12-30 | 2011-12-30 | Substrate for chip-on-film (COF) package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011104543037A CN103187385A (en) | 2011-12-30 | 2011-12-30 | Substrate for chip-on-film (COF) package |
Publications (1)
| Publication Number | Publication Date |
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| CN103187385A true CN103187385A (en) | 2013-07-03 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011104543037A Pending CN103187385A (en) | 2011-12-30 | 2011-12-30 | Substrate for chip-on-film (COF) package |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI578487B (en) * | 2015-09-24 | 2017-04-11 | 聯詠科技股份有限公司 | Chip-on-film package |
| TWI664611B (en) * | 2016-10-31 | 2019-07-01 | 大陸商昆山工研院新型平板顯示技術中心有限公司 | Driving circuit carrier, display panel, flat panel display and manufacturing method |
| CN110473852A (en) * | 2018-05-11 | 2019-11-19 | 瑞鼎科技股份有限公司 | The encapsulating structure of driving device applied to display |
| CN111913602A (en) * | 2019-05-08 | 2020-11-10 | 敦泰电子有限公司 | Display touch control driving chip |
| WO2021223294A1 (en) * | 2020-05-08 | 2021-11-11 | 武汉华星光电半导体显示技术有限公司 | Chip on film |
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| US20050252828A1 (en) * | 2004-05-11 | 2005-11-17 | Yoshikazu Takahashi | Carrier tape, a method of manufacturing an electronic device with the carrier tape, and a tape carrier package with the carrier tape |
| CN101409275A (en) * | 2007-11-28 | 2009-04-15 | 上海长丰智能卡有限公司 | Double-interface smart card module and loading belt |
| CN101471321A (en) * | 2007-12-29 | 2009-07-01 | 南茂科技股份有限公司 | Load bearing belt for packing chip and chip packaging structure |
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- 2011-12-30 CN CN2011104543037A patent/CN103187385A/en active Pending
Patent Citations (3)
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| US20050252828A1 (en) * | 2004-05-11 | 2005-11-17 | Yoshikazu Takahashi | Carrier tape, a method of manufacturing an electronic device with the carrier tape, and a tape carrier package with the carrier tape |
| CN101409275A (en) * | 2007-11-28 | 2009-04-15 | 上海长丰智能卡有限公司 | Double-interface smart card module and loading belt |
| CN101471321A (en) * | 2007-12-29 | 2009-07-01 | 南茂科技股份有限公司 | Load bearing belt for packing chip and chip packaging structure |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI578487B (en) * | 2015-09-24 | 2017-04-11 | 聯詠科技股份有限公司 | Chip-on-film package |
| US11069586B2 (en) | 2015-09-24 | 2021-07-20 | Novatek Microelectronics Corp. | Chip-on-film package |
| TWI664611B (en) * | 2016-10-31 | 2019-07-01 | 大陸商昆山工研院新型平板顯示技術中心有限公司 | Driving circuit carrier, display panel, flat panel display and manufacturing method |
| US10665151B2 (en) | 2016-10-31 | 2020-05-26 | Kunshan New Flat Panel Display Technology Center Co., Ltd. | Driver circuit carrier, display panel, tablet display, and manufacturing method |
| CN110473852A (en) * | 2018-05-11 | 2019-11-19 | 瑞鼎科技股份有限公司 | The encapsulating structure of driving device applied to display |
| CN110473852B (en) * | 2018-05-11 | 2022-05-13 | 瑞鼎科技股份有限公司 | Packaging structure applied to driving device of display |
| CN111913602A (en) * | 2019-05-08 | 2020-11-10 | 敦泰电子有限公司 | Display touch control driving chip |
| CN111913602B (en) * | 2019-05-08 | 2023-08-15 | 敦泰电子有限公司 | Display touch control driving chip |
| WO2021223294A1 (en) * | 2020-05-08 | 2021-11-11 | 武汉华星光电半导体显示技术有限公司 | Chip on film |
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Application publication date: 20130703 |