CN101471321A - Load bearing belt for packing chip and chip packaging structure - Google Patents
Load bearing belt for packing chip and chip packaging structure Download PDFInfo
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- CN101471321A CN101471321A CNA2007103073856A CN200710307385A CN101471321A CN 101471321 A CN101471321 A CN 101471321A CN A2007103073856 A CNA2007103073856 A CN A2007103073856A CN 200710307385 A CN200710307385 A CN 200710307385A CN 101471321 A CN101471321 A CN 101471321A
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- 238000004806 packaging method and process Methods 0.000 title claims description 118
- 238000012856 packing Methods 0.000 title abstract description 6
- 238000012360 testing method Methods 0.000 claims abstract description 158
- 230000005540 biological transmission Effects 0.000 claims description 14
- 230000009977 dual effect Effects 0.000 claims description 7
- 239000002699 waste material Substances 0.000 abstract description 4
- 238000005520 cutting process Methods 0.000 abstract description 2
- 238000005538 encapsulation Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000000523 sample Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000004804 winding Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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Abstract
The invention relates to a bearing strip used for packing chips and a chip packing structure, wherein a plurality of sharing testing pads are arranged in a testing pad area of two packing areas on the bearing strip, which are simultaneously electrically connected with the two packing areas, which reduces the area of the testing pad on the bearing strip, reduces cutting waste, and can save repeated acting time of electrical testing devices in electrical testing, thereby improving testing efficiency.
Description
Technical field
The invention relates to a kind of carrying band and chip-packaging structure that is used for packaged chip; Particularly a kind of carrying band and chip-packaging structure with shared test pad area.
Background technology
Along with progress of industry, the electronic product of various LCD screen, tool folder function is widely used in the daily life.Wherein because flexible circuit board has thin thickness, pin-pitch is little and pin is counted advantages of higher, when LCD screen in order to save the space, or electronic product is when reaching folding function, flexible circuit board just becomes indispensable element.
Generally speaking, flexible circuit board is to utilize chip encapsulation technology, and semiconductor chip is engaged thereon.Wherein, the automatic bond package of winding (Tape Automatic Bonding, TAB) technology is chip to be fixed in carrying be with, and with the projection or the weld pad of chip, engage with the metal lead wire layer contraposition pressurization of carrying band, be one of present modal chip encapsulation technology.It can be divided into again winding carrying encapsulation (Tape CarrierPackage, TCP) and membrane of flip chip encapsulation (Chip-On-Film, COF) two kinds of encapsulation patterns.
Figure 1 shows that the schematic diagram of existing chip encapsulating structure 1, chip-packaging structure 1 comprises carrying and is with 10, and carrying is with 10 to have a plurality of location holes 111, a plurality of testing cushion 131,131 ', the first pin part 141 and the second pin part 142.Wherein, a plurality of location holes 111 are along a throughput direction X, are distributed in the dual side-edge that carries with 10, are with 10 in order to carry this carrying, or in order to location carrying with 10 position be with on 10 or link a testing electrical property device (figure does not show) and carry out testing electrical property so that chip 21 is engaged to carrying.
For convenience of description, as shown in Figure 1, carrying with 10 on definition one packaging area 121 and two test pad area 13,13 ' that lay respectively at packaging area 121 2 sides, wherein, packaging area 121 is to be arranged between the location hole 111 of carrying with 10 dual side-edges, and along throughput direction X distribution, chip 21 is to be arranged in the packaging area 121, and testing cushion 131,131 ' is to be arranged at respectively on first test pad area 13 and second test pad area 13 '.And the first pin part 141 extends to first test pad area 13 and testing cushion 131 electrically connects from encapsulation zone 121, and the second pin part 142 extends to second test pad area 13 ' and testing cushion 131 ' electrically connect from encapsulation zone 121.
Because chip 21 is to be engaged in carrying with 10 packaging area 121, and with input and output (scheming not show) respectively with the first pin part 141 and the second pin part, 142 electrically connects, to constitute this chip-packaging structure 1.Thus, the input of chip 21 and output can pass through the first pin part 141 and the testing cushion 131 of the second pin part, 142 electrically connect to the first test pad area 13 and the testing cushion 131 ' of second test pad area 13 ' respectively.Finish packaged chip 21 in carrying with 10 packaging area 121 in after, in case the testing electrical property device just can carry out testing electrical property to chip 21 with probe simultaneously electrically connect testing cushion 131 and testing cushion 131 '.
Can know by Fig. 1 and to find out that on the existing chip encapsulating structure 1, testing cushion 131,131 ' is to be disposed at each chip 21 2 side respectively.After the testing electrical property of chip 21 was finished, first test pad area 13 and second test pad area 13 ' all need cut removal, only stayed chip 21, the first pin part 141 and the second pin part 142 on the packaging area 121.Can infer ground, if first test pad area 13 and second test pad area, 13 ' the employed zone are bigger, the part that cuts removal the more, this will cause carrying with 10 unnecessary wastes.In addition, existing chip encapsulating structure 1, when carrying out to chip 21 testing electrical properties, it is probe with the testing electrical property device, in proper order and repeatedly testing cushion 131 and testing cushion 131 ' are carried out the action that electrically connects, this testing electrical property need move probe repeatedly, causes spending a large amount of processing procedure times, makes production test efficient not good.
In view of this, providing a kind of carrying band and chip-packaging structure that reduces the amount of cutting and promote testing efficiency, is this field problem demanding prompt solution.
Summary of the invention
A purpose of the present invention is to provide a kind of carrying band and chip-packaging structure that is used for packaged chip, and two adjacent chip-packaging structures can a shared test pad area, with reduce test pad area in carrying with going up shared area ratio.Because the most cropped removal of test pad area, carrying band of the present invention and chip-packaging structure can reduce because cut the waste that test pad area causes carrying band when test is finished laggard row and cut, and then the saving manufacturing cost.
Another object of the present invention is to provide a kind of carrying band and chip-packaging structure that is used for packaged chip, because two adjacent chip-packaging structures can utilize a shared test pad area and a testing electrical property device to electrically connect, so the testing electrical property device can simultaneously or carry out testing electrical property to two chips separately, the action that the probe that can reduce tester table at least and testing cushion contact repeatedly and break away from, and then the activity duration of saving testing electrical property, promote production testing efficient.
For reaching above-mentioned purpose, carrying provided by the present invention brings to and includes two transmission regions, two packaging areas, a test pad area, a plurality of testing cushion and a metallic circuit layer less.These transmission regions are defined in the dual side-edge of this carrying band respectively, and extend along a throughput direction; These packaging areas are to be defined between these transmission regions, distribute along this throughput direction; This test pad area is to be defined between these packaging areas, for these testing cushion settings thereon; This metallic circuit layer is to be distributed on these packaging areas.Wherein, these packaging areas comprise one first packaging area and one second packaging area, and this metallic circuit layer comprises first pin part and that extends to this test pad area from this first packaging area at least and extends to the second pin part of this test pad area from this second packaging area.It is characterized by this first pin part and this second pin part, is in this test pad area, these common testing cushion of corresponding connection.
The present invention also provides a kind of chip-packaging structure, it is to use above-mentioned carrying band, and also comprise one first chip and one second chip, be arranged at respectively this carrying with on this first packaging area and this second packaging area, this first chip and this first pin partly electrically connect, and this second chip and this second pin partly electrically connect.Whereby, this first chip and this second chip are linked to these corresponding testing cushion simultaneously by this first pin part and this second pin part, and then make this first chip and this second chip be connected to the testing electrical property device simultaneously by these testing cushion, carry out testing electrical property.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is elaborated, wherein:
Fig. 1 is the schematic diagram of existing chip-packaging structure;
Fig. 2 is the schematic diagram that band is carried in the present invention; And
Fig. 3 is the schematic diagram of chip-packaging structure of the present invention.
The main element symbol description:
1 chip-packaging structure, 10 carrying bands
111 location holes, 121 packaging areas
13 first test pad area, 13 ' second test pad area
131 testing cushion, 131 ' testing cushion
141 first pin parts, 142 second pin parts
21 chips, 3 carrying bands
31 transmission regions, 311 location holes
321 first packaging area 321a chip bonding area
322 second packaging area 322a chip bonding area
33 test pad area, 331 testing cushion
Pin in the 341 first pin part 341a first
The 341b first outer pin 342 second pin parts
The pin 342b second outer pin in the 342a second
343 the 3rd pin parts 344 the 4th pin part
4 chip-packaging structures, 41 first chips
42 second chip X throughput directions
Embodiment
One embodiment of the invention disclose a kind of carrying that is used for packaged chip and are with 3, be to extend along a throughput direction X, as shown in Figure 2, carrying is with 3 including two transmission regions 31, two packaging areas 321 and 322, one test pad area 33 at least, being arranged at a plurality of testing cushion 331 and a metallic circuit layer on the test pad area 33.
In present embodiment, carrying is with 3 two transmission regions 31, is defined in carrying respectively and extends with 3 dual side-edge and along throughput direction X, and is clearer and more definite, be formed with arranged in order on the transmission region 31, and be adjacent to a plurality of location holes 311 of carrying with 3 dual side-edge along this throughput direction X.Carrying is with 3 to be to transmit and the location by location hole 311, for example when carrying is with 3 to be positioned to a position, fits and can carry out Chip Packaging, cuts and be positioned the another location afterwards.
For convenience of description, packaging area 321 and 322 can be divided into first packaging area 321 and second packaging area 322, is defined between two transmission regions 31.Must explanation be, carrying is to prolong throughput direction X to distribute in proper order with a plurality of packaging areas on 3, present embodiment only at two adjacent packaging areas wherein as illustration, non-in order to limit the present invention.Wherein, first packaging area 321 and second packaging area 322 respectively comprise a chip bonding area 321a and a 322a, use for the chip setting.
Be different from that test pad area is separately corresponding to packaging area in the prior art, so must have two test pad area between the two adjacent packaging areas, only be provided with a shared test pad area 33 between first packaging area 321 of present embodiment and second packaging area 322.Owing to be arranged at carrying with each test pad area 33 on 3, in Chip Packaging in each chip bonding area 321a and 322a and finish packaging and testing after, all must cut removal, so present embodiment adopts shared test pad area 33, can significantly reduce the number and the area of test pad area 33, can significantly reduce the unnecessary waste of packing bearing belt, and then reduce packaging cost.
In addition, the metallic circuit layer is to be distributed on first packaging area 321 and second packaging area 322, and extend in the test pad area 33, for convenience of description, metallic circuit layer definable comprises the first pin part 341, the second pin part 342, the 3rd pin part 343 and the 4th pin part 344.In present embodiment, the first pin part 341 is to extend in the test pad area 33 from first packaging area 321, and the second pin part 342 is to extend in the test pad area 33 from second packaging area 322, and the first pin part 341 and the second pin part 342, in this test pad area 33, connect corresponding testing cushion 331 respectively.Whereby, only need use a shared test pad area 33 between first packaging area 321 and second packaging area 322, just can supply follow-up testing electrical property.
Preferably, in the first pin part 341 of the present invention and the second pin part 342 are the pins with equal number, therefore each pin of the first pin part 341 just can be connected to corresponding testing cushion 331 respectively with each pin of the second pin part 342, is more convenient for the carrying out of testing electrical property.
In addition, the 3rd pin part 343 is with respect to the first pin part 341, be arranged at the opposite side of the chip bonding area 321a in first packaging area 321, and extend to the shared test pad area of another and other packaging area (figure does not show) from first packaging area 321; And the 4th pin part 344 is the opposite sides that are arranged at the chip bonding area 322a in second packaging area 322 with respect to the second pin part 342, and extends to the shared test pad area of another and other packaging area (figure does not show) from second packaging area 322.
And be with chip join and be connected testing cushion 331, the first pin parts 341 and comprise pin 341a and one first outer pin 341b in one first that the second pin part 342 comprises one second interior pin 342a and one second outer pin 342b.The pin 341a and the second interior pin 342a extend respectively in chip bonding area 321a and the 322a in first, in order to engage with the projection of chip respectively.And the first outer pin 341b and the second outer pin 342b extend in the test pad area 33 from first packaging area 321 and second packaging area 322 respectively, and are electrically connected at corresponding testing cushion 331.Be packaged in each chip in each packaging area 321,322, just a plurality of projection electrically connects by each chip are somebody's turn to do interior pin 341a and 342a, and by the testing cushion 331 in outer pin 341b, the 342b electrically connect test pad area 33, so that follow-uply carry out testing electrical property by testing cushion 331.Similarly, aforesaid the 3rd pin part 343 and the 4th pin part 344 also comprise inside and outside pin respectively, do not give unnecessary details in addition at this.
Please refer to Fig. 3, be depicted as the schematic diagram of the disclosed chip-packaging structure 4 of the second embodiment of the present invention, this chip-packaging structure 4 comprises aforesaid carrying and is with 3, and more first chip 41 and second chip 42 is engaged in carrying and is with on 3.First chip 41 and second chip 42 are to be arranged at carrying respectively with first packaging area 321 on 3 and chip bonding area 321a, the 322a (as shown in Figure 2) in second packaging area 322.The first pin part 341 comprises the pin 341a and the first outer pin 341b in first, the second pin part 342 comprises the pin 342a and the second outer pin 342b in second, the pin 341a and the second interior pin 342a are respectively in chip bonding area 321a, the 322a in first, projection with first chip 41 and second chip 42 electrically connects respectively, the first outer pin 341b and the second outer pin 342b then extend in the test pad area 33 from first packaging area 321 and second packaging area 322 respectively, and are electrically connected to corresponding testing cushion 331.Carrying with other detailed structure of 3 as above-mentioned carrying with 3 structure, do not give unnecessary details at this.
Testing cushion 331 on the test pad area 33, after first chip 41 and second chip 42 are engaged to first packaging area 321 and second packaging area 322 respectively and finish encapsulation, can an external testing electrical property device (figure does not show), so that first chip 41 and second chip 42 are carried out a testing electrical property.And be connected to identical testing cushion 331 because of the first pin part 341 and the second pin part 342, therefore to being packaged in different chips in first packaging area 321 and second packaging area 322 when carrying out testing electrical property, only need carry out the action that a time testing cushion 331 is electrically connected to the testing electrical property device, so can save the activity duration of testing electrical property, production efficiency is significantly promoted.
For example, the first pin part 341 is inputs that are connected in first chip 41 by the first interior pin 341a, and the second pin part 342 is inputs that are connected in second chip 42 by the second interior pin 342a, an output that the 3rd pin part 343 of carrying band and 344 of the 4th pin parts are connected to first chip 41 and an output of second chip 42.Thus, testing cushion 331 can be simultaneously electrically connects with the input of first chip 41 and second chip 42.Probe (figure does not show) and testing cushion 331 electric connections when the testing electrical property device just can pass through the first pin part 341 and the second pin part 342 at the same time or separately, to first chip 41 and second chip 42, carry out a testing electrical property.Preferably, the first pin part 341 and the second pin part 342 can have the pin of equal number, and be linked to testing cushion 331 with the first pin part 341 or the second pin part, 342 equal numbers, the testing electrical property device only need carry out once the action to testing cushion 331 electrically connects, just can test first chip 41 and second chip 42 at the same time or separately, the testing electrical property device does not need to carry out continually Plug Action.
Perhaps, the first pin part 341 is the outputs that can be connected in first chip 41, and the second pin part 342 is the outputs that can be connected in second chip 42, and the 3rd pin part 343 is connected in the input of first chip 41, and the 4th pin part 344 is connected in the input of second chip 42.Thus, testing cushion 331 can be simultaneously electrically connects with the output of first chip 41 and second chip 42, and other structure is then identical with aforementioned enforcement aspect, does not give unnecessary details at this.
In the above embodiment of the present invention, first chip 41 can be identical chip in fact with second chip 42, perhaps is different chips, all can implement notion of the present invention.Only need design the first pin part 341 and the second pin part 342 are extended to shared test pad area 33, and connect corresponding testing cushion 331 simultaneously.For example, if first chip 41 is two identical chips with second chip 42, then only this identical two chip need be symmetricly set in carrying is with on 3, input or output that the mutual adjacent side of chip just can have identical quantity, therefore can use the first pin part 341 and the second pin part 342 of same pin quantity easily, be electrically connected at the testing cushion 331 of equal number simultaneously.But, also can reach the purpose that the present invention uses shared test pad area equally by the design of pin and testing cushion if first chip 41 is different from second chip 42.
By above-mentioned carrying with 3 structure, carrying can save with 3 that the shared carrying zone face of two test pad area need be set between packaging area adjacent in the prior art is long-pending, make carrying be with 3 behind testing electrical property, the part that need cut removal reduces, can utilize the carrying band more fully, and then save material cost.And with chip join after, chip-packaging structure 4 of the present invention can link the testing electrical property device by shared test pad area 33, and then carry out testing electrical property respectively or simultaneously, the testing electrical property device more need not carried out frequent Plug Action, more can save the activity duration of testing electrical property, significantly quicken production efficiency, reduce production costs.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little modification and perfect, so protection scope of the present invention is when with being as the criterion that claims were defined.
Claims (12)
1. carrying band that is used for packaged chip, be suitable for extending along a throughput direction, this carrying brings to and includes two transmission regions less, two packaging areas, one test pad area, a plurality of testing cushion and a metallic circuit layer, described transmission region is defined in the dual side-edge of this carrying band respectively, and extend along this throughput direction, described packaging area is between described transmission region, distribute along this throughput direction, this test pad area is between described packaging area, for described testing cushion setting thereon, this metallic circuit layer is to be distributed on the described packaging area, wherein, described packaging area comprises one first packaging area and one second packaging area, this metallic circuit layer comprises one first pin part and one second pin part at least, this first pin partly is to extend to this test pad area from this first packaging area, this second pin partly is to extend to this test pad area from this second packaging area, and this first pin part and this second pin part, be in this test pad area, the common described testing cushion of corresponding connection.
2. carrying band as claimed in claim 1 is characterized in that, the described testing cushion on this test pad area is suitable for an external testing electrical property device, to carry out a testing electrical property.
3. carrying band as claimed in claim 1 is characterized in that, this first pin part partly is the pin with equal number with this second pin.
4. carrying band as claimed in claim 1, it is characterized in that, this first packaging area and this second packaging area comprise a chip bonding area respectively, this first pin partly comprises pin and one first outer pin in one first, this second pin partly comprises pin and one second outer pin in one second, this first interior pin and this second interior pin are to extend respectively in this chip bonding area, this first outer pin and this second outer pin are to extend in this test pad area from this first packaging area and this second packaging area respectively, and the common described testing cushion of corresponding connection.
5. carrying band as claimed in claim 1, it is characterized in that, this metallic circuit layer also comprises one the 3rd pin part and one the 4th pin part, the 3rd pin partly is with respect to this first pin part, extend from this first packaging area, the 4th pin partly is with respect to this second pin part, and this second packaging area extends certainly.
6. chip-packaging structure is characterized in that comprising:
One carrying band, be suitable for extending along a throughput direction, this carrying brings to and includes two transmission regions less, two packaging areas, one test pad area, a plurality of testing cushion and a metallic circuit layer, described transmission region is defined in the dual side-edge of this carrying band respectively, and extend along this throughput direction, described packaging area is between described transmission region, distribute along this throughput direction, this test pad area is between described packaging area, for described testing cushion setting thereon, this metallic circuit layer is to be distributed on the described packaging area, wherein, described packaging area comprises one first packaging area and one second packaging area, and this metallic circuit layer comprises one first pin part and one second pin part at least, and this first pin partly is to extend to this test pad area from this first packaging area, this second pin partly is to extend to this test pad area from this second packaging area, and this first pin part and this second pin part are in this test pad area, the common described testing cushion of corresponding connection;
One first chip and one second chip, be arranged at respectively this carrying with on this first packaging area and this second packaging area, this first chip and this first pin partly electrically connect, and second chip and this second pin partly electrically connect.
7. chip-packaging structure as claimed in claim 6, it is characterized in that, described testing cushion on this test pad area, be suitable for an external testing electrical property device, to pass through this first pin part and this second pin part at the same time or separately, to this first chip and this second chip, carry out a testing electrical property.
8. chip-packaging structure as claimed in claim 6, it is characterized in that, this first packaging area and this second packaging area comprise a chip bonding area respectively, this first pin partly comprises pin and one first outer pin in one first, this second pin partly comprises pin and one second outer pin in one second, this first interior pin and this second interior pin are to extend respectively in this chip bonding area, this first outer pin and this second outer pin are to extend in this test pad area from this first packaging area and this second packaging area respectively, and the common described testing cushion of corresponding connection.
9. chip-packaging structure as claimed in claim 6 is characterized in that, this first pin partly is an input that is connected in this first chip, and this second pin partly is an input that is connected in this second chip.
10. chip-packaging structure as claimed in claim 9, it is characterized in that, this carrying band also comprises one the 3rd pin part and one the 4th pin part, and the 3rd pin partly is connected in an output of this first chip, and the 4th pin partly is connected in an output of this second chip.
11. chip-packaging structure as claimed in claim 6 is characterized in that, this first pin partly is an output that is connected in this first chip, and this second pin partly is an output that is connected in this second chip.
12. chip-packaging structure as claimed in claim 11, it is characterized in that, this carrying band also comprises one the 3rd pin part and one the 4th pin part, and the 3rd pin partly is connected in an input of this first chip, and the 4th pin partly is connected in an input of this second chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007103073856A CN101471321B (en) | 2007-12-29 | 2007-12-29 | Load bearing belt for packing chip and chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007103073856A CN101471321B (en) | 2007-12-29 | 2007-12-29 | Load bearing belt for packing chip and chip packaging structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101471321A true CN101471321A (en) | 2009-07-01 |
| CN101471321B CN101471321B (en) | 2010-08-18 |
Family
ID=40828602
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007103073856A Active CN101471321B (en) | 2007-12-29 | 2007-12-29 | Load bearing belt for packing chip and chip packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101471321B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187385A (en) * | 2011-12-30 | 2013-07-03 | 联咏科技股份有限公司 | Substrate for chip-on-film (COF) package |
| CN106803411A (en) * | 2017-03-30 | 2017-06-06 | 昆山工研院新型平板显示技术中心有限公司 | Display device, detection unit and detection method |
| CN108182898A (en) * | 2017-12-28 | 2018-06-19 | 深圳市华星光电半导体显示技术有限公司 | The system of expansion signal path based on PAD |
| CN110393041A (en) * | 2017-03-03 | 2019-10-29 | 硅工厂股份有限公司 | Flexible circuit board for display |
| US10797672B2 (en) | 2017-12-28 | 2020-10-06 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Signal channel expanding system based on PAD |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2852178B2 (en) * | 1993-12-28 | 1999-01-27 | 日本電気株式会社 | Film carrier tape |
| KR100283030B1 (en) * | 1997-12-31 | 2001-03-02 | 윤종용 | Layout structure of semiconductor device |
| JP3717660B2 (en) * | 1998-04-28 | 2005-11-16 | 株式会社ルネサステクノロジ | Film carrier and burn-in method |
| JP2003330041A (en) * | 2002-05-10 | 2003-11-19 | Sharp Corp | Semiconductor device and display panel module provided therewith |
-
2007
- 2007-12-29 CN CN2007103073856A patent/CN101471321B/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187385A (en) * | 2011-12-30 | 2013-07-03 | 联咏科技股份有限公司 | Substrate for chip-on-film (COF) package |
| CN110393041A (en) * | 2017-03-03 | 2019-10-29 | 硅工厂股份有限公司 | Flexible circuit board for display |
| CN106803411A (en) * | 2017-03-30 | 2017-06-06 | 昆山工研院新型平板显示技术中心有限公司 | Display device, detection unit and detection method |
| CN108182898A (en) * | 2017-12-28 | 2018-06-19 | 深圳市华星光电半导体显示技术有限公司 | The system of expansion signal path based on PAD |
| WO2019127753A1 (en) * | 2017-12-28 | 2019-07-04 | 深圳市华星光电半导体显示技术有限公司 | System of expanded signal channels employing pad |
| US10797672B2 (en) | 2017-12-28 | 2020-10-06 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Signal channel expanding system based on PAD |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101471321B (en) | 2010-08-18 |
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