JP2005318582A5 - - Google Patents
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- Publication number
- JP2005318582A5 JP2005318582A5 JP2005118765A JP2005118765A JP2005318582A5 JP 2005318582 A5 JP2005318582 A5 JP 2005318582A5 JP 2005118765 A JP2005118765 A JP 2005118765A JP 2005118765 A JP2005118765 A JP 2005118765A JP 2005318582 A5 JP2005318582 A5 JP 2005318582A5
- Authority
- JP
- Japan
- Prior art keywords
- analog
- digital conversion
- digital
- pipeline
- conversion module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims 43
- 238000000034 method Methods 0.000 claims 8
- 238000011156 evaluation Methods 0.000 claims 6
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100420875A CN100527630C (zh) | 2004-04-30 | 2004-04-30 | 额外模数转换模块校正流水线式模数转换器的方法及装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2005318582A JP2005318582A (ja) | 2005-11-10 |
| JP2005318582A5 true JP2005318582A5 (enExample) | 2008-05-29 |
Family
ID=35346699
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005118765A Pending JP2005318582A (ja) | 2004-04-30 | 2005-04-15 | パイプラインadc較正方法およびその装置 |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2005318582A (enExample) |
| CN (1) | CN100527630C (enExample) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100845134B1 (ko) | 2006-11-06 | 2008-07-09 | 삼성전자주식회사 | 디지털 자동 보정기능을 가지는 파이프 라인아날로그-디지털 변환기 및 그것의 디지털 보정방법 |
| JPWO2011021260A1 (ja) * | 2009-08-18 | 2013-01-17 | パナソニック株式会社 | パイプライン型ad変換器およびその出力補正方法 |
| CN101888246B (zh) * | 2010-06-30 | 2012-12-19 | 中国电子科技集团公司第五十八研究所 | 具有误差校准功能的电荷耦合流水线模数转换器 |
| KR101287097B1 (ko) | 2012-01-17 | 2013-07-16 | 서강대학교산학협력단 | 채널 간 부정합 문제를 최소화한 4채널 파이프라인 sar adc |
| CN110336561B (zh) * | 2019-07-05 | 2021-02-05 | 中国电子科技集团公司第二十四研究所 | 一种流水线型模数转换器及其输出校正方法 |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100261057B1 (ko) * | 1991-08-15 | 2000-07-01 | 윌리엄 비. 켐플러 | 정확도 부스트래핑 |
| US5499027A (en) * | 1994-02-24 | 1996-03-12 | Massachusetts Institute Of Technology | Digitally self-calibrating pipeline analog-to-digital converter |
| JP3413793B2 (ja) * | 1999-01-18 | 2003-06-09 | 横河電機株式会社 | カスケードa/d変換器 |
| US6369744B1 (en) * | 2000-06-08 | 2002-04-09 | Texas Instruments Incorporated | Digitally self-calibrating circuit and method for pipeline ADC |
| US6563445B1 (en) * | 2001-11-28 | 2003-05-13 | Analog Devices, Inc. | Self-calibration methods and structures for pipelined analog-to-digital converters |
-
2004
- 2004-04-30 CN CNB2004100420875A patent/CN100527630C/zh not_active Expired - Lifetime
-
2005
- 2005-04-15 JP JP2005118765A patent/JP2005318582A/ja active Pending
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