JP2005203598A - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP2005203598A JP2005203598A JP2004009025A JP2004009025A JP2005203598A JP 2005203598 A JP2005203598 A JP 2005203598A JP 2004009025 A JP2004009025 A JP 2004009025A JP 2004009025 A JP2004009025 A JP 2004009025A JP 2005203598 A JP2005203598 A JP 2005203598A
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- semiconductor device
- resin
- manufacturing
- semiconductor chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Wire Bonding (AREA)
Abstract
【解決手段】 半導体装置の製造方法は、配線基板10と半導体チップ20との間に樹脂40を設ける工程と、配線基板10に設けられた配線パターン12のランド14と半導体チップ20の電極22との間に配置されたはんだに、ランド14にメッキされた金15を拡散させて、ランド14と電極22とを電気的に接続する導電部32を、金の含有量が30重量%を超えるように形成する工程と、樹脂40を硬化させる工程とを含む。
【選択図】 図5
Description
前記配線基板に設けられた配線パターンのランドと前記半導体チップの電極との間に配置されたはんだに、前記ランドにメッキされた金を拡散させて、前記ランドと前記電極とを電気的に接続する導電部を、金の含有量が30重量%を超えるように形成する工程と、
前記樹脂を硬化させる工程と、
を含む。本発明によれば、導電部を、金の含有量が30重量%を超えるように形成する。これにより、はんだの濡れ性を確保することができるため、フラックスを使用せずに半導体装置を製造することが可能になる。また、樹脂を硬化させることによって、導電部の破断を防止することができるため、信頼性の高い半導体装置を製造することができる。
(2)この半導体装置の製造方法において、
前記樹脂を硬化させる工程を、前記導電部を形成する工程よりも先又は同時に行ってもよい。
(3)この半導体装置の製造方法において、
前記導電部を形成する工程を、フラックスを利用しないで行ってもよい。
(4)本発明に係る半導体装置は、複数のランドを含む配線パターンが設けられた配線基板と、
複数の電極を有し、前記電極が前記配線パターンと対向するように前記配線基板に搭載されてなる半導体チップと、
それぞれの前記ランドといずれか1つの前記電極とを電気的に接続する、金の含有量が30重量%を超える導電部と、
前記配線基板と前記半導体チップとの間に設けられた樹脂部と、
を有する。本発明によれば、樹脂部によって導電部の破断を防止することができるため、信頼性の高い半導体装置を製造することができる。
Claims (4)
- 配線基板と半導体チップとの間に樹脂を設ける工程と、
前記配線基板に設けられた配線パターンのランドと前記半導体チップの電極との間に配置されたはんだに、前記ランドにメッキされた金を拡散させて、前記ランドと前記電極とを電気的に接続する導電部を、金の含有量が30重量%を超えるように形成する工程と、
前記樹脂を硬化させる工程と、
を含む半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記樹脂を硬化させる工程を、前記導電部を形成する工程よりも先又は同時に行う半導体装置の製造方法。 - 請求項1又は請求項2記載の半導体装置の製造方法において、
前記導電部を形成する工程を、フラックスを利用しないで行う半導体装置の製造方法。 - 複数のランドを含む配線パターンが設けられた配線基板と、
複数の電極を有し、前記電極が前記配線パターンと対向するように前記配線基板に搭載されてなる半導体チップと、
それぞれの前記ランドといずれか1つの前記電極とを電気的に接続する、金の含有量が30重量%を超える導電部と、
前記配線基板と前記半導体チップとの間に設けられた樹脂部と、
を有する半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004009025A JP2005203598A (ja) | 2004-01-16 | 2004-01-16 | 半導体装置及びその製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004009025A JP2005203598A (ja) | 2004-01-16 | 2004-01-16 | 半導体装置及びその製造方法 |
Publications (1)
Publication Number | Publication Date |
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JP2005203598A true JP2005203598A (ja) | 2005-07-28 |
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JP2004009025A Withdrawn JP2005203598A (ja) | 2004-01-16 | 2004-01-16 | 半導体装置及びその製造方法 |
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JP (1) | JP2005203598A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7566977B2 (en) | 2005-06-09 | 2009-07-28 | Seiko Epson Corporation | Semiconductor device and method for manufacturing the same |
-
2004
- 2004-01-16 JP JP2004009025A patent/JP2005203598A/ja not_active Withdrawn
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7566977B2 (en) | 2005-06-09 | 2009-07-28 | Seiko Epson Corporation | Semiconductor device and method for manufacturing the same |
US7811856B2 (en) | 2005-06-09 | 2010-10-12 | Seiko Epson Corporation | Semiconductor device and method for manufacturing the same |
US8102055B2 (en) | 2005-06-09 | 2012-01-24 | Seiko Epson Corporation | Semiconductor device |
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