JP2005203509A - Multilayer wiring board manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer wiring board manufacturing method whereby fine pattern formation is enabled and problems are solved concerning a decrease in value and the delamination of the formed wiring pattern. <P>SOLUTION: The method comprises a step for forming a bump by etching copper foil in a cladding material wherein copper foil and an etching barrier layer are laminated, a step for laminating the cladding material on the wiring board with an insulating layer between for the bump end to contact with the wiring board, a step for forming a plated resist layer of a specified pattern on the etching barrier layer of the laminated cladding material, a step for plating the pattern on the surface with the plated resist layer formed thereon, a step for removing the plated resist layer, and a step for removing the exposed etching barrier layer. A semi-additive method may be used wherein the wiring board is replaced by a board having an etching barrier layer also on the rear surface for the etching barrier layers on both surfaces to serve as seed metal layers. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a multilayer wiring board in which interlayer connection is performed by bumps, and in particular, a novel method for manufacturing a multilayer wiring board using an etching barrier layer at the time of bump formation as a seed metal at the time of pattern plating. About.

  In order to manufacture a so-called build-up multilayer wiring board, it is necessary to sequentially laminate an insulating layer and a conductor layer, pattern each conductor layer into a predetermined wiring pattern, and achieve interlayer connection between the conductor layers. The formation of fine patterns and the realization of efficient interlayer connection are important technologies.

Conventionally, as a manufacturing method of a build-up multilayer wiring board, a method using a so-called semi-additive method or a method of forming a bump on a copper film and embedding it in an insulating film (for example, Patent Document 1 and Patent Document 2) Etc.) are known.
JP 2003-129259 A JP 2002-43699 A

  The former method is shown in FIG. In the method using the semi-additive method, first, as shown in FIG. 3A, an insulating layer 102 is formed on a wiring substrate 101, and holes are formed by laser at a portion where interlayer connection is performed. The via hole 103 is formed as shown in FIG. Next, as shown in FIG. 3C, a seed metal layer 104 is formed on the insulating layer 102. The seed metal layer 104 is made of Cu, for example, and is formed by catalyst (Pd) formation and chemical plating.

  Next, as shown in FIG. 3D, a plating resist layer 105 is formed on the seed metal layer 104. The plating resist layer 105 is formed as a reverse pattern of a desired wiring pattern. After the formation of the plating resist layer 105, electrolytic plating is performed using the seed metal layer 104 to form an electrolytic plating layer 106 as shown in FIG. Thereafter, when the plating resist layer 105 is peeled off, the pattern plating 107 and the via fill plating 108 remain as shown in FIG. After the pattern plating 107 and via fill plating 108 are formed, the exposed seed metal layer 104 is removed as shown in FIG. At this time, Pd 109 used when forming the seed metal layer 104 remains, so Pd is removed as shown in FIG.

  On the other hand, in the latter method, bumps and wiring patterns are formed by etching a copper film. The latter method is shown in FIG.

  In the process shown in FIG. 4, first, as shown in FIG. 4A, a clad material 110 in which a copper film 111, an etching barrier layer 112 made of Ni or the like, and a copper film 113 as a support are laminated, and wiring A substrate 114 is prepared. Then, as shown in FIG. 4B, the copper film 111 is alkali etched to form bumps 115. At this time, the etching barrier layer 112 serves as an etching stopper, and the bump 115 is maintained in a state supported by the etching barrier layer 112 and the copper film 113. After the bump 115 is formed, the etching barrier layer 112 is removed by etching as shown in FIG. 4C, and the bump 115 is embedded in the insulating layer 116 and molded as shown in FIG. 4D.

  Next, as shown in FIG. 4E, an etching resist 117 is formed on the copper film 113, and the copper film 113 is pattern-etched using this as a mask to form a copper pattern 118 shown in FIG. 4F. To do. Finally, the etching resist 117 is stripped and removed. The formed copper pattern 118 becomes a wiring pattern.

  However, each of the above-described methods has advantages and disadvantages, and a problem to be solved remains. For example, the semi-additive method is advantageous in terms of fine pattern formation, but has the following problems. First, in the case of the semi-additive method, it is necessary to remove the seed metal layer 104 after the pattern plating 107 is formed. However, since both the pattern plating 107 and the seed metal layer 104 are Cu, the seed metal layer 104 Since only 104 cannot be removed, the pattern plating 107 is also etched, and the reduction in the size becomes a problem.

  Second, there is also a problem that it is difficult to completely remove the catalyst (Pd) used when the seed metal layer 104 is formed by chemical plating by etching. When Pd remains, for example, in electroless gold plating, gold plating is deposited using Pd as a nucleus, and a decrease in insulation reliability due to a short circuit becomes a problem. In order to remove Pd, so-called desmear treatment may be performed, but in this case, the insulating layer 102 is also dissolved, which causes a problem such as peeling of the fine line pattern.

  On the other hand, in the method of forming bumps on the copper film and embedding them in the insulating film, the bumps can be easily formed (interlayer connection), but the wiring pattern 118 is formed by etching the copper film 113. , There is a big problem that refinement (miniaturization) is difficult.

  The present invention has been proposed in order to solve these problems of the prior art, a fine wiring pattern can be formed, and a multilayer wiring board capable of solving problems such as loss of the formed wiring pattern and peeling. An object is to provide a manufacturing method.

  In order to achieve the above-described object, a method for manufacturing a multilayer wiring board according to the present invention includes, firstly, a step of forming a bump by etching the copper foil of a clad material in which a copper foil and an etching barrier layer are laminated. And a step of superimposing the clad material on the wiring substrate through an insulating layer so that a front end surface of the bump is in contact with the wiring substrate, and a plating resist having a predetermined pattern on the etching barrier layer of the superimposed clad material A step of forming a layer; a step of pattern plating on the surface on which the plating resist layer is formed; a step of removing the plating resist layer; and a step of removing the exposed etching barrier layer. .

  Secondly, a step of forming a bump by etching the copper foil of the clad material in which the copper foil and the first etching barrier layer are laminated, and a front end surface of the bump is in contact with the second etching barrier layer. And a step of superimposing the clad material on a second etching barrier layer supported by a support through an insulating layer, and a predetermined pattern on the first etching barrier layer of the clad material A step of forming a plating resist layer, a step of pattern plating the surface on which the plating resist layer is formed, a step of removing the plating resist layer, a step of removing the exposed first etching barrier layer, Peeling the support and forming a plating resist layer having a predetermined pattern on the second etching barrier layer; and forming the plating resist layer. A step of performing a pattern plating surface was characterized by having a step of removing the plating resist layer, and removing the second etch barrier layer exposed.

  In the manufacturing method of the present invention having the above configuration, the bumps are formed by etching the copper foil and the interlayer connection is achieved by embedding the bumps in the insulating layer. Therefore, the interlayer connection is easy. In addition, since the etching barrier layer is used as a seed metal layer, chemical plating is unnecessary, and it is not necessary to remove the catalyst (Pd). Furthermore, since the etching barrier layer functioning as a seed metal layer is, for example, Ni and has etching selectivity with respect to the wiring pattern made of Cu, the wiring pattern is etched when the etching barrier layer (seed metal layer) is removed by etching. There is nothing to do. Furthermore, since the wiring pattern is basically formed by a semi-additive method, a fine pattern is formed.

  According to the method for manufacturing a multilayer wiring board of the present invention, interlayer connection can be easily performed by forming bumps, and a fine pattern can be formed. Furthermore, in the present invention, since the etching barrier layer is used as the seed metal layer, problems such as loss of the formed wiring pattern and peeling can be solved.

  Hereinafter, a method of manufacturing a multilayer wiring board to which the present invention is applied will be described in detail with reference to the drawings.

(First embodiment)
This embodiment is an example applied in the case of multilayering by sequentially laminating insulating layers and conductor layers on a wiring board, patterning each conductor layer into a predetermined wiring pattern, and making interlayer connection between each conductor layer. is there.

  In this embodiment, first, as shown in FIG. 1A, a wiring board 1 and a clad material 2 on which a wiring pattern is formed in advance are prepared. The clad material 2 is formed by laminating, for example, a copper foil 3 for bump formation, an etching barrier layer 4 made of Ni or the like, and a copper foil 5 serving as a support. Here, the etching barrier layer 4 has etching selectivity with respect to the copper foil 3 and serves as an etching stopper when the copper foil 3 is etched. The copper foil 5 functions as a support for supporting bumps formed by etching the etching barrier layer 4 and the copper foil 3, and the material thereof is not necessarily copper.

  And as shown in FIG.1 (b), the said copper foil 3 is etched and the bump 6 is formed. The etching of the copper foil 3 is preferably performed by combining etching with an acidic etching solution and etching with an alkaline etching solution. That is, after forming a resist film (not shown) as a mask on the copper foil 3, an acidic etching solution (for example, cupric chloride) is sprayed. As a result, the copper foil 3 is etched, but the etching depth by the acidic etchant is made shallower than the thickness of the copper foil 3 and is within a range where the etching barrier layer 4 is not exposed. Next, after washing (rinsing), the remaining portion of the copper foil 3 is etched with an alkaline etching solution (for example, ammonium hydroxide). The alkaline etching solution hardly invades Ni constituting the etching barrier layer 4, and therefore the etching barrier layer 4 functions as a stopper for etching by the alkaline etching solution. At this time, the pH of the alkaline etching solution is preferably 8.0 or less. By setting the alkaline etching solution to the pH, the copper foil 3 can be etched relatively quickly without damaging the etching barrier layer 4.

  Next, as shown in FIG. 1C, the clad material 2 on which the bumps 6 are formed is superposed on the wiring substrate 1 via the insulating layer 7 and integrally molded. At this time, the bump 6 is brought into contact with a connection pattern (not shown) on the wiring substrate 1 to achieve electrical conduction. Therefore, an anisotropic conductive adhesive film or the like may be interposed between the bump 6 and the wiring board 1.

  After the clad material 2 and the wiring substrate 1 are integrated through the insulating layer 7 as described above, the copper foil 5 used as a support is peeled and removed as shown in FIG. The copper foil 5 may be peeled off mechanically or may be removed by etching. When removing the copper foil 5 by etching, an alkaline etching solution is used as the etching solution. If the copper foil 5 is etched with an alkaline etchant, the etching barrier layer 4 is not attacked and the etching barrier layer 4 remains on the insulating layer 7.

  Subsequently, a wiring pattern is formed by a so-called semi-additive method using the etching barrier layer 4 as a seed metal layer.

  In order to form a wiring pattern, a plating resist 8 is formed on the etching barrier layer 4 as shown in FIG. The plating resist 8 is formed as a reverse pattern of a desired wiring pattern. After the plating resist 8 is formed, electrolytic plating (pattern plating) is performed using the etching barrier layer 4 as a seed metal layer to form a plating pattern 9 as shown in FIG. In the electrolytic plating, plating is performed only on the portion where the etching barrier layer 4 is exposed, and no plating film is formed on the portion where the plating resist 8 is formed.

  Next, as shown in FIG. 1 (g), the plating resist 8 is peeled off, and as shown in FIG. 1 (h), the exposed etching barrier layer 4 is removed.

  In the above manufacturing method, since the plating pattern 9 to be a wiring pattern is formed according to the semi-additive method, a fine pattern can be formed. In addition, the interlayer connection is performed by the bumps 6. However, the formation of the bumps 6 by etching can be performed in a shorter time than, for example, via fill plating.

  Furthermore, in this embodiment, since the etching barrier layer 4 is used as a seed metal layer and a semi-additive method is performed, a fine pattern can be formed. Further, since chemical plating is not required and a catalyst (Pd) removal step is not required, peeling of the fine line pattern due to desmear treatment or the like can be eliminated. Further, since the etching barrier layer 4 has etching selectivity with respect to the plating pattern 9 formed of Cu, the plating pattern 9 is not etched when the etching barrier layer 4 is removed by etching. It is possible to prevent loss of eyes.

(Second Embodiment)
This embodiment is an example applied to the formation of a double-sided substrate that becomes a core of a multilayer wiring board, for example. The manufacturing process in this embodiment is shown in FIGS. 2A and 2B.

  Also in the present embodiment, first, as shown in FIG. 2A (a), a copper foil 12 for bump formation, a first etching barrier layer 13 made of Ni or the like, and a copper foil 14 to be a support are formed. A laminated clad material 11 is prepared, and the copper foil 12 is etched to form bumps 15 as shown in FIG. 2A (b).

  Next, as shown in FIG. 2A (c), the clad material 11 on which the bumps 15 are formed is laminated and integrated with the second clad material 17 via an insulating layer 16. Similar to the first etching barrier layer 13, the second cladding material 17 is composed of a second etching barrier layer 18 formed of Ni or the like and a copper foil 19 serving as a support. Note that the support is not necessarily made of the copper foil 19 and may be formed of any material as long as it can mechanically support the second etching barrier layer 18 having a small thickness. Alternatively, it is also possible to omit the copper foil 19 as a support and form the second etching barrier layer 18 only on the insulating layer 16 after laminating the insulating layer 16 on the clad material 11. In this case, the step of removing the support later can be omitted.

  Subsequently, on the first clad material 11 side, the first etching barrier layer 13 is used as a seed metal layer, and a plating pattern to be a wiring pattern is formed by a semi-additive method. That is, as shown in FIG. 2A (d), the copper foil 14 used as a support is peeled off and removed, and a plating resist 20 is formed on the first etching barrier layer 13 as shown in FIG. 2A (e). To do. Then, as shown in FIG. 2A (f), electrolytic plating (pattern plating) is performed using the etching barrier layer 13 as a seed metal layer to form a plating pattern 21, and then a plating resist 20 is formed as shown in FIG. 2A (g). To peel off. The process shown in FIG. 2A (f) is single-sided plating in which the copper foil 19 is covered with a resist or the like to form a plating layer only on the first etching barrier layer 13 side, but double-sided plating can also be used. When this process is a double-sided plating, a plating layer is also formed on the copper foil 19 and the thickness increases. Further, as shown in FIG. 2A (h), the exposed etching barrier layer 13 is peeled and removed.

  Next, on the second clad material 17 side, the second etching barrier layer 18 is used as a seed metal layer, and similarly, a plating pattern to be a wiring pattern is formed by a semi-additive method. That is, as shown in FIG. 2B (i), the copper foil 19 used as a support is peeled and removed, and a plating resist 22 is formed on the second etching barrier layer 18 as shown in FIG. 2B (j). To do. 2B (k), electrolytic plating (pattern plating) is performed using the etching barrier layer 18 as a seed metal layer to form a plating pattern 23, and then a plating resist 22 is formed as shown in FIG. 2B (l). To peel off. Further, as shown in FIG. 2B (m), the exposed etching barrier layer 18 is peeled and removed.

  Also in the manufacturing process of the present embodiment, the semi-additive method is performed by using the etching barrier layer 13 and the etching barrier layer 18 as a seed metal layer, as in the first embodiment. Formation is possible. Further, since chemical plating is not required and a catalyst (Pd) removal step is not required, peeling of the fine line pattern due to desmear treatment or the like can be eliminated. Further, since the etching barrier layer 13 and the etching barrier layer 18 have etching selectivity with respect to the plating patterns 21 and 23 formed of Cu, the plating patterns 21 and 23 are removed when the etching barrier layer 13.18 is removed by etching. It is possible to prevent the plating patterns 21 and 23 from being lost.

FIGS. 2A and 2B show a manufacturing process in the first embodiment, where FIG. 1A is a cross-sectional view showing a clad material and a wiring board, FIG. 1B is a cross-sectional view showing a bump forming step, and FIG. (D) is a sectional view showing a copper foil removing step, (e) is a sectional view showing a plating resist forming step, (f) is a sectional view showing a pattern plating step, (g) ) Is a sectional view showing a plating resist peeling step, and (h) is a sectional view showing an etching barrier layer peeling step. The manufacturing process in 2nd Embodiment is shown, (a) is sectional drawing which shows a clad material, (b) is sectional drawing which shows a bump formation process, (c) is 2nd cladding via an insulating layer (D) is a sectional view showing a copper foil removing step, (e) is a sectional view showing a plating resist forming step, (f) is a sectional view showing a pattern plating step, (g) ) Is a sectional view showing a plating resist peeling step, and (h) is a sectional view showing an etching barrier layer peeling step. The manufacturing process in 2nd Embodiment is shown, (i) is sectional drawing which shows a copper foil removal process, (j) is sectional drawing which shows a plating resist formation process, (k) is a cross section which shows a pattern plating process FIG. 1L is a cross-sectional view showing a plating resist peeling step, and FIG. The manufacturing process by a semi-additive method is shown, (a) is sectional drawing which shows an insulating layer formation process, (b) is sectional drawing which shows a laser drilling process, (c) is sectional drawing which shows a seed metal formation process , (D) is a sectional view showing a plating resist forming step, (e) is a sectional view showing a pattern plating step, (f) is a sectional view showing a resist peeling step, and (g) is a sectional view showing a seed metal layer removing step. FIG. 9H is a cross-sectional view showing the Pd removal step. 1 shows a manufacturing process for forming bumps and wiring patterns by etching a copper film, (a) is a sectional view showing a clad material and a wiring board, (b) is a sectional view showing a bump forming step, and (c) is a sectional view showing the bump forming process. (D) is a sectional view showing an insulating layer forming step, (e) is a sectional view showing an etching resist forming step, (f) is a sectional view showing a pattern etching step, (g) ) Is a cross-sectional view showing a resist stripping step.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Wiring board, 2 Clad material, 3, 5 Copper foil, 4 Etching barrier layer, 6 Bump, 7 Insulating layer, 8 Plating resist, 9 Plating pattern, 11 1st cladding material, 12, 14 Copper foil, 13 1st Etching barrier layer, 15 bump, 16 insulating layer, 17 second cladding material, 18 second etching barrier layer, 19 copper foil, 20, 22 plating resist, 21, 23 plating pattern

Claims (9)

Etching the copper foil of the clad material in which the copper foil and the etching barrier layer are laminated to form bumps;
Superimposing the clad material on the wiring board through an insulating layer so that the front end surface of the bump is in contact with the wiring board;
Forming a plating resist layer having a predetermined pattern on the etched barrier layer of the clad material;
Applying pattern plating to the surface on which the plating resist layer is formed;
Removing the plating resist layer;
Removing the exposed etching barrier layer;
A method for producing a multilayer wiring board, comprising:   2. The method of manufacturing a multilayer wiring board according to claim 1, wherein the bump is formed with the clad material supported by a support, and the support is removed after the clad material is overlaid on the wiring board. .   The method for manufacturing a multilayer wiring board according to claim 2, wherein the support is a copper foil.   2. The method for manufacturing a multilayer wiring board according to claim 1, wherein the etching barrier layer is a layer containing Ni. Etching the copper foil of the clad material in which the copper foil and the first etching barrier layer are laminated to form bumps;
Superimposing the clad material on the second etching barrier layer via an insulating layer such that the front end surface of the bump is in contact with the second etching barrier layer;
Forming a plating resist layer having a predetermined pattern on the first etching barrier layer of the laminated clad material;
Applying pattern plating to the surface on which the plating resist layer is formed;
Removing the plating resist layer;
Removing the exposed first etching barrier layer;
Forming a plating resist layer having a predetermined pattern on the second etching barrier layer;
Applying pattern plating to the surface on which the plating resist layer is formed;
Removing the plating resist layer;
Removing the exposed second etching barrier layer;
A method for producing a multilayer wiring board, comprising:   6. The multilayer wiring according to claim 5, wherein the bump is formed in a state where the clad material is supported by a support, and the support is removed after the clad material is overlaid on the second etching barrier layer. A method for manufacturing a substrate.   The second etching barrier layer is supported by a support, and the clad material is overlaid so that a front end surface of the bump is in contact with a surface opposite to a surface supported by the support. Item 6. A method for producing a multilayer wiring board according to Item 5.   8. The method for manufacturing a multilayer wiring board according to claim 6, wherein the support for the clad material and the support for the second etching barrier layer are copper foils. 6. The method of manufacturing a multilayer wiring board according to claim 5, wherein the first etching barrier layer and the second etching barrier layer are layers containing Ni.