JP2005202986A5 - - Google Patents

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Publication number
JP2005202986A5
JP2005202986A5 JP2005103792A JP2005103792A JP2005202986A5 JP 2005202986 A5 JP2005202986 A5 JP 2005202986A5 JP 2005103792 A JP2005103792 A JP 2005103792A JP 2005103792 A JP2005103792 A JP 2005103792A JP 2005202986 A5 JP2005202986 A5 JP 2005202986A5
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JP
Japan
Prior art keywords
cache
address signal
logic circuit
tag
entry
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2005103792A
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English (en)
Japanese (ja)
Other versions
JP3799050B2 (ja
JP2005202986A (ja
Filing date
Publication date
Priority claimed from US08/406,305 external-priority patent/US5617347A/en
Application filed filed Critical
Publication of JP2005202986A publication Critical patent/JP2005202986A/ja
Publication of JP2005202986A5 publication Critical patent/JP2005202986A5/ja
Application granted granted Critical
Publication of JP3799050B2 publication Critical patent/JP3799050B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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JP2005103792A 1995-03-17 2005-03-31 階層化された記憶項目とキャッシュタグを単一キャッシュアレイ構造に格納するキャッシュメモリ装置及び方法 Expired - Lifetime JP3799050B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/406,305 US5617347A (en) 1995-03-17 1995-03-17 Cache memory system and method thereof for storing a staged memory item and a cache tag within a single cache array structure

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP05802596A Division JP3709235B2 (ja) 1995-03-17 1996-03-14 階層化された記憶項目とキャッシュタグを単一キャッシュアレイ構造に格納するキャッシュメモリ装置及び方法

Publications (3)

Publication Number Publication Date
JP2005202986A JP2005202986A (ja) 2005-07-28
JP2005202986A5 true JP2005202986A5 (enExample) 2005-09-29
JP3799050B2 JP3799050B2 (ja) 2006-07-19

Family

ID=23607394

Family Applications (2)

Application Number Title Priority Date Filing Date
JP05802596A Expired - Lifetime JP3709235B2 (ja) 1995-03-17 1996-03-14 階層化された記憶項目とキャッシュタグを単一キャッシュアレイ構造に格納するキャッシュメモリ装置及び方法
JP2005103792A Expired - Lifetime JP3799050B2 (ja) 1995-03-17 2005-03-31 階層化された記憶項目とキャッシュタグを単一キャッシュアレイ構造に格納するキャッシュメモリ装置及び方法

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP05802596A Expired - Lifetime JP3709235B2 (ja) 1995-03-17 1996-03-14 階層化された記憶項目とキャッシュタグを単一キャッシュアレイ構造に格納するキャッシュメモリ装置及び方法

Country Status (2)

Country Link
US (1) US5617347A (enExample)
JP (2) JP3709235B2 (enExample)

Families Citing this family (26)

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Publication number Priority date Publication date Assignee Title
JP3116827B2 (ja) * 1996-07-16 2000-12-11 日本電気株式会社 キャッシュメモリ制御装置
US5916314A (en) * 1996-09-11 1999-06-29 Sequent Computer Systems, Inc. Method and apparatus for cache tag mirroring
US5890207A (en) * 1996-11-27 1999-03-30 Emc Corporation High performance integrated cached storage device
US5890219A (en) * 1996-11-27 1999-03-30 Emc Corporation Redundant writing of data to cached storage system
US5884055A (en) * 1996-11-27 1999-03-16 Emc Corporation Method and apparatus including a shared resource and multiple processors running a common control program accessing the shared resource
US5956746A (en) * 1997-08-13 1999-09-21 Intel Corporation Computer system having tag information in a processor and cache memory
JP3244053B2 (ja) * 1998-06-12 2002-01-07 日本電気株式会社 情報処理システム、装置、二次記憶装置及び記録媒体
RU2158023C1 (ru) * 1999-07-13 2000-10-20 Прогаров Олег Валерианович Способ хранения сети виртуальных нейронов и нейронный компьютер для его осуществления
US6446169B1 (en) 1999-08-31 2002-09-03 Micron Technology, Inc. SRAM with tag and data arrays for private external microprocessor bus
US6434665B1 (en) * 1999-10-01 2002-08-13 Stmicroelectronics, Inc. Cache memory store buffer
US7240277B2 (en) * 2003-09-26 2007-07-03 Texas Instruments Incorporated Memory error detection reporting
US20050144397A1 (en) * 2003-12-29 2005-06-30 Rudd Kevin W. Method and apparatus for enabling volatile shared data across caches in a coherent memory multiprocessor system to reduce coherency traffic
US7275202B2 (en) * 2004-04-07 2007-09-25 International Business Machines Corporation Method, system and program product for autonomous error recovery for memory devices
JP2006190402A (ja) * 2005-01-07 2006-07-20 Renesas Technology Corp 半導体装置
US20080052488A1 (en) * 2006-05-10 2008-02-28 International Business Machines Corporation Method for a Hash Table Lookup and Processor Cache
JP4484923B2 (ja) * 2007-12-27 2010-06-16 株式会社日立製作所 プロセッサ
WO2012061048A1 (en) 2010-11-04 2012-05-10 Rambus Inc. Techniques for storing data and tags in different memory arrays
US9215269B2 (en) 2012-08-23 2015-12-15 Amazon Technologies, Inc. Predictive caching for content
US9712854B2 (en) * 2012-09-06 2017-07-18 Alcatel Lucent Cost-aware cloud-based content delivery
US9588874B2 (en) * 2012-12-14 2017-03-07 Microsoft Technology Licensing, Llc Remote device automation using a device services bridge
US9465740B2 (en) * 2013-04-11 2016-10-11 Apple Inc. Coherence processing with pre-kill mechanism to avoid duplicated transaction identifiers
US9608890B1 (en) * 2013-12-23 2017-03-28 Kabam, Inc. System and method for forwarding external notifications of events in a virtual space from a user device to a presentation control device
US9544388B1 (en) * 2014-05-09 2017-01-10 Amazon Technologies, Inc. Client-side predictive caching for content
US9326046B1 (en) 2015-03-19 2016-04-26 Amazon Technologies, Inc. Uninterrupted playback of video streams using lower quality cached files
CN110737396B (zh) * 2018-07-20 2023-08-11 伊姆西Ip控股有限责任公司 数据复制的方法、设备和计算机存储介质
CN113597599A (zh) 2019-03-18 2021-11-02 拉姆伯斯公司 具有高速缓存模式的dram部件的系统应用

Family Cites Families (14)

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US5067078A (en) * 1989-04-17 1991-11-19 Motorola, Inc. Cache which provides status information
US5307477A (en) * 1989-12-01 1994-04-26 Mips Computer Systems, Inc. Two-level cache memory system
JP2938511B2 (ja) * 1990-03-30 1999-08-23 三菱電機株式会社 半導体記憶装置
JP2822588B2 (ja) * 1990-04-30 1998-11-11 日本電気株式会社 キャッシュメモリ装置
CA2043493C (en) * 1990-10-05 1997-04-01 Ricky C. Hetherington Hierarchical integrated circuit cache memory
US5210845A (en) * 1990-11-28 1993-05-11 Intel Corporation Controller for two-way set associative cache
JP2646854B2 (ja) * 1990-12-18 1997-08-27 三菱電機株式会社 マイクロプロセッサ
US5339399A (en) * 1991-04-12 1994-08-16 Intel Corporation Cache controller that alternately selects for presentation to a tag RAM a current address latch and a next address latch which hold addresses captured on an input bus
US5293603A (en) * 1991-06-04 1994-03-08 Intel Corporation Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path
US5228134A (en) * 1991-06-04 1993-07-13 Intel Corporation Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus
US5353424A (en) * 1991-11-19 1994-10-04 Digital Equipment Corporation Fast tag compare and bank select in set associative cache
US5345576A (en) * 1991-12-31 1994-09-06 Intel Corporation Microprocessor simultaneously issues an access to an external cache over an external cache bus and to an internal cache, cancels the external cache access on an internal cache hit, and reissues the access over a main memory bus on an external cache miss
US5471415A (en) * 1993-06-30 1995-11-28 Sgs-Thomson Microelectronics, Inc. Cache tag memory
US5499204A (en) * 1994-07-05 1996-03-12 Motorola, Inc. Memory cache with interlaced data and method of operation

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