JP2007115390A5 - - Google Patents

Download PDF

Info

Publication number
JP2007115390A5
JP2007115390A5 JP2006268644A JP2006268644A JP2007115390A5 JP 2007115390 A5 JP2007115390 A5 JP 2007115390A5 JP 2006268644 A JP2006268644 A JP 2006268644A JP 2006268644 A JP2006268644 A JP 2006268644A JP 2007115390 A5 JP2007115390 A5 JP 2007115390A5
Authority
JP
Japan
Prior art keywords
memory
data
error correction
correction code
bank
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006268644A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007115390A (ja
Filing date
Publication date
Application filed filed Critical
Publication of JP2007115390A publication Critical patent/JP2007115390A/ja
Publication of JP2007115390A5 publication Critical patent/JP2007115390A5/ja
Pending legal-status Critical Current

Links

JP2006268644A 2005-09-30 2006-09-29 メモリ機器、データを転送する方法、およびデータを格納する方法 Pending JP2007115390A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US72272205P 2005-09-30 2005-09-30

Publications (2)

Publication Number Publication Date
JP2007115390A JP2007115390A (ja) 2007-05-10
JP2007115390A5 true JP2007115390A5 (enExample) 2009-11-12

Family

ID=37432280

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006268644A Pending JP2007115390A (ja) 2005-09-30 2006-09-29 メモリ機器、データを転送する方法、およびデータを格納する方法

Country Status (3)

Country Link
US (1) US7676730B2 (enExample)
EP (1) EP1777624A3 (enExample)
JP (1) JP2007115390A (enExample)

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7734985B2 (en) * 2006-02-27 2010-06-08 Intel Corporation Systems, methods, and apparatuses for using the same memory type to support an error check mode and a non-error check mode
US7904789B1 (en) * 2006-03-31 2011-03-08 Guillermo Rozas Techniques for detecting and correcting errors in a memory device
US7280398B1 (en) * 2006-08-31 2007-10-09 Micron Technology, Inc. System and memory for sequential multi-plane page memory operations
US7590899B2 (en) * 2006-09-15 2009-09-15 International Business Machines Corporation Processor memory array having memory macros for relocatable store protect keys
US8386676B2 (en) * 2007-06-05 2013-02-26 Intel Corporation Systems, methods, and apparatuses for transmitting data mask bits to a memory device
JP2009199266A (ja) * 2008-02-20 2009-09-03 Hitachi Ltd データ転送制御装置、データ整合性判定方法及び記憶制御装置
US8161356B2 (en) * 2008-03-28 2012-04-17 Intel Corporation Systems, methods, and apparatuses to save memory self-refresh power
US8949684B1 (en) * 2008-09-02 2015-02-03 Apple Inc. Segmented data storage
CN102045478B (zh) * 2009-10-23 2013-05-01 精工爱普生株式会社 图像读取装置、校正处理方法及用该装置的图像处理方法
EP2502234B1 (en) 2009-11-20 2019-01-09 Rambus Inc. Bit-replacement technique for dram error correction
US8484536B1 (en) * 2010-03-26 2013-07-09 Google Inc. Techniques for data storage, access, and maintenance
US8719675B1 (en) 2010-06-16 2014-05-06 Google Inc. Orthogonal coding for data storage, access, and maintenance
US8612676B2 (en) 2010-12-22 2013-12-17 Intel Corporation Two-level system main memory
US8644104B2 (en) 2011-01-14 2014-02-04 Rambus Inc. Memory system components that support error detection and correction
US8694857B2 (en) * 2011-04-13 2014-04-08 Inphi Corporation Systems and methods for error detection and correction in a memory module which includes a memory buffer
US8621317B1 (en) 2011-07-25 2013-12-31 Google Inc. Modified orthogonal coding techniques for storing data
US8615698B1 (en) 2011-09-28 2013-12-24 Google Inc. Skewed orthogonal coding techniques
US9342453B2 (en) 2011-09-30 2016-05-17 Intel Corporation Memory channel that supports near memory and far memory access
US9189329B1 (en) * 2011-10-13 2015-11-17 Marvell International Ltd. Generating error correcting code (ECC) data using an ECC corresponding to an identified ECC protection level
US8959417B2 (en) 2011-11-23 2015-02-17 Marvell World Trade Ltd. Providing low-latency error correcting code capability for memory
US9753858B2 (en) 2011-11-30 2017-09-05 Advanced Micro Devices, Inc. DRAM cache with tags and data jointly stored in physical rows
US8856619B1 (en) 2012-03-09 2014-10-07 Google Inc. Storing data across groups of storage nodes
US9391637B2 (en) 2012-03-30 2016-07-12 Intel Corporation Error correcting code scheme utilizing reserved space
US8694862B2 (en) * 2012-04-20 2014-04-08 Arm Limited Data processing apparatus using implicit data storage data storage and method of implicit data storage
US8949698B2 (en) * 2012-09-27 2015-02-03 Intel Corporation Method, apparatus and system for handling data faults
US8984368B2 (en) * 2012-10-11 2015-03-17 Advanced Micro Devices, Inc. High reliability memory controller
WO2014074390A1 (en) 2012-11-06 2014-05-15 Rambus Inc. Memory repair using external tags
WO2015047334A1 (en) 2013-09-27 2015-04-02 Intel Corporation Error correction in non_volatile memory
JP6318769B2 (ja) 2014-03-28 2018-05-09 富士通株式会社 ストレージ制御装置、制御プログラム、および制御方法
US10528423B2 (en) 2015-12-01 2020-01-07 Nvidia Corporation Memory management systems and methods
KR102766654B1 (ko) * 2016-11-16 2025-02-12 에스케이하이닉스 주식회사 반도체장치 및 반도체시스템
US10606696B2 (en) 2017-12-04 2020-03-31 International Business Machines Corporation Internally-generated data storage in spare memory locations
US20190243566A1 (en) * 2018-02-05 2019-08-08 Infineon Technologies Ag Memory controller, memory system, and method of using a memory device
KR102557993B1 (ko) * 2018-10-02 2023-07-20 삼성전자주식회사 메모리 이용 효율을 향상한 보안 처리기를 포함하는 시스템 온 칩, 메모리 시스템 및 시스템 온 칩의 동작방법
US11119909B2 (en) * 2018-12-11 2021-09-14 Texas Instmments Incorporated Method and system for in-line ECC protection
US20200097362A1 (en) 2019-11-29 2020-03-26 Intel Corporation Methods and apparatus for reducing microbumps for inter-die double-data rate (ddr) transfer
US11144383B2 (en) * 2020-03-10 2021-10-12 Sap Se Platform for automated administration and monitoring of in-memory systems
CN114756403B (zh) * 2022-04-25 2023-03-14 电子科技大学 一种基于网络编码的ram利用率提升方法
US12216521B2 (en) * 2022-08-12 2025-02-04 Micron Technology, Inc. Common rain buffer for multiple cursors
US12504876B2 (en) * 2023-05-19 2025-12-23 Qualcomm Incorporated Flexible metadata regions for a memory device

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4955024A (en) * 1987-09-14 1990-09-04 Visual Information Technologies, Inc. High speed image processing computer with error correction and logging
US5052001A (en) * 1989-11-22 1991-09-24 Unisys Corporation Multiple memory bank parity checking system
US5117428A (en) * 1989-11-22 1992-05-26 Unisys Corporation System for memory data integrity
US5088092A (en) * 1989-11-22 1992-02-11 Unisys Corporation Width-expansible memory integrity structure
US6070262A (en) * 1997-04-04 2000-05-30 International Business Machines Corporation Reconfigurable I/O DRAM
JPH1198462A (ja) * 1997-09-19 1999-04-09 Hitachi Ltd データ再生装置
JP3184129B2 (ja) 1997-09-29 2001-07-09 甲府日本電気株式会社 記憶装置
JP3809719B2 (ja) * 1998-01-05 2006-08-16 ソニー株式会社 ディジタルビデオ信号処理装置および方法、ディジタルビデオ信号再生装置、復号装置および方法、ならびに、再生装置および方法
US6353910B1 (en) 1999-04-09 2002-03-05 International Business Machines Corporation Method and apparatus for implementing error correction coding (ECC) in a dynamic random access memory utilizing vertical ECC storage
US6279072B1 (en) * 1999-07-22 2001-08-21 Micron Technology, Inc. Reconfigurable memory with selectable error correction storage
US6854084B2 (en) * 2000-07-14 2005-02-08 Sun Microsystems, Inc. Partitioned random access memory
US6718444B1 (en) * 2001-12-20 2004-04-06 Advanced Micro Devices, Inc. Read-modify-write for partial writes in a memory controller
US7117421B1 (en) * 2002-05-31 2006-10-03 Nvidia Corporation Transparent error correction code memory system and method
US7043679B1 (en) * 2002-06-27 2006-05-09 Advanced Micro Devices, Inc. Piggybacking of ECC corrections behind loads
KR100481820B1 (ko) * 2002-09-26 2005-04-11 (주)실리콘세븐 패러티로서 비유효한 출력 데이터를 보정하는 에스램 호한메모리와 그 구동방법
KR100482380B1 (ko) * 2002-11-11 2005-04-14 (주)실리콘세븐 메모리 뱅크별 기입 동작의 수행이 가능한 에스램 호환 메모리 및 그 구동방법
US20040128464A1 (en) * 2002-12-30 2004-07-01 Lee Micheil J. Memory reclamation
US20040128465A1 (en) * 2002-12-30 2004-07-01 Lee Micheil J. Configurable memory bus width
US7447950B2 (en) * 2003-05-20 2008-11-04 Nec Electronics Corporation Memory device and memory error correction method

Similar Documents

Publication Publication Date Title
JP2007115390A5 (enExample)
US7676730B2 (en) Method and apparatus for implementing error correction coding in a random access memory
JP5675954B2 (ja) メタデータタグを介した不規則なパリティ分布の検出
US8719662B2 (en) Memory device with error detection
JP5516924B2 (ja) ストライプに基づく不揮発性多値メモリ操作
CN104051024B (zh) 用于内建错误更正的储存装置及其操作方法
US9223648B2 (en) Memory storage device, memory controller thereof, and method for processing data thereof
US20060112321A1 (en) Transparent error correcting memory that supports partial-word write
US9817712B2 (en) Storage control apparatus, storage apparatus, information processing system, and storage control method
US20080177938A1 (en) Hybrid hard disk drive, computer system including the same, and flash memory DMA circuit for hybrid HDD
US20090282305A1 (en) Storage system with data recovery function and method thereof
US20090327840A1 (en) Redundant data distribution in a flash storage device
TW201123196A (en) Bit error threshold and content addressable memory to address a remapped memory device
US20070283217A1 (en) Correction of data errors in a memory buffer
US10922234B2 (en) Method and system for online recovery of logical-to-physical mapping table affected by noise sources in a solid state drive
WO2004112048A3 (en) Error detection and correction method and apparatus in a magneto-resistive random access memory
JP2002312130A5 (enExample)
TW200921360A (en) Data preserving method and data accessing method for non-volatile memory
KR20150038343A (ko) 솔리드 스테이트 저장 장치를 위한 배드 블록 보상
US9754682B2 (en) Implementing enhanced performance with read before write to phase change memory
US20230238049A1 (en) Address mapping for improved memory reliability
US7966518B2 (en) Method for repairing a neighborhood of rows in a memory array using a patch table
TW200929237A (en) Memory architecture and configuration method thereof
US8924814B2 (en) Write management using partial parity codes
KR100972807B1 (ko) 에러 정정 코드 생성 방법 및 메모리 관리 장치