JP2005202254A - Display device - Google Patents

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JP2005202254A
JP2005202254A JP2004009951A JP2004009951A JP2005202254A JP 2005202254 A JP2005202254 A JP 2005202254A JP 2004009951 A JP2004009951 A JP 2004009951A JP 2004009951 A JP2004009951 A JP 2004009951A JP 2005202254 A JP2005202254 A JP 2005202254A
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wiring
storage capacitor
active element
display device
pixel
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JP4581408B2 (en
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Yukito Iida
幸人 飯田
Kazuo Nakamura
和夫 中村
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Sony Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To suppress the fluctuation in holding potential due to capacitive coupling in a light emitting display device of an active matrix type. <P>SOLUTION: In the display device, a pixel 3 includes a light emitting element, a holding capacitor 7, an active element 8 for sampling, and an active element 9 for driving. The active element 8 for sampling, when selected by the scanning wiring 1, operates to sample a vide signal from signal wiring 2 and holds the signal in the holding capacitor 7. The active element 9 for driving drives the light emitting element according to the video signal held in the holding capacitor 7. The holding capacitor 7 has a laminated structure holding a dielectric film between an upper electrode 7T and a lower electrode 7B and is disposed below the signal wiring 2 so as to be superposed thereon. The lower electrode 7B is connected to the active element 8 and the upper electrode 7T is connected to the power source supply wiring 4. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は表示装置に関する。詳しくは、有機ＥＬ素子によって代表される発光素子を画素とした、アクティブマトリクス型の自発光表示装置に関する。更に詳しくは、発光素子とともに各画素に形成される信号保持用の容量素子の構造に関する。   The present invention relates to a display device. Specifically, the present invention relates to an active matrix self-luminous display device using light-emitting elements typified by organic EL elements as pixels. More specifically, the present invention relates to the structure of a signal holding capacitor formed in each pixel together with a light emitting element.

アクティブマトリクス型の自発光表示装置は、現在有機ＥＬ素子が有望であり、盛んに開発が進められている。有機ＥＬ素子は有機薄膜に電界を掛けると発光する現象を利用したものである。有機ＥＬ素子は、印加電圧が１０Ｖ以下で発光する為、低電圧駆動・低消費電力である。又、有機ＥＬ素子は自発光素子である為、バックライトなどの照明部品を必要とせず、軽量化及び薄型化が可能である。更に、有機ＥＬ素子の応答速度は数μｓ程度と非常に高速であるので、動画表示時の残像が発生しない。   Active matrix type self-luminous display devices are currently promising organic EL elements, and are actively being developed. An organic EL element utilizes a phenomenon in which light is emitted when an electric field is applied to an organic thin film. Since the organic EL element emits light when the applied voltage is 10 V or less, it has low voltage driving and low power consumption. In addition, since the organic EL element is a self-luminous element, it does not require an illumination component such as a backlight, and can be reduced in weight and thickness. Furthermore, since the response speed of the organic EL element is as high as several μs, an afterimage at the time of displaying a moving image does not occur.

有機ＥＬ素子を用いた平面自発光表示装置の中でも、取り分け画素回路を構成する能動素子として薄膜トランジスタを用いたアクティブマトリクス型平面自発光表示装置の開発が盛んであり、以下の特許文献１に記載されている。
特開平１４−１５６９２３号公報 Among the flat self-luminous display devices using organic EL elements, active matrix flat self-luminous display devices using thin film transistors as active elements constituting pixel circuits are actively developed, and are described in Patent Document 1 below. ing.
Japanese Patent Laid-Open No. 14-156923

図１０は従来の表示装置の一例を示す模式的な回路図である。図示する様に、従来の表示装置は、行状の走査配線１と、列状の信号配線２と、各走査配線１及び信号配線２が交差する部分に配された画素３と、各画素３に電源を供給する電源供給配線４，５とを含む。画素３は、発光素子６と保持容量７とサンプリング用の薄膜トランジスタ８と駆動用の薄膜トランジスタ９を含む。サンプリング用トランジスタ８は、走査配線１によって選択された時動作し、信号配線２から映像信号をサンプリングして保持容量７に保持する。駆動用トランジスタ９は、保持容量７に保持された映像信号に応じて発光素子６を駆動する。   FIG. 10 is a schematic circuit diagram showing an example of a conventional display device. As shown in the figure, the conventional display device includes a row-shaped scanning line 1, a column-shaped signal line 2, a pixel 3 disposed at a portion where each scanning line 1 and the signal line 2 intersect, and each pixel 3. Power supply lines 4 and 5 for supplying power. The pixel 3 includes a light emitting element 6, a storage capacitor 7, a thin film transistor 8 for sampling, and a thin film transistor 9 for driving. The sampling transistor 8 operates when selected by the scanning wiring 1, samples a video signal from the signal wiring 2, and holds it in the storage capacitor 7. The driving transistor 9 drives the light emitting element 6 in accordance with the video signal held in the holding capacitor 7.

図１１は、図１０に示した表示装置の動作説明に供するタイミングチャートである。走査配線が高電位に遷移することで、サンプリング用トランジスタはオン状態となり、信号配線から供給された映像信号電位を保持容量に充電する。すると駆動用トランジスタのゲート電位は上昇を開始し、ドレイン電流を流し始める。その為有機ＥＬ素子などからなるダイオード型発光素子のアノード電位は上昇し発光を開始する。そして走査配線が低電位に遷移すると、保持容量に映像信号電位が保持され、駆動用トランジスタのゲート電位は一定に維持される。これにより発光素子の発光輝度は次のフレームまで一定に維持される。   FIG. 11 is a timing chart for explaining the operation of the display device shown in FIG. When the scanning wiring transitions to a high potential, the sampling transistor is turned on, and the video signal potential supplied from the signal wiring is charged in the storage capacitor. Then, the gate potential of the driving transistor starts to rise, and the drain current starts to flow. Therefore, the anode potential of the diode type light emitting element composed of an organic EL element or the like rises and light emission starts. When the scanning wiring transitions to a low potential, the video signal potential is held in the storage capacitor, and the gate potential of the driving transistor is kept constant. Thereby, the light emission luminance of the light emitting element is kept constant until the next frame.

現在、図１０に示したアクティブマトリクス型平面自発光表示装置の高精細化が市場で大きく望まれている。画素数の増大に伴い、個々の画素サイズが細かくなる。しかしながら、画素サイズが狭ピッチとなった場合や回路素子が多くなった場合、信号配線のレイアウト配置が困難となるだけでなく、保持容量を十分に確保することができなくなる。又、保持容量上に映像信号配線を配置すると、映像信号配線と保持容量との間に形成される寄生容量カップリングの為、保持電位が変動し発光輝度が変化してしまう。この発光輝度の変動は表示画面上でいわゆる縦クロストークとして現われるという課題がある。   At present, there is a great demand in the market for higher definition of the active matrix flat self-luminous display device shown in FIG. As the number of pixels increases, individual pixel sizes become finer. However, when the pixel size becomes a narrow pitch or the number of circuit elements increases, not only the layout of the signal wiring becomes difficult, but also a sufficient storage capacity cannot be secured. Further, when the video signal wiring is arranged on the storage capacitor, the storage potential varies and the light emission luminance changes due to the parasitic capacitance coupling formed between the video signal wiring and the storage capacitor. There is a problem that the fluctuation of the light emission luminance appears as so-called vertical crosstalk on the display screen.

上述した従来の技術の課題に鑑み、本発明は容量カップリングに起因する保持電位の変動を抑制することを目的とする。係る目的を達成する為に以下の手段を講じた。即ち、行状の走査配線と、列状の信号配線と、各走査配線及び信号配線が交差する部分に配された画素と、各画素に電源を供給する電源供給配線とを含む表示装置であって、前記画素は、発光素子と保持容量とサンプリング用の能動素子と駆動用の能動素子を含む。前記サンプリング用の能動素子は、該走査配線によって選択されたとき動作し、該信号配線から映像信号をサンプリングして該保持容量に保持する。前記駆動用の能動素子は、該保持容量に保持された映像信号に応じて該発光素子を駆動する。前記保持容量は、誘電体膜を上部電極と下部電極とで挟んだ積層構造を有し、該信号配線と重なる様にその下方に配されているとともに、前記下部電極は該サンプリング用の能動素子に接続されている一方、前記上部電極は該電源供給配線に接続されていることを特徴とする。
好ましくは、前記能動素子は、ゲート電極の上にゲート絶縁膜を介して半導体薄膜を重ねた積層構造を有する薄膜トランジスタからなり、前記保持容量は、該上部電極が該半導体薄膜と同層で、該下部電極が該ゲート電極と同層で、該誘電体膜が該ゲート絶縁膜と同層の積層構造を有する。又好ましくは、前記発光素子は有機ＥＬ素子である。 In view of the above-described problems of the conventional technology, an object of the present invention is to suppress a change in holding potential caused by capacitive coupling. In order to achieve this purpose, the following measures were taken. In other words, the display device includes a row-shaped scanning wiring, a column-shaped signal wiring, a pixel arranged at a portion where each scanning wiring and the signal wiring intersect, and a power supply wiring for supplying power to each pixel. The pixel includes a light emitting element, a storage capacitor, an active element for sampling, and an active element for driving. The sampling active element operates when selected by the scanning wiring, samples a video signal from the signal wiring, and holds it in the storage capacitor. The active element for driving drives the light emitting element according to the video signal held in the holding capacitor. The storage capacitor has a laminated structure in which a dielectric film is sandwiched between an upper electrode and a lower electrode, and is arranged below the signal wiring so as to overlap the signal wiring, and the lower electrode is an active element for sampling While the upper electrode is connected to the power supply wiring.
Preferably, the active element is a thin film transistor having a stacked structure in which a semiconductor thin film is stacked on a gate electrode via a gate insulating film, and the storage capacitor includes the upper electrode in the same layer as the semiconductor thin film, The lower electrode is in the same layer as the gate electrode, and the dielectric film has a stacked structure in the same layer as the gate insulating film. Preferably, the light emitting element is an organic EL element.

本発明によれば、保持容量の上部電極を電源供給配線に接続することで、映像信号配線回りのノイズから保持容量を電気的に遮蔽している。映像信号配線と保持容量間で容量カップリングを引き起こしても、画質への影響は見られなくなる。これにより、映像信号配線に重ねてその下部に保持容量を形成できる為、十分な容量値を確保できるとともに、狭ピッチ又は多素子の画素回路のデバイス設計及びレイアウト設計の簡易化が図れる。   According to the present invention, the storage capacitor is electrically shielded from noise around the video signal wiring by connecting the upper electrode of the storage capacitor to the power supply wiring. Even if capacitive coupling is caused between the video signal wiring and the storage capacitor, the influence on the image quality is not seen. As a result, a storage capacitor can be formed below the video signal wiring, so that a sufficient capacitance value can be secured, and device design and layout design of a narrow-pitch or multi-element pixel circuit can be simplified.

以下図面を参照して本発明の実施の形態を詳細に説明する。図１は本発明に係るアクティブマトリクス型自発光表示装置の基本的な構成を示す回路図である。図示する様に、本表示装置は行状の走査配線１と、列状の信号配線２と、各走査配線１及び信号配線２が交差する部分に配された画素３と、各画素３に電源を供給する電源供給配線４，５とを含む。画素３は、有機ＥＬ素子によって代表される発光素子６と保持容量７とサンプリング用の能動素子と駆動用の能動素子を含む。サンプリング用の能動素子はサンプリング用トランジスタ８（Ｎ型の薄膜トランジスタＴＦＴ）からなり、走査配線１によって選択された時動作し、信号配線２から映像信号をサンプリングして保持容量７に保持する。駆動用の能動素子は駆動用トランジスタ９（Ｎ型の薄膜トランジスタＴＦＴ）からなり、保持容量７に保持された映像信号に応じて発光素子６を駆動する。保持容量７は、誘電体膜を上部電極７Ｔと下部電極７Ｂとで挟んだ積層構造を有する。図示しないが、この積層構造は信号配線２と重なる様にその下方に配されている。特徴事項として、下部電極７Ｂはサンプリング用トランジスタ８に接続されている一方、上部電極７Ｔは共通電源供給配線４に接続されている。映像信号配線２の下に保持容量７が配置されると、映像信号配線２と保持容量７の上部電極７Ｔとの間に積層された層間絶縁膜の為、寄生容量Ｃｐが形成される。ここで、保持容量７の上部電極７Ｔを共通の電源供給配線４と接続することで、信号配線２と保持容量７間で寄生容量Ｃｐに起因する容量カップリングを引き起こしても、画質への悪影響を防ぐことができる。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing a basic configuration of an active matrix self-luminous display device according to the present invention. As shown in the figure, this display device includes a row-shaped scanning wiring 1, a column-shaped signal wiring 2, a pixel 3 arranged at a portion where each scanning wiring 1 and the signal wiring 2 intersect, and power to each pixel 3. Power supply lines 4 and 5 to be supplied. The pixel 3 includes a light emitting element 6 represented by an organic EL element, a holding capacitor 7, an active element for sampling, and an active element for driving. The sampling active element includes a sampling transistor 8 (N-type thin film transistor TFT). The sampling active element operates when selected by the scanning wiring 1, samples a video signal from the signal wiring 2, and holds it in the holding capacitor 7. The driving active element is composed of a driving transistor 9 (N-type thin film transistor TFT), and drives the light emitting element 6 in accordance with the video signal held in the holding capacitor 7. The storage capacitor 7 has a laminated structure in which a dielectric film is sandwiched between the upper electrode 7T and the lower electrode 7B. Although not shown, this laminated structure is arranged below the signal wiring 2 so as to overlap. As a feature, the lower electrode 7B is connected to the sampling transistor 8, while the upper electrode 7T is connected to the common power supply wiring 4. When the storage capacitor 7 is disposed under the video signal wiring 2, a parasitic capacitance Cp is formed due to the interlayer insulating film laminated between the video signal wiring 2 and the upper electrode 7 </ b> T of the storage capacitor 7. Here, if the upper electrode 7T of the storage capacitor 7 is connected to the common power supply wiring 4, even if the capacitive coupling caused by the parasitic capacitance Cp occurs between the signal wiring 2 and the storage capacitor 7, the image quality is adversely affected. Can be prevented.

走査配線１が高電位に遷移すると、サンプリング用トランジスタ８はオン状態となり、信号配線２から供給される映像信号を保持容量７に充電する。すると、駆動用トランジスタ９のゲート電位は上昇を開始し、ドレイン電流を流し始める。その為、発光素子６のアノード電位は上昇し発光を開始する。そして、走査配線１が低電位に遷移すると、保持容量７に映像信号がそのまま保持され、駆動用トランジスタ９のゲート電位は一定となり、発光輝度は次のフレームまで一定となる。   When the scanning line 1 transitions to a high potential, the sampling transistor 8 is turned on to charge the storage capacitor 7 with the video signal supplied from the signal line 2. Then, the gate potential of the driving transistor 9 starts to rise and starts to flow a drain current. Therefore, the anode potential of the light emitting element 6 rises and starts to emit light. When the scanning wiring 1 transitions to a low potential, the video signal is held as it is in the holding capacitor 7, the gate potential of the driving transistor 9 becomes constant, and the light emission luminance becomes constant until the next frame.

図２は、図１に示した画素の模式的な平面図である。画素３は、直交配列された走査配線１と映像信号配線２の交差部にサンプリング用トランジスタ８が配されている。サンプリング用トランジスタ８のゲートＧと走査配線１が接続され、ドレインＤと映像信号配線８が接続されている。サンプリング用トランジスタ８のソースＳには保持容量７の下部電極７Ｂとさらに駆動用トランジスタ９のゲートＧが接続される。駆動用トランジスタ９のドレインＤには電源供給配線５が接続され、ソースＳには発光素子のアノード６Ａが接続される。保持容量７の上部電極７Ｔと発光素子のカソード（図示せず）が共通電源供給配線４に接続される。本発明の特徴事項として、走査配線１と直交した映像信号配線２の下に保持容量７が配置されているとともに、保持容量７の上部電極７ＴがコンタクトＣＯＮを介して共通電源供給配線４に接続されている。   FIG. 2 is a schematic plan view of the pixel shown in FIG. In the pixel 3, a sampling transistor 8 is arranged at the intersection of the scanning wiring 1 and the video signal wiring 2 that are orthogonally arranged. The gate G of the sampling transistor 8 and the scanning wiring 1 are connected, and the drain D and the video signal wiring 8 are connected. The lower electrode 7B of the storage capacitor 7 and the gate G of the driving transistor 9 are connected to the source S of the sampling transistor 8. The power supply wiring 5 is connected to the drain D of the driving transistor 9, and the anode 6 A of the light emitting element is connected to the source S. The upper electrode 7T of the storage capacitor 7 and the cathode (not shown) of the light emitting element are connected to the common power supply wiring 4. As a feature of the present invention, the storage capacitor 7 is arranged under the video signal wiring 2 orthogonal to the scanning wiring 1 and the upper electrode 7T of the storage capacitor 7 is connected to the common power supply wiring 4 via the contact CON. Has been.

図３の（Ａ）は、サンプリング用薄膜トランジスタ８の断面構造を示す模式図である。図示する様に、サンプリング用トランジスタ８は、ゲート電極Ｇの上にゲート絶縁膜２１を介して半導体薄膜２２を重ねた積層構造を有する薄膜トランジスタからなる。具体的には、ガラスなどの絶縁基板２０に金属モリブデンなどからなるゲート電極Ｇがパタニングされており、その上をＳｉＯ２／ＳｉＮなどからなるゲート絶縁膜２１が被覆している。ゲート絶縁膜２１の上には多結晶シリコンなどからなる半導体薄膜２２が形成されている。係る構成を有する薄膜トランジスタは層間絶縁膜２３により被覆されている。トランジスタ８のドレインＤは層間絶縁膜２３に開口したコンタクトホールを介して信号配線２に接続している。ソースＳも層間絶縁膜２３に開口したコンタクトホールを介して他の配線に接続される。 FIG. 3A is a schematic diagram showing a cross-sectional structure of the sampling thin film transistor 8. As shown in the figure, the sampling transistor 8 is a thin film transistor having a stacked structure in which a semiconductor thin film 22 is stacked on a gate electrode G via a gate insulating film 21. Specifically, a gate electrode G made of metal molybdenum or the like is patterned on an insulating substrate 20 made of glass or the like, and a gate insulating film 21 made of SiO 2 / SiN or the like is coated thereon. A semiconductor thin film 22 made of polycrystalline silicon or the like is formed on the gate insulating film 21. The thin film transistor having such a configuration is covered with an interlayer insulating film 23. The drain D of the transistor 8 is connected to the signal wiring 2 through a contact hole opened in the interlayer insulating film 23. The source S is also connected to another wiring through a contact hole opened in the interlayer insulating film 23.

（Ｂ）は保持容量７の構造を表わしている。図示する様に、保持容量７は絶縁基板２０の上に形成されており、下から順に下部電極７Ｂ、誘電体膜７Ｍ、上部電極７Ｔを重ねた積層構造を有する。保持容量７は層間絶縁膜２３で覆われており、その上に信号配線２が形成されている。信号配線２は例えばＴｉ／Ａｌからなる。本実施例では、薄膜トランジスタ８と薄膜容量７は同時に形成可能である。すなわち保持容量７は、上部電極７Ｔが半導体薄膜２２と同層で、下部電極７Ｂがゲート電極Ｇと同層で、誘電体膜７Ｍがゲート絶縁膜２１と同層の積層構造を有する。   (B) represents the structure of the storage capacitor 7. As shown in the figure, the storage capacitor 7 is formed on an insulating substrate 20 and has a laminated structure in which a lower electrode 7B, a dielectric film 7M, and an upper electrode 7T are stacked in order from the bottom. The storage capacitor 7 is covered with an interlayer insulating film 23, and the signal wiring 2 is formed thereon. The signal wiring 2 is made of, for example, Ti / Al. In this embodiment, the thin film transistor 8 and the thin film capacitor 7 can be formed simultaneously. That is, the storage capacitor 7 has a stacked structure in which the upper electrode 7T is the same layer as the semiconductor thin film 22, the lower electrode 7B is the same layer as the gate electrode G, and the dielectric film 7M is the same layer as the gate insulating film 21.

図４は、本発明に係る表示装置の全体構成を示すブロック図である。図示する様に、本表示装置は表示アレイ１２を構成するパネルと、周辺の駆動回路とで構成されている。周辺の駆動回路は垂直ドライバ１５と水平ドライバ１６を含む。表示アレイ１２は画素３をマトリクス状に配列したものである。前述した様に各画素３は、走査配線１と信号配線２の交差部に配され、発光素子６、保持容量７、サンプリング用トランジスタ８、駆動用トランジスタ９などを含んでいる。信号配線２と保持容量７の上部電極との間に寄生容量Ｃｐが形成されている。保持容量７の上部電極は共通の電源供給配線４に接続されている。垂直ドライバ１５は、パネルの表示アレイ１２に画像を表示する際の描画タイミングを指示する走査パルスを、各走査配線１に順次出力する。一方水平ドライバ１６はパネルの表示アレイ１２に画像を表示する際の描画データに基づく映像信号を、各信号配線２に供給している。   FIG. 4 is a block diagram showing the overall configuration of the display device according to the present invention. As shown in the figure, this display device is composed of a panel constituting the display array 12 and peripheral drive circuits. The peripheral driving circuit includes a vertical driver 15 and a horizontal driver 16. The display array 12 has pixels 3 arranged in a matrix. As described above, each pixel 3 is arranged at the intersection of the scanning wiring 1 and the signal wiring 2 and includes the light emitting element 6, the holding capacitor 7, the sampling transistor 8, the driving transistor 9, and the like. A parasitic capacitance Cp is formed between the signal line 2 and the upper electrode of the storage capacitor 7. The upper electrode of the storage capacitor 7 is connected to the common power supply wiring 4. The vertical driver 15 sequentially outputs a scanning pulse for instructing a drawing timing when an image is displayed on the display array 12 of the panel to each scanning wiring 1. On the other hand, the horizontal driver 16 supplies a video signal based on drawing data when displaying an image on the display array 12 of the panel to each signal wiring 2.

図５は、図４に示した表示装置の動作説明に供するタイミングチャートであり、１画素分に着目したものである。着目した画素において、サンプリング期間に所定の映像信号をサンプリングする。サンプリングされた映像信号は保持期間中保持される。保持期間では着目した画素以外の他の画素への映像信号が、映像信号配線に供給される。ここで保持期間に映像信号配線電位が低電位側や高電位側に遷移すると、前述した寄生容量Ｃｐを介して保持容量の保持電位（駆動用トランジスタのゲート電位）が減少または増加する。これを容量カップリングと呼ぶ。何ら対策を施さないと、この容量カップリングにより駆動用トランジスタのゲート電位が変動してしまう。これに対処する為本発明では保持容量の上部電極を共通電源供給配線に接続している。すなわち寄生容量Ｃｐが映像信号配線と共通電源供給配線との間に形成されている。この為容量カップリングにより保持電位が変動しても即座に変動前の保持電位に戻る。この為発光輝度は一定に保たれる。これにより、発光輝度に影響を与えることなく映像信号配線下に保持容量を配置できる為、十分な容量値を確保できるとともに、狭ピッチの有機ＥＬ画素や多素子の有機ＥＬ画素回路のデバイス設計及びレイアウト設計の簡易化が図れる。   FIG. 5 is a timing chart for explaining the operation of the display device shown in FIG. 4 and focuses on one pixel. In the pixel of interest, a predetermined video signal is sampled during the sampling period. The sampled video signal is held during the holding period. In the holding period, video signals to pixels other than the pixel of interest are supplied to the video signal wiring. Here, when the video signal wiring potential transitions to the low potential side or the high potential side during the retention period, the retention potential (gate potential of the driving transistor) of the retention capacitor decreases or increases via the parasitic capacitance Cp described above. This is called capacitive coupling. If no measures are taken, the gate potential of the driving transistor will fluctuate due to this capacitive coupling. In order to cope with this, in the present invention, the upper electrode of the storage capacitor is connected to the common power supply wiring. That is, the parasitic capacitance Cp is formed between the video signal wiring and the common power supply wiring. For this reason, even if the holding potential fluctuates due to capacitive coupling, it immediately returns to the holding potential before the fluctuation. For this reason, the light emission luminance is kept constant. As a result, a storage capacitor can be arranged under the video signal wiring without affecting the light emission luminance, so that a sufficient capacitance value can be secured, and device design of a narrow pitch organic EL pixel or a multi-element organic EL pixel circuit and Simplify layout design.

図６はアクティブマトリクス型平面自発光表示装置の参考例を示す画素回路図である。理解を容易にする為、図１に示した本発明に係る表示装置の画素回路と対応する部分には対応する参照番号を付してある。異なる点は、保持容量７の上部電極７Ｔが駆動用トランジスタ９のゲートに接続する一方、下部電極７Ｂが共通電源供給配線４に接続されていることである。この結果信号配線２の下方に保持容量７を配置すると、駆動用トランジスタ９のゲートに接続された上部電極７Ｔと信号配線２との間に寄生容量Ｃｐが発生することになる。   FIG. 6 is a pixel circuit diagram showing a reference example of an active matrix type flat self-luminous display device. For easy understanding, portions corresponding to the pixel circuits of the display device according to the present invention shown in FIG. 1 are denoted by corresponding reference numerals. The difference is that the upper electrode 7T of the storage capacitor 7 is connected to the gate of the driving transistor 9, while the lower electrode 7B is connected to the common power supply wiring 4. As a result, when the storage capacitor 7 is disposed below the signal wiring 2, a parasitic capacitance Cp is generated between the upper electrode 7 </ b> T connected to the gate of the driving transistor 9 and the signal wiring 2.

図７は、図６に示した画素回路に含まれる各素子のレイアウトを示した模式図である。理解を容易にする為、図２に示した本発明の画素のレイアウトと対応する部分には対応する参照番号を付してある。保持容量７が信号配線２の下部に重ねて配されている点は共通している。異なる点は、保持容量７の下部電極７ＢがコンタクトＣＯＮを介して共通電源供給配線４に接続されている一方、上部電極７Ｔがサンプリング用トランジスタ８のソースＳ及び駆動用トランジスタ９のゲートＧに接続されていることである。この結果、層間絶縁膜を介して、信号配線２と上部電極７Ｔとの間に寄生容量が発生し、且つこの寄生容量が直接駆動用トランジスタ９のゲートＧに接続されていることになる。   FIG. 7 is a schematic diagram showing a layout of each element included in the pixel circuit shown in FIG. In order to facilitate understanding, portions corresponding to the layout of the pixel of the present invention shown in FIG. The common point is that the storage capacitor 7 is arranged below the signal wiring 2. The difference is that the lower electrode 7B of the storage capacitor 7 is connected to the common power supply wiring 4 via the contact CON, while the upper electrode 7T is connected to the source S of the sampling transistor 8 and the gate G of the driving transistor 9. It has been done. As a result, a parasitic capacitance is generated between the signal wiring 2 and the upper electrode 7T via the interlayer insulating film, and this parasitic capacitance is directly connected to the gate G of the driving transistor 9.

図８は参考例に係る表示装置の全体構成を示すブロック図であり、中央の表示アレイ１２を構成するパネルと、周辺の垂直ドライバ１５及び水平ドライバ１６とで構成されている。基本的には、図４に示した本発明の構成と同様であり、対応する部分には対応する参照番号を付してある。異なる点は、表示アレイ１２に含まれる個々の画素３に形成される寄生容量Ｃｐが、信号配線２と駆動用トランジスタ９のゲートとの間に形成されることである。   FIG. 8 is a block diagram showing the overall configuration of a display device according to a reference example, which includes a panel constituting a central display array 12, peripheral vertical drivers 15, and horizontal drivers 16. Fundamentally, it is the same as that of the structure of this invention shown in FIG. 4, and the corresponding reference number is attached | subjected to the corresponding part. The difference is that a parasitic capacitance Cp formed in each pixel 3 included in the display array 12 is formed between the signal line 2 and the gate of the driving transistor 9.

図９は、図８に示した参考例に係る表示装置の動作説明に供するタイミングチャートである。ある特定の画素において、高電位の映像信号をサンプリングする。保持期間中には他の画素への映像信号が信号配線に供給される。図示する様に保持期間中に映像信号配線電位が低電位に遷移すると、寄生容量Ｃｐを介して保持容量の保持電位（駆動用トランジスタのゲート電位）が減少する。逆に保持期間中信号配線電位が高電位に遷移すると、同じく寄生容量Ｃｐを介して保持容量の保持電位が増大する。これを容量カップリングと呼ぶ。ここで保持容量の上部電極が共通電源供給配線に接続されていない場合には、係る保持電位の変動は映像信号配線が次の映像信号電位に切り換わるまで維持される。保持電位の変動は駆動用トランジスタのゲート電位の変動につながる。駆動用トランジスタのゲート電位の減少は発光素子に供給される駆動電流を減少させ、発光輝度を減少させる。逆に保持期間中更に高電位の映像信号が供給されると、容量カップリングにより保持電位が増加する。保持容量の増加は発光素子に供給される駆動電流を増加させ、発光輝度の増大を招く。これら容量カップリングによる発光輝度の変動は表示パネルに縦クロストークとして現われる。映像信号配線下に保持容量を配置しなければ容量カップリングを回避できるが、弊害として十分な保持容量を確保できない為保持電位のリークを引き起こす。パネルに表示する画像の絵柄によっては、保持期間中信号配線に常に低電位又は高電位の映像信号が印加される場合もある。この時には、寄生容量を介した容量カップリングにより駆動用トランジスタのゲート電位の変動が顕著となる為、クロストークが目立つ。   FIG. 9 is a timing chart for explaining the operation of the display device according to the reference example shown in FIG. A high potential video signal is sampled at a specific pixel. During the holding period, a video signal to other pixels is supplied to the signal wiring. As shown in the figure, when the video signal wiring potential transitions to a low potential during the holding period, the holding potential of the holding capacitor (the gate potential of the driving transistor) decreases via the parasitic capacitance Cp. On the other hand, when the signal wiring potential transitions to a high potential during the holding period, the holding potential of the holding capacitor similarly increases via the parasitic capacitance Cp. This is called capacitive coupling. Here, when the upper electrode of the storage capacitor is not connected to the common power supply wiring, the change in the storage potential is maintained until the video signal wiring is switched to the next video signal potential. The fluctuation of the holding potential leads to the fluctuation of the gate potential of the driving transistor. Decreasing the gate potential of the driving transistor decreases the driving current supplied to the light emitting element and decreases the light emission luminance. Conversely, when a video signal having a higher potential is supplied during the holding period, the holding potential increases due to capacitive coupling. The increase in the storage capacity increases the drive current supplied to the light emitting element, leading to an increase in light emission luminance. Variations in emission luminance due to these capacitive couplings appear as vertical crosstalk on the display panel. Capacitance coupling can be avoided if a storage capacitor is not disposed under the video signal wiring, but a sufficient storage capacitor cannot be secured as a detrimental effect, causing leakage of the storage potential. Depending on the pattern of the image displayed on the panel, a low-potential or high-potential video signal may always be applied to the signal wiring during the holding period. At this time, the variation in the gate potential of the driving transistor becomes significant due to the capacitive coupling via the parasitic capacitance, so that crosstalk is conspicuous.

本発明に係る表示装置の構成を示す画素回路図である。1 is a pixel circuit diagram illustrating a configuration of a display device according to the present invention. 本発明に係る表示装置の画素回路レイアウトを示す模式的な平面図である。It is a typical top view which shows the pixel circuit layout of the display apparatus which concerns on this invention. 本発明に係る表示装置の断面構造を示す模式図である。It is a schematic diagram which shows the cross-section of the display apparatus which concerns on this invention. 本発明に係る表示装置の全体構成を示すブロック図である。It is a block diagram which shows the whole structure of the display apparatus which concerns on this invention. 本発明に係る表示装置の動作説明に供するタイミングチャートである。3 is a timing chart for explaining the operation of the display device according to the present invention. 参考例に係る表示装置の画素構成を示す回路図である。It is a circuit diagram which shows the pixel structure of the display apparatus which concerns on a reference example. 参考例に係る表示装置の画素レイアウトを示す平面図である。It is a top view which shows the pixel layout of the display apparatus which concerns on a reference example. 参考例に係る表示装置の全体構成を示すブロック図である。It is a block diagram which shows the whole structure of the display apparatus which concerns on a reference example. 参考例に係る表示装置の動作説明に供するタイミングチャートである。It is a timing chart with which it uses for operation | movement description of the display apparatus which concerns on a reference example. 従来の表示装置の一例を示す画素回路図である。It is a pixel circuit diagram which shows an example of the conventional display apparatus. 従来の表示装置の動作説明に供するタイミングチャートである。It is a timing chart with which it uses for description of operation | movement of the conventional display apparatus.

符号の説明Explanation of symbols

１・・・走査配線、２・・・信号配線、３・・・画素、４・・・共通電源供給配線、５・・・電源供給配線、６・・・発光素子（ＥＬ）、７・・・保持容量、７Ｔ・・・上部電極、７Ｂ・・・下部電極、８・・・サンプリング用トランジスタ、９・・・駆動用トランジスタ DESCRIPTION OF SYMBOLS 1 ... Scanning wiring, 2 ... Signal wiring, 3 ... Pixel, 4 ... Common power supply wiring, 5 ... Power supply wiring, 6 ... Light emitting element (EL), 7 ...・ Retention capacity, 7T: upper electrode, 7B: lower electrode, 8: sampling transistor, 9: driving transistor

Claims (3)

行状の走査配線と、列状の信号配線と、各走査配線及び信号配線が交差する部分に配された画素と、各画素に電源を供給する電源供給配線とを含む表示装置であって、
前記画素は、発光素子と保持容量とサンプリング用の能動素子と駆動用の能動素子を含み、
前記サンプリング用の能動素子は、該走査配線によって選択されたとき動作し、該信号配線から映像信号をサンプリングして該保持容量に保持し、
前記駆動用の能動素子は、該保持容量に保持された映像信号に応じて該発光素子を駆動し、
前記保持容量は、誘電体膜を上部電極と下部電極とで挟んだ積層構造を有し、該信号配線と重なる様にその下方に配されているとともに、
前記下部電極は該サンプリング用の能動素子に接続されている一方、前記上部電極は該電源供給配線に接続されていることを特徴とする表示装置。 A display device including a row-shaped scanning wiring, a column-shaped signal wiring, a pixel arranged at a portion where each scanning wiring and the signal wiring intersect, and a power supply wiring for supplying power to each pixel,
The pixel includes a light emitting element, a storage capacitor, an active element for sampling, and an active element for driving,
The sampling active element operates when selected by the scanning wiring, samples a video signal from the signal wiring, and holds it in the storage capacitor,
The active element for driving drives the light emitting element according to the video signal held in the holding capacitor,
The storage capacitor has a laminated structure in which a dielectric film is sandwiched between an upper electrode and a lower electrode, and is arranged below the signal wiring so as to overlap,
The display device, wherein the lower electrode is connected to the sampling active element, and the upper electrode is connected to the power supply wiring. 前記能動素子は、ゲート電極の上にゲート絶縁膜を介して半導体薄膜を重ねた積層構造を有する薄膜トランジスタからなり、
前記保持容量は、該上部電極が該半導体薄膜と同層で、該下部電極が該ゲート電極と同層で、該誘電体膜が該ゲート絶縁膜と同層の積層構造を有することを特徴とする請求項１記載の表示装置。 The active element comprises a thin film transistor having a stacked structure in which a semiconductor thin film is stacked on a gate electrode via a gate insulating film,
The storage capacitor has a laminated structure in which the upper electrode is in the same layer as the semiconductor thin film, the lower electrode is in the same layer as the gate electrode, and the dielectric film is in the same layer as the gate insulating film. The display device according to claim 1. 前記発光素子は有機ＥＬ素子であることを特徴とする請求項１記載の表示装置。   The display device according to claim 1, wherein the light emitting element is an organic EL element.
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