JP2000284723A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the display device which makes an excellent display by suppressing variation in the hold voltage of an auxiliary capacitor. SOLUTION: A gate projection part 53 which has display pixels arrayed on an insulating substrate in areas surrounded with gate signal lines 51 and drain signal lines 52 and is arranged projecting from the gate signal lines 51 in the extension direction of the drain signal lines 52 and a shield film 18 which forms a capacitor with the gate projection part 53 and a capacity electrode 54 made of p-Si across a gate insulating film and is provided covering the capacity electrode 54 across an inter-layer insulating film are provided above the channel of an active layer made of p-Si to width less than the channel length of the channel without overlapping with a source and drain connection part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a display device which forms a capacitance with an auxiliary capacitance electrode line or a gate signal line and a semiconductor film.

[0002]

2. Description of the Related Art In recent years, as a display device, a liquid crystal display device (Thin Film Transistor: hereinafter referred to as "TFT") as a switching element for driving a display electrode in a display area.
y: Hereinafter, referred to as “LCD”. ) And electroluminescence (hereinafter, referred to as “EL”) display devices are also being researched and developed.

FIG. 7 is a plan view of one display pixel of the LCD, FIG. 8A is a cross-sectional view taken along the line AA in FIG. 7, and FIG. FIG. 4 shows a cross-sectional view along line -B.

As shown in FIG. 7, display pixels are formed in a region surrounded by a gate signal line 51 partially provided with a gate electrode 11 and a drain signal line 52 partially provided with a drain electrode 16. ing. A switching element T for supplying a signal to the display electrode 20 is provided near the intersection of both signal lines.
An FT is provided.

A part of the gate signal line 51 (hatched from upper left to lower right in the figure) is part of the gate signal line 5.
1 and a gate projection 53 projecting in the direction of a display pixel in the next stage.
Overlaps with the drain signal line 52 in the direction in which the drain signal line 52 extends.

The structure of the TFT and the LCD will be described with reference to FIG.

As shown in FIG. 8B, a gate signal line 51 made of a high melting point metal such as chromium (Cr) or molybdenum (Mo) is formed on an insulating substrate 10 made of quartz glass, non-alkali glass or the like. A gate electrode 11 forming a part is provided. The gate insulating film 1 is formed on the gate electrode 11.
2, and an active layer 13 made of a polycrystalline silicon (hereinafter referred to as “p-Si”) film is formed in order, and the active layer 13 has an intrinsic or substantially intrinsic channel above the gate electrode 11. A lightly doped region (LDD) formed by ion implantation using the stopper insulating film 14 as a mask on both sides of the channel 13c and the channel 13c.
Drain) region, and the source 13s and the drain 13d are made into a high concentration region by further ion implantation.
Is provided. As shown in FIG. 8A, charge is accumulated between a gate protrusion 53 protruding from the gate signal line 51 and a capacitor electrode 54 formed by extending the source 13s of the active layer 13. Thus, an auxiliary capacitance forming portion forming a capacitance is formed. The capacitance formed here is the liquid crystal 2
2 is an auxiliary capacitor provided to hold the voltage applied to the second capacitor. In order to secure the auxiliary capacitance and increase the area of the opening of the display pixel, the auxiliary capacitance forming portion is formed in a region overlapping with the drain signal line.

Then, as shown in FIG. 8B, an SiO ₂ film, a SiN film and an SiO ₂ film are stacked in this order on the entire surface of the gate insulating film 12, the active layer 13 and the stopper insulating film 14. An insulating film 15 is provided, and a shielding film 18 is provided thereon. Furthermore, an SiO ₂ film, a SiN film and a S
An interlayer insulating film 17 laminated in the order of the iO ₂ film is provided, and a contact hole provided at a position corresponding to the drain 13 d of the interlayer insulating film 15 and the interlayer insulating film 17 is filled with a metal such as Al to form a drain electrode 16. . At this time, as shown in FIG. 8A, the drain signal line 52 formed simultaneously with the drain electrode 16 is arranged above the gate protrusion 53.

Here, the gate protrusion 53 and the capacitance electrode 54
Has a structure in which a drain signal line 52 is formed above a capacitance electrode 54 made of a p-Si film with a shielding film 18 interposed therebetween. Without the shielding film 18, capacitive coupling occurs between the drain signal line 52 and the capacitive electrode 54, and the capacitive electrode follows the voltage applied to the drain signal line 52 that changes every horizontal synchronization period. As a result, the voltage applied to the display electrode 54 changes with respect to the voltage that should be held.
Since the voltage applied to the liquid crystal 22 also changes, the holding voltage, that is, the effective voltage applied to the liquid crystal 22 becomes small, and the display becomes white and the contrast is lowered.

In order to prevent this, a shielding film 18 is provided between the capacitance electrode 54 and the drain signal line 52, that is, on the interlayer insulating film 17. Further, a flattening insulating film 19 made of, for example, an organic resin and flattening the surface is provided thereon.

A contact hole is formed at a position corresponding to the source 13s of the planarizing insulating film 19, the interlayer insulating film 17, and the interlayer insulating film 15, and an ITO (Indium) contacting the source 13s through the contact hole.
The display electrode 20 made of Tin Oxide) is flattened by the insulating film 19.
Provided above.

On the display electrode 20 and the flattening insulating film 19, an alignment film 21 for aligning the liquid crystal 22 is formed.

Thus, the TFT substrate 10 having the TFT is provided.
Is completed.

A counter electrode substrate 30 provided to face the TFT substrate 10 includes a counter electrode 31 made of a transparent material and an alignment film 3 made of an organic resin or the like in order from the substrate 30 side.
2 are formed.

The substrates 10 and 30 are opposed to each other, the periphery thereof is adhered with a sealing adhesive, the liquid crystal 22 is filled in the gap between the substrates, and the polarizing plate 33 is attached to the outside of the substrates to form an LCD. Is completed.

[0016]

As described above, on the interlayer insulating film 15, besides the transmitted light from the display electrode 20, for example, the shielding film 18 is formed so as to block the transmitted light from around the display electrode 20. Is provided. Further, in the light-shielding film 18, the potential of the light-shielding film changes due to the potential applied to the display electrode 20 and the like, and the potential of the channel of the TFT changes due to the influence on the channel of the TFT.
To prevent this, a constant potential, for example, a potential such as a gate potential or a ground potential is applied.

The channel 13c region and the drain 13
The junction with d or the junction between the channel 13c and the source 13s is also covered with the light shielding film 18.

However, these have the drawback that the electric field is concentrated at the junction and the leakage current increases.

Therefore, the present invention has been made in view of the above-mentioned conventional disadvantages, and suppresses the fluctuation of the auxiliary capacitance and the increase in the leak current of the TFT, thereby reducing
It is an object of the present invention to provide a display device capable of sufficiently maintaining a voltage applied to a liquid crystal and obtaining good display.

[0020]

A display device according to the present invention comprises a plurality of gate signal lines serving also as gate electrodes on an insulating substrate;
And a display device in which display pixels are arranged in each region surrounded by a plurality of drain signal lines, wherein a part of a gate signal line connected to a display pixel in a previous stage is arranged in a direction of the display pixel in the next stage. An auxiliary capacitance forming portion that forms a capacitance with a gate protrusion arranged so as to protrude in an extending direction of the drain signal line and a semiconductor film provided via the gate protrusion and a first insulating film; A shielding film provided to cover the semiconductor film via the semiconductor film and a second insulating film; and the drain signal line provided on the shielding film via the shielding film and a third insulating film. And a display electrode provided on the drain signal line via a fourth insulating film. The semiconductor film has a channel in a region intersecting the gate electrode,
And a source and a drain on both sides of the channel, wherein the shielding film is provided on the second insulating film on the semiconductor film and above the channel, and in a channel length direction of the shielding film Has a width smaller than a channel length of the channel, and does not overlap with a junction between the drain and the source and the channel.

In the display device according to the present invention, display pixels are arranged in an area surrounded by a plurality of gate signal lines also serving as gate electrodes and a plurality of drain signal lines on an insulating substrate. A display device comprising an auxiliary capacitance electrode line forming a capacitance corresponding to each display pixel, wherein a part of the auxiliary capacitance electrode line is arranged so as to protrude in an extending direction of the drain signal line. And an auxiliary capacitance forming portion that forms a capacitance with the auxiliary capacitance electrode projecting portion and a semiconductor film provided with a first insulating film interposed therebetween, wherein the semiconductor film is formed with the semiconductor film and the second insulating film interposed therebetween. A shielding film provided so as to cover the film, the drain signal line provided on the shielding film via the shielding film and the third insulating film, and a fourth insulating film on the drain signal line. And a display electrode provided in the semiconductor device. The film has a channel in a region intersecting with the gate electrode, and a source and a drain on both sides of the channel, and the shielding film is on the second insulating film on the semiconductor film and above the channel. A width of the shielding film in a channel length direction is smaller than a channel length of the channel, and does not overlap with a junction between the drain and the source and the channel.

Further, in the display device according to the present invention, in the display device described above, the shielding film is connected to the gate electrode and a gate potential is applied, or a ground potential is applied. .

Further, the display device of the present invention is the display device described above, wherein the shielding film is made of an opaque material.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS <First Embodiment> A case where a display device of the present invention is applied to an LCD will be described.

FIG. 1 is a plan view showing one display pixel of the LCD, FIG. 2A is a cross-sectional view taken along the line AA in FIG. 1, and FIG. FIG. 3 shows a cross-sectional view along the line BB, and FIG. 3 shows a cross-sectional view along the line CC in FIG.

As shown in FIG. 1, the gate electrode 11 is partially
And a plurality of drain signal lines 5 (hatched from upper right to lower left in the figure).
The display electrodes 20 forming display pixels are provided in each region surrounded by
Are formed, and the display electrode 20 is formed by a TFT.
It is connected to the.

At this time, the gate projection 53 vertically projecting from the gate signal line 51 extends in the direction in which the drain signal line 52 extends (vertical direction in the drawing), and overlaps with the drain signal line 52. Are located.

By arranging in this manner, an auxiliary capacitance described later can be formed without lowering the aperture ratio.

As shown in FIG. 2B, the active layer 13 of the TFT is formed of a p-Si film, the drain 13d provided on the active layer 13 is connected to the drain signal line 52, and the source 13s Are connected to the display electrode 20.

The gate electrode 11 and the gate insulating film 12
A channel 13c is formed in the active layer 13 superimposed through the channel 13c. In the present embodiment, there are two channels 13c because of the double gate structure.

Further, the source 13 s is disposed so as to extend so as to overlap the entire gate protrusion 53, and
Has formed. Thus, a capacitance is formed via the gate insulating film 12 between the capacitance electrode 54 and the gate protrusion 53. The capacitance electrode 54 has a p-S
It is formed of an i film.

The shielding film 18 is formed via the first interlayer insulating film 15 formed on the capacitance electrode 54. A second interlayer insulating film 17 is provided on the shielding film 18, and a drain signal line 52 made of a conductive material such as Al is formed thereon. A flattening insulating film 19 made of an organic resin and flattening the surface is provided on the drain signal line 52, and a display electrode 20 made of ITO is formed thereon.

The structure of the LCD will be described with reference to FIG.

As shown in FIG. 2 (b), Cr, Cr,
A gate signal line 51 made of a refractory metal such as Mo and a gate electrode 11 forming a part thereof are provided. On the gate electrode 11, a gate insulating film 12, which is a first insulating film, and an active layer 13 made of a p-Si film are formed in this order. A channel 13c which is intrinsically intrinsic and a low-concentration region so-called LDD region formed by ion implantation using the stopper insulating film 14 as a mask on both sides of the channel 13c are provided. Source 13 as an area
s and a drain 13d are provided. Note that FIG.
As shown in (a), a charge is accumulated between a gate protrusion 53 protruding from the gate signal line 51 and a capacitor electrode 54 formed by extending the source 13s of the active layer 13 to form a capacitor. ing. This capacitance is an auxiliary capacitance provided for holding a voltage applied to the liquid crystal 22. The gate projection 53 is formed of the same material at the same time as the gate electrode 11 and the gate signal line 51.

The entire surface of the gate insulating film 12, the active layer 13, and the stopper insulating film 14 is formed of, for example, SiO 2
_There is provided an interlayer insulating film 15 which is a second insulating film laminated in order of _two films, a SiN film and a SiO ₂ film.

A shielding film 18 made of a metal which is an opaque material for shielding light, for example, Cr, Mo, titanium (Ti) or the like is formed thereon. Further, for example, an SiO ₂ film, S
An interlayer insulating film 17, which is a third insulating film formed by laminating an iN film and a SiO ₂ film in this order, is provided. Then, a drain electrode 16 is provided by filling a metal such as Al into a contact hole provided in the interlayer insulating film 15 and the interlayer insulating film 17 corresponding to the drain 13d. At this time, as shown in FIG. 2A, the drain signal line 52 formed simultaneously with the drain electrode 16 is disposed above the protrusion 53 of the gate electrode 11.

Further, a flattening insulating film 19 made of, for example, an organic resin and serving as a fourth insulating film for flattening the surface is provided thereon.

Then, a contact hole is formed at a position corresponding to the source 13 s of the planarizing insulating film 19, the interlayer insulating film 17 and the interlayer insulating film 15, and a transparent conductive material which is in contact with the source 13 s through the contact hole. A display electrode 20 made of a certain ITO is provided on the planarization insulating film 19.

On the display electrode 20 and the flattening insulating film 19, an alignment film 21 for aligning the liquid crystal 22 is formed.

Thus, the TFT substrate 10 having the TFT
Is completed.

On a counter electrode substrate 30 provided to face the TFT substrate 10, a counter electrode 31 made of a transparent conductive material and an alignment film 32 made of an organic resin or the like are formed in this order from the substrate 30 side.

The substrates 10 and 30 are opposed to each other, the periphery thereof is adhered with a sealing adhesive, the liquid crystal 22 is filled in the gap between the substrates, and the polarizing plate 33 is attached to the outside of the substrates to form an LCD. Is completed.

The shielding film 18 is formed such that the width of the light shielding film in the channel length direction is smaller than the channel length of the channel 13c of the TFT in the TFT region. And drain 1
3d or junction 13 or channel 13c and source 13
s is arranged so as not to overlap with the joint 72 with
The drain signal line forming the auxiliary capacitance is formed so as to cover the gate projection 53 and the capacitance electrode 54 forming a capacitance.

As described above, the width of the light-shielding film in the channel direction is made smaller than the channel length, and its end 70 is
By not overlapping with the first and second joints 71 and 72,
No electric field concentration occurs, and the occurrence of leakage current can be suppressed.

Since the shielding film 18 covers the capacitance electrode 54 made of the p-Si film in the auxiliary capacitance forming portion,
The leakage light around the display electrode 20 can be shielded, the capacitance coupling between the capacitance electrode 54 made of p-Si and the drain signal line 52 can be prevented, and the voltage applied to the drain signal line 52 can be reduced. Capacitance electrode 54
, And a decrease in the holding voltage can be suppressed.

Therefore, it is possible to prevent the voltage applied to the display electrode from fluctuating in accordance with the voltage applied to the drain signal line and changing every horizontal period, thereby preventing the display from becoming white, thereby preventing a reduction in contrast. Can be prevented.

Further, as shown in FIG.
The shield film 18 and the gate electrode 11 are connected via contact holes provided in the gate insulating film 12 and the gate insulating film 12, and
The same potential as the potential applied to the gate electrode 11 for each gate signal line 51 in each row is applied to the shielding film 18.

Therefore, a gate voltage can be applied to the channel 13c of the TFT from the gate electrode 11 side and the shielding film 18 side, and the current when the TFT is turned on can be increased. For this reason, the charging time of the signal voltage to the display electrode 20 can be shortened, and the deterioration of the display quality such as the contrast difference between the left and right can be prevented. <Second Embodiment> A case where the display device of the present invention is applied to an LCD will be described.

FIG. 4 is a plan view showing one display pixel of the LCD, FIG. 5A is a sectional view taken along the line AA in FIG. 4, and FIG. FIG. 6 shows a cross-sectional view along the line BB, and FIG. 6 shows a cross-sectional view along the line CC in FIG.

This embodiment is different from the first embodiment in that an auxiliary capacitance electrode projection 55 projecting from the auxiliary capacitance electrode line 60 and a capacitance electrode 54 made of p-Si forming the source 13s are used. The point is to form a capacitance.

As shown in FIG. 4, the gate electrode 11 is partially formed.
And a plurality of drain signal lines 5 (hatched from upper right to lower left in the figure).
The display electrodes 20 forming display pixels are provided in each region surrounded by
Are formed, and the display electrode 20 is formed by a TFT.
It is connected to the.

At this time, the auxiliary capacitance electrode projection 55 vertically protruding from the auxiliary capacitance electrode line 60 is connected to the drain signal line 5.
2 extend in the extending direction (vertical direction in the figure), and are arranged so as to overlap with the drain signal line 52.

With this arrangement, although the aperture ratio is somewhat reduced, the additional capacitance of the gate signal line can be reduced, and a deterioration in display quality such as a difference between left and right contrast can be prevented.

As shown in FIG. 5B, the active layer 13 of the TFT is formed of a p-Si film, the drain 13d provided on the active layer 13 is connected to the drain signal line 52, and the source 13s Are connected to the display electrode 20.

The gate electrode 11 and the gate insulating film 12
A channel 13c is formed in the active layer 13 superimposed through the channel 13c. In the present embodiment, there are two channels 13c because of the double gate structure.

Further, the source 13 s is arranged so as to extend so as to overlap with the entire auxiliary capacitance electrode projection 55, thereby forming a capacitance electrode 54. Thus, a capacitance is formed between the capacitance electrode 54 and the auxiliary capacitance electrode projection 55 via the gate insulating film 12. The capacitance electrode 54 is formed of a p-Si film simultaneously with the formation of the active layer 13.

The shielding film 18 is formed via the first interlayer insulating film 15 formed on the capacitance electrode 54. A second interlayer insulating film 17 is provided on the shielding film 18, and a drain signal line 52 made of a conductive material such as Al is formed thereon. A flattening insulating film 19 made of an organic resin and flattening the surface is provided on the drain signal line 52, and a display electrode 20 made of ITO is formed thereon.

The structure of the LCD will be described with reference to FIG.

As shown in FIG. 5B, on an insulating substrate 10 made of quartz glass, non-alkali glass or the like, Cr,
A gate signal line 51 made of a refractory metal such as Mo and a gate electrode 11 forming a part thereof are provided. On the gate electrode 11, a gate insulating film 12, which is a first insulating film, and an active layer 13 made of a p-Si film are formed in this order. A channel 13c which is intrinsically intrinsic and a low-concentration region so-called LDD region formed by ion implantation using the stopper insulating film 14 as a mask on both sides of the channel 13c are provided. Source 13 as an area
s and a drain 13d are provided. FIG.
As shown in (a), the capacitance is accumulated between the auxiliary capacitance electrode projection 55 protruding from the auxiliary capacitance electrode line 60 and the capacitance electrode 54 formed by extending the source 13 s of the active layer 13, and the capacitance is accumulated. Has formed. This capacitance is an auxiliary capacitance provided for holding a voltage applied to the liquid crystal 22. The auxiliary capacitance electrode projection 55 is formed of the same material at the same time as the gate electrode 11 and the gate signal line 51.

Then, the entire surface of the gate insulating film 12, the active layer 13, and the stopper insulating film 14, for example, SiO 2
_There is provided an interlayer insulating film 15 which is a second insulating film laminated in order of _two films, a SiN film and a SiO ₂ film.

A shielding film 18 made of a metal which is an opaque material for shielding light, for example, Cr, Mo, titanium (Ti) or the like is formed thereon. Further, for example, an SiO ₂ film, S
An interlayer insulating film 17, which is a third insulating film formed by laminating an iN film and a SiO ₂ film in this order, is provided. Then, a drain electrode 16 is provided by filling a metal such as Al into a contact hole provided in the interlayer insulating film 15 and the interlayer insulating film 17 corresponding to the drain 13d. At this time, as shown in FIG. 5A, the drain signal line 52 formed simultaneously with the drain electrode 16 is disposed above the auxiliary capacitance electrode projection 55.

Further, a flattening insulating film 19 made of, for example, an organic resin and serving as a fourth insulating film for flattening the surface is provided thereon.

Then, a contact hole is formed at a position corresponding to the source 13 s of the planarizing insulating film 19, the interlayer insulating film 17, and the interlayer insulating film 15, and a transparent conductive material which is in contact with the source 13 s through the contact hole. A display electrode 20 made of a certain ITO is provided on the planarization insulating film 19.

On the display electrode 20 and the flattening insulating film 19, an alignment film 21 for aligning the liquid crystal 22 is formed.

As described above, the TFT substrate 10 having the TFT
Is completed.

On a counter electrode substrate 30 provided to face the TFT substrate 10, a counter electrode 31 made of a transparent conductive material and an alignment film 32 made of an organic resin or the like are formed in this order from the substrate 30 side.

The substrates 10 and 30 are opposed to each other, the periphery thereof is adhered with a sealing adhesive, the gap between the substrates is filled with the liquid crystal 22, and the polarizing plate 33 is attached to the outside of the substrates to form an LCD. Is completed.

Here, the shielding film 18 is formed such that the width of the light shielding film in the channel length direction is smaller than the channel length of the channel 13c of the TFT in the TFT region, and the end portion 70 is formed in the channel 13c. And drain 1
3d or junction 13 or channel 13c and source 13
s is arranged so as not to overlap with the joint 72 with
The auxiliary capacitance forming portion for forming the auxiliary capacitance is formed so as to cover the gate projecting portion 53 and the capacitance electrode 54 forming the capacitance.

As described above, the width of the light-shielding film in the channel direction is made smaller than the channel length, and its end 70 is
By not overlapping with the first and second joints 71 and 72,
No electric field concentration occurs, and the occurrence of leakage current can be suppressed.

Since the shielding film 18 covers the capacitance electrode 54 made of the p-Si film in the auxiliary capacitance forming portion,
The leakage light around the display electrode 20 can be shielded, the capacitance coupling between the capacitance electrode 54 made of p-Si and the drain signal line 52 can be prevented, and the voltage applied to the drain signal line 52 can be reduced. Capacitance electrode 54
, And a decrease in the holding voltage can be suppressed.

For this reason, it is possible to prevent the voltage applied to the display electrode from fluctuating in accordance with the voltage applied to the drain signal line and changing every one horizontal period, thereby preventing the display from becoming white, thereby preventing a decrease in contrast. Can be prevented.

Further, as shown in FIG.
The shield film 18 and the gate electrode 11 are connected via contact holes provided in the gate insulating film 12 and the gate insulating film 12, and
The same potential as the potential applied to the gate electrode 11 for each gate signal line 51 in each row is applied to the shielding film 18.

Therefore, a gate voltage can be applied to the channel 13c of the TFT from the gate electrode 11 side and the shielding film 18 side, and the current when the TFT is turned on can be increased. For this reason, the charging time of the signal voltage to the display electrode 20 can be shortened, and the deterioration of the display quality such as the contrast difference between the left and right can be prevented.

In each of the above embodiments, the p-Si film is used as the semiconductor film of the active layer. However, a microcrystalline silicon film or an amorphous silicon film may be used.

Further, in this embodiment, the case where the present invention is applied to an LCD is shown, but the present invention is not limited to this. Even when applied to an organic EL display device, the same effects as those of the present invention can be obtained. be able to.

In each embodiment, the shielding film 1
8 has been described as being the same as the potential of the gate electrode 11 for supplying a gate signal to the TFT connected to the display electrode of the preceding stage, but the present invention is not limited to this. You may. In that case,
As in the case where the gate potential is applied, the effect of reducing the leakage current of the present application can be obtained.

[0077]

According to the present invention, it is possible to suppress the electric field concentration at the junction caused by the shielding film covering the entire surface of the channel, thereby obtaining a display device having a TFT with no leakage current. Since a constant holding voltage can be obtained irrespective of the voltage applied to the drain signal line that changes every horizontal synchronization period, it is possible to obtain a display device capable of obtaining a favorable display without a decrease in contrast.

[Brief description of the drawings]

FIG. 1 is a plan view showing a first embodiment when the present invention is applied to an LCD.

FIG. 2 is a sectional view showing a first embodiment when the present invention is applied to an LCD.

FIG. 3 is a sectional view showing a first embodiment when the present invention is applied to an LCD.

FIG. 4 is a plan view showing a second embodiment when the present invention is applied to an LCD.

FIG. 5 is a sectional view showing a second embodiment when the present invention is applied to an LCD.

FIG. 6 is a sectional view showing a second embodiment when the present invention is applied to an LCD.

FIG. 7 is a plan view of a conventional LCD.

FIG. 8 is a cross-sectional view of a conventional LCD.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 TFT substrate 11 Gate electrode 13s Source 13d Drain 13c Channel 16 Drain electrode 18 Shielding film 20 Display electrode 30 Counter electrode substrate 51 Gate signal line 52 Drain signal line 53 Gate projection 54 Capacitance electrode 55 Auxiliary capacitance electrode projection 60 Auxiliary capacitance electrode Line 70 Light-shielding film end 71 Junction between channel and drain 72 Junction between channel and source

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H092 GA29 JA24 JA36 JA37 JA41 JA46 JB51 JB69 KB25 NA07 NA19 NA26 PA11 5C094 AA06 AA07 AA25 AA54 BA03 BA29 BA43 CA19 DA13 DA15 DB04 EA04 ED15 FA01 FA02 5F110 AA08 DD18 EE28 EE36 GG02 GG13 GG14 GG15 GG35 HJ13 HM15 NN03 NN16 NN23 NN24 NN44 NN46 NN73 QQ11

Claims (4)

[Claims] 1. A display device in which display pixels are arranged in a region surrounded by a plurality of gate signal lines also serving as a gate electrode and a plurality of drain signal lines on an insulating substrate, wherein the display pixels in a preceding stage are provided. A gate signal line connected to the gate signal line and a first insulating film arranged so as to protrude in the direction of the display pixel in the next stage and in the direction in which the drain signal line extends. A shielding film provided so as to cover the semiconductor film via the semiconductor film and a second insulating film; and a shielding film provided to cover the semiconductor film via the semiconductor film and a second insulating film. And a drain signal line provided on the shielding film via a third insulating film; and a display electrode provided on the drain signal line via a fourth insulating film. Is a channel in a region intersecting with the gate electrode, And a source and a drain on both sides of the channel, wherein the shielding film is provided on the second insulating film on the semiconductor film and above the channel, and a channel length direction of the shielding film is provided. Wherein the width of the channel is smaller than the channel length of the channel and does not overlap with the junction between the drain and source and the channel. 2. A display pixel is arranged on an insulating substrate in a region surrounded by a plurality of gate signal lines also serving as a gate electrode and a plurality of drain signal lines. What is claimed is: 1. A display device comprising an auxiliary capacitance electrode line forming a capacitance, comprising: an auxiliary capacitance electrode projection in which a part of the auxiliary capacitance electrode line is projected in a direction in which the drain signal line extends; An auxiliary capacitance forming unit that forms a capacitance with the protrusion and the semiconductor film provided via the first insulating film;
A shielding film provided to cover the semiconductor film via the semiconductor film and a second insulating film; and the drain signal line provided on the shielding film via the shielding film and a third insulating film. And a display electrode provided on the drain signal line via a fourth insulating film. The semiconductor film has a channel in a region intersecting with the gate electrode, and a source and a drain on both sides of the channel. The shielding film is provided on the second insulating film on the semiconductor film and above the channel, and a width of the shielding film in a channel length direction is larger than a channel length of the channel. A display device which is narrow and does not overlap with a junction between the drain and the source and the channel. 3. The display device according to claim 1, wherein the shielding film is connected to the gate electrode and a gate potential is applied thereto or a ground potential is applied thereto. 4. The display device according to claim 1, wherein the shielding film is made of an opaque material.