JP2010026237A - Liquid crystal display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display that reduces a flicker. <P>SOLUTION: The liquid crystal display has first and second substrates which have a plurality of pixels arranged in a matrix form and are disposed opposite each other with a liquid crystal layer interposed, a first electrode formed in a planar shape at least in each pixel on the first substrate side, and a plurality of second linear electrodes formed above the first electrode with a first insulating layer interposed and overlapping with the first electrode by the pixels, and drives the liquid crystal layer with an electric field produced by the first electrode and the second electrodes, wherein a third linear electrode is held at the same potential with the first electrode, formed in the same layer with the second electrodes, and disposed between the second electrodes. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device in which a storage capacitor is constituted by a pixel electrode and a counter electrode.

  A conventional liquid crystal display device is sandwiched between a first substrate shown in FIG. 2 on which pixel electrodes and the like are formed, a second substrate disposed opposite to the first substrate, and the first substrate and the second substrate. And a liquid crystal layer.

  In the conventional liquid crystal display device configured as shown in FIG. 2, a signal is input from the gate line GL to the gate electrode GT of the thin film transistor TFT, and a signal from the drain line DL is input to the drain electrode DT. Is input. On the other hand, the source of the thin film transistor TFT is provided with a pixel electrode PX for applying an electric field corresponding to display data to the liquid crystal layer, and a storage capacitor for holding the charge supplied to the pixel electrode PX for one frame period. Cst1 is provided between the pixel electrode PX and the counter electrode CT. In addition, a liquid crystal capacitor Clc and an insulating film capacitor Cst2 are formed in series by interposing a liquid crystal layer between the pixel electrode PX and the counter electrode CT.

  3 is a plan view of a liquid crystal display element for one pixel of a conventional liquid crystal display device, FIG. 4 is a sectional view taken along line AA ′ in FIG. 3, and is based on FIGS. The insulating film capacitance will be described.

  As shown in FIGS. 3 and 4, the conventional liquid crystal display device has a configuration in which the pixel electrode PX is arranged via a capacitive insulating film CI formed in the upper layer of the counter electrode CT. In the conventional liquid crystal display device formed in this way, it is generally performed that the pair of electrodes for constituting the storage capacitor is also used as the pixel electrode PX and the counter electrode CT. That is, by using the capacitor insulating film CI as an interlayer insulating film formed between the pixel electrode PX and the counter electrode CT, the pixel electrode PX and the counter electrode CT can be insulated while realizing the insulation between the pixel electrode PX and the counter electrode CT. Thus, the storage capacitance necessary for holding the pixel charge is realized.

  In such a conventional liquid crystal display device, the amplitude at the time of AC inversion driving is caused by fixed charges existing inside the capacitive insulating film CI or at the interface between the liquid crystal layer and the capacitive insulating film CI, that is, charges accumulated in the insulating film capacitance Cst2. It is known that flicker occurs when the positive polarity is different from the positive polarity and negative polarity.

As a technique for solving this problem, there is a liquid crystal display device described in Patent Document 1. In the liquid crystal display device described in Patent Document 1, after an insulating film is formed on the upper layer of the counter electrode, the shape of the insulating film is etched into a pixel electrode shape to form a pixel electrode.
JP 2007-183299 A

  In the conventional liquid crystal display device, in order to minimize the decrease in the electric field strength applied to the liquid crystal layer, an inorganic material protective insulating film is formed on the upper layer of the thin film transistor, and an organic material planarizing film is formed on the upper layer. The counter electrode and the pixel electrode for driving the liquid crystal layer are formed on the planarizing film.

  However, the technique described in Patent Document 1 has a configuration in which an insulating film is processed into the shape of a comb-shaped pixel electrode, that is, the insulating film at the opening of the comb-shaped pixel electrode is removed.

  For this reason, in the technique described in Patent Document 1, a step difference in the opening of the pixel electrode becomes large, and thus a rubbing failure occurs when a rubbing layer formed on the upper layer of the pixel electrode is formed. There is a problem that the contrast of the apparatus is lowered.

  An object of the present invention is to provide a liquid crystal display device capable of reducing flicker.

  Another object of the present invention is to provide a liquid crystal display device capable of suppressing a decrease in contrast due to defective rubbing.

  In order to solve the above problems, the present invention is configured as follows, for example.

  (1) In the liquid crystal display device of the present invention, a plurality of pixels are arranged in a matrix, and at least each pixel is disposed on the first and second substrates opposed to each other with a liquid crystal layer interposed therebetween. A first electrode formed in a planar shape inside, and a plurality of linear electrodes formed on the first electrode via a first insulating layer and superimposed on the first electrode for each pixel. A liquid crystal display device having a second electrode and driving the liquid crystal layer with an electric field generated by the first electrode and the second electrode, the liquid crystal display device having the same potential as the first electrode, and the same as the second electrode It is provided with a linear third electrode which is formed in a layer and arranged with the second electrodes interposed therebetween.

  (2) In the liquid crystal display device according to (1), the first electrode and the third electrode are formed of a conductive layer integrally formed.

  (3) In the liquid crystal display device according to (1) or (2), a groove is formed in the planarization layer, and a part of the first electrode is formed in the groove.

  (4) In the liquid crystal display device according to (1) or (2), the liquid crystal display device has a second insulating layer formed in an upper layer of a planarizing layer, and the first electrode is formed in a groove formed in the second insulating layer. Is formed.

  (5) In the liquid crystal display device according to (1), the first electrode and the third electrode are connected through a contact portion formed in the first insulating layer.

  (6) In the liquid crystal display device according to (1) or (5), the first insulating layer is formed of a capacitive insulating layer, and the second electrode and the third electrode are formed on the first insulating layer. It is what is done.

  (7) In the liquid crystal display device according to any one of (1) to (7), the liquid crystal display device includes a thin film transistor that inputs display charges to the second electrode, and the source electrode and the second electrode of the thin film transistor are provided. The contact portion to be connected is flattened with the first insulating layer.

  In the liquid crystal display device of the present invention, it has the same potential as the counter electrode, is formed in the same layer as the pixel electrode, and includes a linear third electrode disposed with the pixel electrode in between. The capacitance generated between the liquid crystal layer and the insulating layer can be greatly reduced, and flicker can be reduced.

  In addition, since each pixel has a third electrode formed on the same layer as the pixel electrode, it is possible to prevent a rubbing layer formed on the upper layer of the pixel electrode from being defective and to reduce the contrast of the liquid crystal display device. Can be prevented.

  Other effects of the present invention will become apparent from the description of the entire specification.

  Hereinafter, an example of an embodiment to which the present invention is applied will be described with reference to the drawings. In the following description, the structure of the liquid crystal display device may be described by its manufacturing process. However, in the following description, the same components are denoted by the same reference numerals, and repeated description is omitted.

(Embodiment 1)
5 is a schematic configuration diagram of the liquid crystal display device according to the first embodiment of the present invention, and FIG. 6 is a plan view of a liquid crystal display element for one pixel of the liquid crystal display device according to the first embodiment shown in FIG. FIG. 7 is a cross-sectional view taken along line BB ′ shown in FIG. 6. Although the case of an amorphous silicon TFT is described as the thin film transistor, the present invention is not limited to this, and a polysilicon TFT may be used. A diode or the like may be used as the switching element instead of the thin film transistor.

  The liquid crystal display device of Embodiment 1 includes a first substrate on which pixel electrodes and the like are formed, a second substrate disposed opposite to the first substrate, a first substrate, and a second substrate, as will be described later. It is comprised with the liquid crystal layer pinched | interposed.

As shown in FIG. 5, the first substrate of the liquid crystal display device of Embodiment 1 has a configuration in which a large number of gate lines GL are arranged in the horizontal direction and a large number of drain lines DL are arranged in the vertical direction. A pixel composed of a thin film transistor TFT and a pixel capacitor is formed at each intersection of each gate line GL and each drain line DL. Further, a common line CL for supplying a common voltage (common voltage) to the counter electrode of each pixel is configured in parallel with the drain line DL. A gate signal for pixel selection from the gate driver SCDv is supplied to the gate line GL, and a drain signal that is a write voltage to each pixel is supplied from the drain driver SCDh to the drain line. The common line CL is configured to be supplied with a common signal (reference signal (voltage)) corresponding to the driving format of the liquid crystal display device from a common driver (not shown). However, a rectangular region surrounded by a pair of adjacent gate lines GL and a pair of adjacent drain lines DL constitutes a region where pixels are formed, and these pixels are arranged in a matrix in the liquid crystal display region AR. The

  In the first substrate of the liquid crystal display device of the first embodiment configured as described above, a gate signal (scanning signal (voltage)) is input from the gate line GL to the gate electrode GT of the thin film transistor TFT. A drain signal (video signal (voltage)) from the drain line DL is input to the drain electrode DT. On the other hand, the source of the thin film transistor TFT is provided with a pixel electrode PX for applying an electric field corresponding to display data to the liquid crystal layer, and a storage capacitor for holding the charge supplied to the pixel electrode PX for one frame period. Is provided between the pixel electrode PX and the counter electrode CT. At this time, as will be described later, since the capacitor insulating film CI is not interposed between the counter electrode CT and the pixel electrode PX formed on the upper surface of the planarizing film PASo, only the liquid crystal capacitor Clc is formed, and the source of the thin film transistor TFT The storage capacitor Cst1 and the pixel capacitor Clc are simply connected in parallel.

  Next, based on FIG.1 and FIG.6, the detailed structure of the 1st board | substrate of the liquid crystal display device of Embodiment 1 is demonstrated. In the following description, one pixel is described, but it goes without saying that other pixel structures have the same configuration. Further, in order to simplify the description, a case where two pixel electrodes are formed in a comb shape as a plurality of linear electrodes will be described, but the present invention is not limited to this, and three or more pixel electrodes are combined. The present invention can also be applied to shapes arranged in a tooth shape.

  As shown in FIG. 6, in the first substrate of the liquid crystal display device according to the first embodiment, the pixel electrode PX is arranged via the capacitive insulating film CI formed on the upper layer of the counter electrode CT formed in a planar shape. It has become. The counter electrode CT is made of ITO (Indium Tin Oxide), which is a transparent electrode material, and is connected to the common line CL through the contact hole TH2. The pixel electrode PX is also made of ITO formed in a comb shape, and is electrically connected to the source electrode ST of the thin film transistor TFT through the contact hole TH1 formed in the planarizing film PASo and the protective insulating film PASi. . On the other hand, the drain line DL extends to the formation region side of the thin film transistor TFT at a part of the intersection with the gate line GL, and this extended portion reaches the upper surface of the semiconductor layer AS to form the drain electrode DT of the thin film transistor TFT. is doing.

  The pixel PIX includes a thin film transistor TFT that is turned on by a gate signal from the gate line GL, a pixel electrode PX to which a drain signal from the drain line DL is supplied via the turned on thin film transistor TFT, and a common signal applied to the pixel PIX. And a counter electrode CT that generates an electric field due to a potential difference with the electrode PX. The pixel electrode PX and the counter electrode CT are both formed on the first substrate SUB1, which is the same substrate, and the electric field partially includes an electric field component parallel to the surface of the first substrate SUB1.

  As described above, in the first substrate of the liquid crystal display device according to the first embodiment, the pixel electrode PX is formed so as to overlap the counter electrode CT formed on the bottom of the trench (groove) TF with the capacitive insulating film CI interposed therebetween. In addition, the counter electrode CT outside the trench region is formed in the same layer as the pixel electrode PX, and the counter electrode CT outside the trench region and the trench region is integrally formed including the trench edge. Regardless of the configuration, a common signal having the same potential is input.

  Here, in the first substrate of the liquid crystal display device of Embodiment 1, the trench TF is formed along the outer peripheral shape of the pixel electrode PX, and the pixel electrode PX is formed in the trench TF region. Yes. In particular, the first substrate of the liquid crystal display device according to the first embodiment has a configuration in which the capacitor insulating film CI is formed only in the trench TF region, and the pixel is interposed via the capacitor insulating film CI in the trench TF region. The electrode PX is superposed on the counter electrode CT. Therefore, in the region related to the display, the counter electrode CT in the trench TF region is configured as a planar electrode with respect to the pixel electrode PX formed in a linear shape, and the pixel is formed by the counter electrode CT outside the trench TF region. The electrode PX is sandwiched therebetween. At this time, in the first substrate of the first embodiment, the size of the pixel electrode PX is formed to be the same size as the conventional pixel electrode, so that a storage capacitor necessary for holding the charge written in the pixel electrode PX is realized. It has a sufficient structure.

  Next, the structure of the pixel electrode and the counter electrode according to the first embodiment will be described in detail with reference to FIG. As shown in FIG. 1, in the first substrate of the liquid crystal display device of Embodiment 1, a base film IN1 for protecting the thin film transistor TFT is formed on the upper layer of the glass substrate SUB1, and the gate electrode GT and the gate insulating film are formed on the upper layer. A thin film transistor TFT composed of GI, semiconductor layer AS, drain electrode DT, source electrode ST, and the like is formed. In order to protect the thin film transistor TFT from an alkali component contained in a liquid crystal layer (not shown), a protective insulating film PASi is formed on the entire upper surface of the thin film transistor TFT. A planarizing layer PASo is laminated on the protective insulating film PASi.

  Here, in the first substrate of the display device according to the first embodiment, the trench TF is formed on the planarizing layer PASo, and the counter electrode CT is formed on the upper surface of the planarizing layer PASo including the surface of the trench TF. Has been. Accordingly, in the region related to the display of the pixel PIX, the linear pixel electrode PX is arranged between the linear counter electrodes CT formed on the planarizing film PASo. In addition, the capacitive insulating film CI is formed up to the level of the planarization layer PASo in the upper layer of the counter electrode CT formed in the trench TF region, and the pixel electrode PX is formed only in the upper layer of the capacitive insulating film CI in the trench TF region. It is the structure formed. Note that the trench TF formed in the central portion in the BB ′ line direction of the cross-sectional view shown in FIG. 1 is a trench TF region corresponding to a region connecting the two pixel electrodes PX, as is apparent from FIG. Therefore, it does not affect the display performance.

  Next, FIG. 7 is a process diagram showing an embodiment of a manufacturing method for forming the counter electrode and the pixel electrode of the liquid crystal display device of Embodiment 1, and the manufacturing method will be described below in order of steps based on FIG. . In addition, since formation of the thin film including formation of the electrode in each process is possible by a well-known photolithography technique, detailed description is abbreviate | omitted.

Step 1. (Fig. 7 (a))
A base film IN1, a gate electrode GT, a gate insulating film GI, a semiconductor layer AS, a drain electrode DT, and a source electrode ST are formed on the upper surface (liquid crystal side) of the glass substrate SUB1, and an amorphous silicon TFT thin film transistor TFT is formed. To do. At this time, the source electrode ST of the thin film transistor TFT formed simultaneously with the drain line DL and the drain electrode DT is formed opposite to the drain electrode DT on the semiconductor layer AS. Further, the source electrode ST extends from the semiconductor layer AS to a region where the semiconductor layer AS is not formed, and this extended portion constitutes a pad portion. This pad portion is a portion that is electrically and physically connected to the pixel electrode PX in a process described later.

Step 2. (Fig. 7 (b))
A protective insulating film PASi made of a silicon nitride film, which is an inorganic material for protecting the thin film transistor TFT, is formed on the entire upper surface of the glass substrate SUB1 to form a protective film for the thin film transistor TFT. A flattening film PASo made of an acrylic film is formed on the upper surface side of the glass substrate by a known spin coating method or the like on the upper layer (the liquid crystal side of the substrate) of the protective insulating film PASi, and the gate lines GL including the thin film transistors TFT, The unevenness on the upper surface of the glass substrate accompanying the formation of the drain line DL, the common line CL, etc. is flattened. In the first substrate of the liquid crystal display device according to the first embodiment, the protective insulating film PASi and the planarizing film PASo constitute a protective film.

  Next, a comb-like trench TF is formed on the upper surface (liquid crystal side surface) of the planarizing film PASo by a known technique.

Step 3. (Fig. 7 (c))
The counter electrode CT is formed of ITO, which is a transparent electrode material, in the same region as the conventional counter electrode. At this time, the first embodiment has a structure in which the upper layer portion from the bottom of the trench TF formed by etching to the region not etched along the edge of the trench TF is covered with the counter electrode CT.

  Next, a capacitive insulating film CI is formed on the upper surface of the glass substrate by forming a coating type insulating film and performing a baking process by a heat treatment of about 200 degrees. At this time, since the ITO film serving as the counter electrode CT is also heat-treated at the same time, the ITO film changes from an amorphous state to a polycrystalline state. Since this polycrystalline ITO film is hardly processed under the etching conditions of the amorphous ITO film, the ITO film to be the counter electrode CT is not simultaneously processed at the time of ITO processing for forming the pixel electrode PX later.

Step 4. (Fig. 7 (d))
The counter electrode CT other than the trench TF portion of the planarizing film PASo is exposed from the capacitive insulating film CI by etching the capacitive insulating film CI to the level of the planarizing film PASo, and the capacitive insulating film CI is formed only in the trench TF portion. Form. By this step, a linear counter electrode CT formed in the same layer as the pixel electrode PX is formed. However, it is desirable to form the capacitor insulating film CI so that the height thereof is lower than that of the ITO film serving as the counter electrode CT.

Step 5 (FIG. 7 (e))
A contact hole TH1 is formed in the planarization layer PASo and the protective insulating film PASi.

Step 6 (FIG. 1)
By forming an ITO film in a region where the contact hole portion TH1 and the trench TF are formed, the pixel electrode PX connected to the source electrode ST of the thin film transistor TFT is formed. By this step, a linear pixel electrode PX that is the same layer as the counter electrode CT is formed between the linear counter electrodes CT.

  FIG. 18 is a cross-sectional view of the liquid crystal display device of the present invention based on the first embodiment. As shown in FIG. 18, the liquid crystal display device of Embodiment 1 includes a glass substrate (second substrate) SUB2 on which a black matrix BM, a color filter CF, and an alignment film ORI2 are formed, and a glass substrate (first substrate) of Embodiment 1. The liquid crystal LC is sandwiched between the substrate SUB1 and the polarizing plate PL is formed on both sides of the two glass substrates SUB1 and SUB2.

  As shown in FIG. 4, the conventional liquid crystal display device has a structure in which the insulating film capacitor Cst2 is connected in series to the liquid crystal capacitor Clc because the counter electrode CT is covered with the capacitor insulating film CI.

  On the other hand, in the liquid crystal display device according to the first embodiment of the present invention, the counter electrode CT is not covered with the capacitor insulating film CI in the region where the liquid crystal capacitor Clc is formed as shown in FIG. Since the film ORI1 is in contact, only the liquid crystal capacitance Clc is formed. Furthermore, the counter electrode CT is formed below the pixel electrode PX via the capacitor insulating film CI, and a high aperture ratio can be realized by forming a transparent storage capacitor. FIG. 18 shows a cross-sectional structure using the first embodiment, but the same effect can be obtained by using the second to fifth embodiments.

  As described above, in the liquid crystal display device according to the first embodiment, in the region related to the display of the pixel PIX, the linear pixel electrode PX is interposed between the linear counter electrodes CT formed on the planarizing film PASo. Therefore, the capacitor insulating film CI can be configured not to be interposed between the counter electrode CT and the pixel electrode PX formed on the upper surface (between the grooves) of the planarizing film PASo. . As a result, the liquid crystal drive signal can be configured to be hardly affected by the fixed charge inside the capacitive insulating film or at the liquid crystal / capacitor insulating film interface, so that a liquid crystal display device with greatly reduced flicker can be provided. it can.

  In addition, since the capacitor insulating film CI has a structure in which the trench TF is embedded, the step on the upper surface of the glass substrate SUB1 can be suppressed to about the film thickness of the ITO electrode, which effectively prevents the alignment film ORI1 from rubbing. Can be suppressed.

Further, since the electric field between the pixel electrode PX and the counter electrode CT can be strengthened by making the height of the capacitor insulating film CI lower than that of the counter electrode CT, the response of the liquid crystal LC can be accelerated. .

(Embodiment 2)
FIG. 8 is a cross-sectional view for explaining a schematic configuration of a liquid crystal display device according to Embodiment 2 of the present invention. 8 is a cross-sectional view of the first substrate corresponding to FIG. 1 of the first embodiment, and corresponds to a cross-sectional view taken along line BB ′ of FIG. The LCD configuration diagram and pixel plan view of the second embodiment are the same as those in FIGS. 5 and 6, respectively.

  As is apparent from FIG. 8, the liquid crystal display device according to the second embodiment has a configuration in which the counter electrode CT, the pixel electrode PX, and the like are formed on the upper surface side (the liquid crystal layer LC side not shown) of the planarizing film PASo. In the following description, the configuration of the trench insulating film TI, the counter electrode CT, the capacitor insulating film CI, and the pixel electrode PX, which are different in configuration from the liquid crystal display device of Embodiment 1, will be described in detail.

  In FIG. 8, the liquid crystal display device according to the second embodiment has a configuration in which a trench insulating film TI made of, for example, a silicon nitride film or the like is formed on the planarizing film PASo. Of the region where the trench insulating film TI is formed, a trench (groove) TF reaching the planarizing film PASo is formed in the region where the pixel electrode PX is formed. On the other hand, since the counter electrode CT is formed in the pixel region excluding the formation region of the contact hole TH1, not only the upper layer of the trench insulating film TI but also the bottom (exposed planarizing layer) of the trench (groove) TF. A counter electrode CT having a predetermined film thickness is formed from PASo) to the edge thereof. Therefore, in the region related to the display of the pixel PIX, the linear pixel electrode PX is arranged between the linear counter electrodes CT formed in the trench insulating film TI.

  Here, also in the liquid crystal display device of the second embodiment, like the liquid crystal display device of the first embodiment, a capacitive insulating film is formed on the counter electrode CT in a region where the trench TF is formed (hereinafter referred to as a trench region). CI is formed to the same height as the trench insulating film TI. Further, the pixel electrode PX is formed only in the upper layer of the capacitor insulating film CI formed only in the trench region. However, the contact hole TH1 portion and the portion to which the comb-like pixel electrode PX is connected are not limited to this.

  Next, FIG. 9 is a process diagram showing an embodiment of a manufacturing method for forming the counter electrode and the pixel electrode of the liquid crystal display device of Embodiment 2, and the manufacturing method will be described in the order of steps based on FIG. . As in the first embodiment, since a thin film including an electrode in each step can be formed by a known photolithography technique, a detailed description is omitted.

Step 1. (Fig. 9 (a))
A base film IN1, a gate electrode GT, a gate insulating film GI, a semiconductor layer AS, a drain electrode DT, and a source electrode ST are formed on the liquid crystal side surface of the glass substrate SUB1, and a thin film transistor TFT of an amorphous silicon TFT is formed. This step 1 is the same as step 1 in the first embodiment.

Step 2. (Fig. 9 (b))
In order to protect the thin film transistor TFT, a protective insulating film PASi made of a silicon nitride film, which is an inorganic material, is formed on the entire upper surface side (liquid crystal side of the substrate) of the glass substrate SUB1 to form a protective film for the thin film transistor TFT. A planarizing film PASo made of an acrylic film is formed on the upper surface side of the glass substrate SUB1 by a known spin coating method or the like on the protective insulating film PASi (on the liquid crystal side of the substrate), and gate lines GL including the thin film transistors TFT are formed. Then, the unevenness on the upper surface of the glass substrate SUB1 accompanying the formation of the drain line DL, the common line CL, etc. is flattened. The steps up to the formation of the planarizing film PASo in step 2 are the same as those in the first embodiment. Also, in the first substrate SUB1 of the liquid crystal display device according to the second embodiment, the protective insulating film PASi and the planarizing film PASo constitute a protective film.

  Next, a trench insulating film TI made of, for example, a silicon nitride film is formed on the planarizing film PASo. Thereafter, the trench insulating film TI is etched until the planarizing film PASo is exposed, thereby forming a trench TF. It should be noted that the etching region of the trench insulating film TI is a region where the pixel electrode PX is formed in a later process, as in the first embodiment. Although the depth of the trench TI can be controlled by controlling the etching amount of the trench insulating film TI, the trench TI is etched by controlling the film thickness of the trench insulating film TI and etching to the planarizing film PASo. When formed, the depth of the trench TI can be controlled more accurately.

Step 3. (Fig. 9 (c))
Similar to the first embodiment, the counter electrode CT is formed of ITO, which is a transparent electrode material. At this time, the upper layer portion from the bottom of the trench TI formed by etching to the region not etched along the edge of the trench TI is covered with the counter electrode CT formed of an ITO film.

  Next, a capacitive insulating film CI is formed on the entire upper surface of the glass substrate SUB1 by forming a coating type insulating film and performing a baking process by a heat treatment of about 200 degrees. At this time, as in the formation of the capacitive insulating film CI in the first embodiment, the ITO film to be the counter electrode CT is also heat-treated at the same time, so that the ITO film changes from an amorphous state to a polycrystalline state.

Step 4. (Fig. 9 (d))
By etching the capacitive insulating film CI to the height of the trench insulating film TI, the counter electrode CT other than the trench TF portion is exposed from the capacitive insulating film CI, and the capacitive insulating film CI is formed only in the trench TF portion. By this step, a linear counter electrode CT formed in the same layer as the pixel electrode PX is formed. However, it is desirable to form the insulating film CI so that its height is lower than that of the ITO film serving as the counter electrode CT.

Step 5 (FIG. 9 (e))
A contact hole TH1 that penetrates the planarization layer PASo and the protective insulating film PASi from the trench insulating film TI and reaches the pad portion of the source electrode ST is formed.

Step 6 (FIG. 8)
A pixel electrode PX connected to the source electrode ST of the thin film transistor TFT is formed by forming the pixel electrode PX using ITO as an electrode material in a region where the contact hole TH1 portion and the trench TF are formed. By this step, a linear pixel electrode PX that is the same layer as the counter electrode CT is formed between the linear counter electrodes CT.

  As described above, also in the liquid crystal display device of the second embodiment, in the region related to the display of the pixel PIX, the linear pixel electrode PX is disposed between the linear counter electrodes CT formed on the upper surface of the trench insulating film TI. Therefore, the capacitor insulating film CI is not interposed between the counter electrode CT and the pixel electrode PX formed on the upper surface (between the grooves) of the trench insulating film TI. Therefore, the liquid crystal drive signal can be configured to be hardly affected by the fixed charge inside the capacitive insulating film or at the liquid crystal / capacitor insulating film interface, so that it is possible to provide a liquid crystal display device with greatly reduced flicker. .

  In addition, since the capacitor insulating film CI has a structure in which the trench TF is embedded, the step on the upper surface of the glass substrate SUB1 can be suppressed to the thickness of the ITO electrode, which effectively prevents the alignment film from rubbing. Can be suppressed.

In addition, since the electric field between the pixel electrode PX and the counter electrode CT can be increased by making the height of the capacitor insulating film CI lower than that of the counter electrode CT, the response of the liquid crystal can be accelerated.

  In addition to the effects described above, in the liquid crystal display device according to the second embodiment, a film (trench insulating film TI) for forming the trench TF is provided separately from the planarizing film PASo, and the film is etched to form the trench TF. Therefore, the trench depth and the like can be easily controlled. Therefore, it is possible to easily form the trench TI shallowly (that is, to form the capacitor insulating film CI thin) without impairing the flatness on the upper surface side (the liquid crystal layer LC side not shown) of the first substrate SUB1. ) It is possible to obtain a special effect that the storage capacity can be increased.

(Embodiment 3)
FIG. 10 is a plan view of a liquid crystal display element for one pixel for explaining a schematic configuration of the liquid crystal display device according to the first embodiment of the present invention, and FIG. 11 is a cross-sectional view taken along line CC ′ shown in FIG. It is.

  As is apparent from FIG. 10, the liquid crystal display device according to the third embodiment has a configuration in which a trench TF is formed in the planarizing film PASo, and a pixel electrode PX is formed in the trench TF region via a capacitive insulating film CI. Therefore, in the following description, the configuration of the contact hole TH1 having a configuration different from that of the liquid crystal display device of the first embodiment will be described in detail.

  In the liquid crystal display device of Embodiment 3 shown in FIG. 10, the counter electrode CT is formed in a region where the contact hole TH1 for electrically connecting the source electrode ST of the thin film transistor TFT and the pixel electrode PX is formed. The contact hole electrode THT is formed using the same ITO. One of the contact hole electrodes THT is configured to be electrically connected to the source electrode ST, and the other is configured to be electrically connected to the pixel electrode PX. At this time, as is clear from FIG. 10, the counter electrode CT and the contact hole electrode THT are formed at a predetermined distance so that the counter electrode CT and the contact hole electrode THT are not electrically connected.

  As shown in FIG. 11, in the liquid crystal display device according to the third embodiment, the capacitive insulating film CI is formed up to the level of the planarizing film PASo on the contact hole electrode THT, and the capacitive insulating film CI and the contact hole are formed. The pixel electrode PX is formed on the upper layer of the electrode THT. On the other hand, the upper surface (liquid crystal layer) side of the region where the thin film transistor TFT and the pixel electrode PX are formed has the same configuration as that of the liquid crystal display device of the first embodiment, so The film thickness can be suppressed to about the same. As a result, it is possible to effectively suppress the rubbing failure of the alignment film (not shown).

  Next, FIG. 12 is a process diagram showing an embodiment of a manufacturing method of the liquid crystal display device of Embodiment 3, and the manufacturing method will be described below in the order of steps based on FIG. Note that, as in the first and second embodiments, the formation of a thin film including the formation of electrodes in each step can be performed by a known photolithography technique, and thus detailed description thereof is omitted.

Step 1. (Fig. 12 (a))
A base film IN1, a gate electrode GT, a gate insulating film GI, a semiconductor layer AS, a drain electrode DT, and a source electrode ST are formed on the surface of the glass substrate SUB1 on the liquid crystal LC side, and a thin film transistor TFT of an amorphous silicon TFT is formed. In addition, this process 1 is the same as the process 1 of Embodiment 1,2.

Step 2. (Fig. 12 (b))
In order to protect the thin film transistor TFT, a protective insulating film PASi made of a silicon nitride film, which is an inorganic material, is formed on the entire upper surface side (the liquid crystal LC side of the substrate) of the glass substrate SUB1 to form a protective film for the thin film transistor TFT. A flattening film PASo made of an acrylic film is formed on the upper surface side of the glass substrate SUB1 by a known spin coating method or the like on the upper layer of the protective insulating film PASi (the liquid crystal LC side of the substrate), and gate lines including thin film transistors TFT are formed. The unevenness on the upper surface of the glass substrate SUB1 accompanying the formation of the GL, the drain line DL, the common line CL, etc. is flattened. The steps up to the formation of the planarizing film PASo in step 2 are the same as those in the first and second embodiments. Also, in the first substrate SUB1 of the liquid crystal display device according to the third embodiment, the protective insulating film PASi and the planarizing film PASo constitute a protective film.

  Thereafter, a contact hole TH1 that penetrates the planarization layer PASo and the protective insulating film PASi and reaches the pad portion of the source electrode ST is formed.

Step 3. (Fig. 12 (c))
Next, a trench TF along the shape of the pixel electrode PX is formed on the upper surface of the planarizing film PASo.

Step 4. (Fig. 12 (d))
Next, the counter electrode CT is formed of ITO, which is a transparent electrode material, and the contact hole electrode THT is formed in the contact hole TH1. The configuration of the counter electrode CT excluding the contact hole electrode THT is the same as that of the first embodiment.

Step 5. (Fig. 12 (e))
Next, as in the first embodiment, a coating-type insulating film is formed and baked by a heat treatment of about 200 ° C. to form a capacitive insulating film CI on the entire surface. This capacitive insulating film CI is formed on the planarizing film PASo. Etching is performed to expose the counter electrode CT other than the upper part of the contact hole electrode THT and the trench TF from the capacitor insulating film CI. However, it is desirable to form the capacitor insulating film CI so that the height thereof is lower than that of the ITO film serving as the counter electrode CT. Step 6 (FIG. 11)
By forming the pixel electrode PX using ITO as an electrode material in the region where the contact hole TH1 portion and the trench TF are formed, the pixel electrode PX connected to the source electrode ST of the thin film transistor TFT via the contact hole electrode THT is formed. Form. At this time, since the contact hole TH1 is flattened in the third embodiment, the liquid crystal gap can be made uniform even above the contact hole TH1.

  As described above, also in the liquid crystal display device of the third embodiment, the configuration of the pixel electrode PX and the counter electrode CT is the same as that of the first embodiment, that is, in the region related to the display of the pixel PIX, the upper portion of the planarization film PASo. Since the linear pixel electrode PX is arranged between the formed linear counter electrodes CT, the liquid crystal drive signal is almost affected by the fixed charge inside the capacitor insulating film or at the interface between the liquid crystal / capacitor insulating film. Thus, a liquid crystal display device can be provided in which flicker is greatly reduced.

  In addition, since the capacitor insulating film CI has a structure in which the trench TF is embedded, the step on the upper surface of the glass substrate SUB1 can be suppressed to the thickness of the ITO electrode, which effectively prevents the alignment film from rubbing. Can be suppressed.

  In addition, since the electric field between the pixel electrode PX and the counter electrode CT can be increased by making the height of the capacitor insulating film CI lower than that of the counter electrode CT, the response of the liquid crystal can be accelerated.

  In addition to the effects described above, in the liquid crystal display device of Embodiment 3, since the contact hole TH1 is flattened, a special effect that the liquid crystal gap can be made uniform also at the upper part of the contact hole TH1 can be obtained. As a result, the refraction of light in the contact hole TH1 region can be greatly reduced, the black matrix width can be significantly reduced, the black matrix can be eliminated, and the like, so that the aperture ratio can be improved. Can be obtained.

(Embodiment 4)
FIG. 13 is a cross-sectional view for explaining a schematic configuration of a liquid crystal display device according to Embodiment 4 of the present invention. 13 is a cross-sectional view of the first substrate corresponding to FIG. 1 of the first embodiment, and corresponds to a cross-sectional view taken along the line CC ′ of FIG. 10 of the third embodiment. The LCD configuration diagram and the pixel plan view of the fourth embodiment are the same as FIG. 5 of the first embodiment and FIG. 10 of the third embodiment, respectively.

  As is apparent from FIG. 13, the liquid crystal display device of the fourth embodiment has a configuration in which the configuration of the contact hole of the liquid crystal display device of the third embodiment is adapted to the configuration of the liquid crystal display device of the second embodiment.

  That is, in the liquid crystal display device according to the fourth embodiment, the trench insulating film TI is formed in the upper layer of the planarizing film PASo, the trench TF is formed in the trench insulating film TI, and the pixel electrode PX is formed through the capacitive insulating film CI. It has a configuration. Further, the contact hole portion is configured such that the capacitor insulating film CI is formed up to the height of the trench insulating film TI above the contact hole electrode THT, and the pixel electrode PX is formed above the capacitor insulating film CI and the contact hole electrode THT. It is the composition which becomes. At this time, the counter electrode CT and the contact hole electrode THT are formed at a predetermined distance so that the counter electrode CT and the contact hole electrode THT are not electrically connected.

  Next, FIG. 14 is a process diagram showing an embodiment of a manufacturing method of the liquid crystal display device of Embodiment 4, and the manufacturing method will be described below in the order of steps based on FIG. As in the first embodiment, since a thin film including an electrode in each step can be formed by a known photolithography technique, a detailed description is omitted.

Step 1. (Fig. 14 (a))
A base film IN1, a gate electrode GT, a gate insulating film GI, a semiconductor layer AS, a drain electrode DT, and a source electrode ST are formed on the surface of the glass substrate SUB1 on the liquid crystal LC side, and a thin film transistor TFT of an amorphous silicon TFT is formed. This step 1 is the same as step 1 in the first embodiment.

Step 2. (Fig. 14 (b))
In order to protect the thin film transistor TFT, a protective insulating film PASi made of a silicon nitride film, which is an inorganic material, is formed on the entire upper surface side (the liquid crystal LC side of the substrate) of the glass substrate SUB1 to form a protective film for the thin film transistor TFT. A flattening film PASo made of an acrylic film is formed on the upper surface side of the glass substrate SUB1 by a known spin coating method or the like on the upper layer of the protective insulating film PASi (the liquid crystal LC side of the substrate), and gate lines including thin film transistors TFT are formed. The unevenness on the upper surface of the glass substrate SUB1 accompanying the formation of the GL, the drain line DL, the common line CL, etc. is flattened. Next, a trench insulating film TI made of, for example, a silicon nitride film is formed on the planarizing film PASo. The steps up to the formation of the trench insulating film TI in step 2 are the same as those in the second embodiment. Also, in the first substrate SUB1 of the liquid crystal display device according to the fourth embodiment, the protective insulating film PASi and the planarizing film PASo constitute a protective film.

  Thereafter, the trench insulating film TI is etched until the planarizing film PASo is exposed, and a trench TF for forming the counter electrode CT and the pixel electrode PX and a trench TF1 for forming a contact hole are formed.

Step 3 (FIG. 14 (c))
A contact hole TH1 that penetrates the planarization layer PASo and the protective insulating film PASi and reaches the pad portion of the source electrode ST is formed in the region of the trench TF1 formed in step 2.

Step 4. (Fig. 14 (d))
The counter electrode CT is formed of ITO, which is a transparent electrode material, and the contact hole electrode THT is formed in the contact hole TH1 portion. Next, as in the second embodiment, a coating type insulating film is formed and baked by a heat treatment of about 200 ° C. to form a capacitive insulating film CI on the entire surface, and this capacitive insulating film CI is formed on the trench insulating film TI. Etching is performed to expose the counter electrode CT other than the upper part of the contact hole electrode THT and the trench TF from the capacitor insulating film CI.

Step 5 (FIG. 13)
By forming the pixel electrode PX using ITO as an electrode material in the region where the contact hole TH1 portion and the trench TF are formed, the pixel electrode PX connected to the source electrode ST of the thin film transistor TFT via the contact hole electrode THT is formed. Form. At this time, since the contact hole TH1 is also flattened in the fourth embodiment, the liquid crystal gap can be made uniform even above the contact hole TH1.

  As described above, the liquid crystal display device of the fourth embodiment can have the effects of the liquid crystal display devices of the second and third embodiments. For example, in the region related to the display of the pixel PIX, since the linear pixel electrode PX is arranged between the linear counter electrodes CT formed on the upper surface of the trench insulating film TI, the upper surface of the trench insulating film TI is formed. The capacitor insulating film CI is not interposed between the counter electrode CT and the pixel electrode PX (between the grooves). Therefore, the liquid crystal drive signal can be configured to be hardly affected by the fixed charge inside the capacitive insulating film or at the liquid crystal / capacitor insulating film interface, so that it is possible to provide a liquid crystal display device with greatly reduced flicker. .

  Furthermore, in addition to the effects of the liquid crystal display devices of the second and third embodiments, it is possible to simultaneously improve the aperture ratio by flattening the contact hole and the retention capacity by thinning the capacitor insulating film. A special effect can be obtained.

(Embodiment 5)
FIG. 15 is a plan view of a liquid crystal display element for one pixel for explaining a schematic configuration of the liquid crystal display device according to the first embodiment of the present invention, and FIG. 16 is a cross-sectional view taken along line DD ′ shown in FIG. It is. As will be described later, since the capacitor insulating film CI is not interposed between the pixel electrode PX and the upper counter electrode CT2 formed in the same layer, only the liquid crystal capacitor Clc is formed and the source of the thin film transistor TFT is the storage capacitor. The configuration is such that Cst1 and the liquid crystal capacitor Clc are only connected in parallel.

  Based on FIG. 15, the detailed structure of the 1st board | substrate of the liquid crystal display device of Embodiment 5 is demonstrated. In the following description, one pixel is described, but it is needless to say that other pixels have the same structure. Further, in order to simplify the description, a case where two pixel electrodes PX are formed in a comb-teeth shape will be described. However, the present invention is not limited to this, and three or more pixel electrodes PX are arranged in a comb-teeth shape. The present invention can also be applied to shapes that have been made.

  As shown in FIG. 15, in the first substrate SUB1 of the liquid crystal display device of Embodiment 5, the positional relationship between the lower layer counter electrode CT1 and the pixel electrode PX is the same as that of the conventional liquid crystal display device, and the lower layer counter electrode CT1. The pixel electrode PX is arranged through the capacitive insulating film CI formed in the upper layer.

  In the liquid crystal display device according to the fifth embodiment, the upper-layer counter electrode CT2 is formed in the same layer as the pixel electrode PX, that is, the upper layer of the capacitor insulating film CI so as to cover the upper surface of the capacitor insulating film CI. At this time, in order to prevent the pixel electrode PX and the upper layer counter electrode CT2 from being electrically connected, the upper layer counter electrode CT2 is formed along the outer periphery of the pixel electrode PX so as to avoid the pixel electrode PX. Therefore, in the region where the pixel electrode PX is formed, the shape of the upper counter electrode CT2 is also formed in a comb shape.

  The upper counter electrode CT2 is made of ITO and is directly connected to the common line CL via the contact hole TH4. On the other hand, the lower layer counter electrode CT1 formed of ITO is connected to the upper layer counter electrode CT2 via the contact hole TH3. Therefore, a common signal is supplied to the lower counter electrode CT1 and the upper counter electrode CT2, and has the same potential.

  Further, the pixel electrode PX is also made of ITO formed in a comb shape, and is electrically connected to the source electrode ST of the thin film transistor TFT through the contact hole TH1 formed in the planarization film PASo and the protective insulating film PASi. Yes. Accordingly, in the area related to the display of the pixel PIX, the pixel electrode PX is arranged between the linear upper layer counter electrode CT2 formed in the same layer as the pixel electrode PX.

  On the other hand, the drain line DL extends to the formation region side of the thin film transistor TFT at a part of the intersection with the gate line GL, and this extended portion reaches the upper surface of the semiconductor layer AS to form the drain electrode DT of the thin film transistor TFT. is doing.

  Next, based on FIG. 16, the structure of the liquid crystal display device of this Embodiment 1 is demonstrated in detail. As shown in FIG. 16, in the first substrate SUB1 in the liquid crystal display device of Embodiment 5, the base film IN1 for protecting the thin film transistor TFT is formed on the upper layer of the glass substrate SUB1, and the gate electrode GT and the gate insulating film are formed on the upper layer. A thin film transistor TFT composed of the film GI, the semiconductor layer AS, the drain electrode DT, the source electrode ST, and the like is formed. In order to protect the thin film transistor TFT from an alkali component contained in a liquid crystal layer (not shown), a protective insulating film PASi is formed on the entire surface of the glass substrate SUB1 including the upper layer of the thin film transistor TFT. A planarizing film PASo is laminated on the protective insulating film PASi.

  The lower counter electrode CT1 formed in the upper layer of the planarizing film PASo is formed so as to avoid the contact hole TH1 in a region surrounded by a pair of adjacent gate lines GL and the common line CL, similarly to the conventional counter electrode. The common signal is commonly supplied to the pixels arranged in the extending direction of the gate lines GL (the arrangement direction of the drain lines DL). Similarly, the upper-layer counter electrode CT2 is formed so as to avoid the pixel electrode PX including the contact hole TH1, and is common to each pixel arranged in the extending direction of the gate line GL (the arrangement direction of the drain line DL). Is configured to supply.

  Further, in the region related to the display of the pixel PIX, the linear pixel electrode PX is arranged between the linear upper layer counter electrode CT2 formed in the same layer as the pixel electrode PX.

  Next, FIG. 17 is a process diagram showing an embodiment of a method for manufacturing a liquid crystal display device of Embodiment 5, and the manufacturing method will be described below in the order of steps based on FIG. Note that, as in Embodiments 1 to 4, thin film formation including electrode formation in each step can be performed by a known photolithography technique, and thus detailed description thereof is omitted.

Step 1. (Fig. 17 (a))
A base film IN1, a gate electrode GT, a gate insulating film GI, a semiconductor layer AS, a drain electrode DT, and a source electrode ST are formed on the surface of the glass substrate SUB1 on the liquid crystal LC side, and a thin film transistor TFT of an amorphous silicon TFT is formed. This step 1 is the same as step 1 in the first embodiment.

Step 2. (Fig. 17 (b))
In order to protect the thin film transistor TFT, a protective insulating film PASi made of a silicon nitride film, which is an inorganic material, is formed on the entire upper surface side (the liquid crystal LC side of the substrate) of the glass substrate SUB1 to form a protective film for the thin film transistor TFT. A flattening film PASo made of an acrylic film is formed on the upper surface side of the glass substrate SUB1 by a known spin coating method or the like on the upper layer of the protective insulating film PASi (the liquid crystal LC side of the substrate), and gate lines including thin film transistors TFT are formed. The unevenness on the upper surface of the glass substrate SUB1 accompanying the formation of the GL, the drain line DL, the common line CL, etc. is flattened. Next, the lower layer counter electrode CT1 is formed of ITO, which is a transparent electrode material, on the planarizing film PASo.

Step 3 (FIG. 17 (c))
Next, a coating type insulating film is formed and subjected to a baking process by a heat treatment of about 200 degrees to form a capacitive insulating film CI on the entire surface. Next, the contact hole TH3 reaching the lower counter electrode CT1 in the capacitive insulating film CI, the contact hole TH1 passing through the planarization layer PASo and the protective insulating film PASi and reaching the pad portion of the source electrode ST, and the planarization layer PASo and the protection A contact hole TH4 that penetrates the insulating film PASi and reaches the common line CL is formed.

Step 4. (Fig. 16)
Next, by forming a pixel electrode PX and an upper counter electrode CT2 using ITO as an electrode material on the upper layer of the capacitor insulating film CI, the pixel electrode PX electrically connected to the source electrode ST of the thin film transistor TFT and the common electrode An upper layer counter electrode CT2 electrically connected to the line CL is formed.

  As described above, in the fifth embodiment, the shape and positional relationship of the counter electrode (lower layer counter electrode CT1), the capacitor insulating film CI, and the pixel electrode PX formed on the upper surface side of the planarizing film PASo remain unchanged. Since the upper layer counter electrode CT2 having the same potential as the lower layer counter electrode CT1 is formed in the same layer, an inexpensive liquid crystal display device can be provided.

  Further, in the liquid crystal display device of the fifth embodiment, in the region related to the display of the pixel PIX, the linear pixel electrode PX is disposed between the linear upper layer counter electrode CT2 formed in the upper layer of the planarizing film PASo. Therefore, the capacitor insulating film CI is not interposed between the upper counter electrode CT2 and the pixel electrode PX. Therefore, the liquid crystal drive signal can be configured to be hardly affected by the fixed charge inside the capacitive insulating film or at the liquid crystal / capacitor insulating film interface, so that it is possible to provide a liquid crystal display device with greatly reduced flicker. .

  Further, since the step on the upper surface of the glass substrate SUB1 can be suppressed to the thickness of the ITO electrode, the rubbing failure of the alignment film can be effectively suppressed.

  In the liquid crystal display devices described in the first to fifth embodiments, the insulating substrate SUB1 is not limited to glass but may be other insulating substrates such as quartz glass and plastic. For example, if quartz glass is used, the process temperature can be increased, so that the gate insulating film can be densified and the reliability of the TFT is improved. If a plastic substrate is used, an image display device that is lightweight and excellent in impact resistance can be provided.

  Moreover, although the case where an ITO electrode was used as a transparent electrode was demonstrated, it is not limited to an ITO electrode, You may use a well-known ZnO type | system | group transparent electrode.

  Furthermore, in the liquid crystal display devices according to the first to fifth embodiments, the electrode formed in a planar shape is the counter electrode CT and the electrode formed in a comb-like shape is the pixel electrode PX. Alternatively, the thin film transistor TFT may be connected to the electrode formed in a planar shape to form the pixel electrode PX, and the common line CL may be connected to the electrode formed in a comb shape to form the counter electrode CT.

It is a pixel area sectional view for explaining the liquid crystal display device of Embodiment 1 of the present invention. It is a circuit diagram of the conventional liquid crystal display device. It is a top view of the liquid crystal display element for 1 pixel of the conventional liquid crystal display device. It is pixel area sectional drawing for demonstrating the conventional liquid crystal display device. It is a circuit diagram of the liquid crystal display device of Embodiment 1 of this invention. It is a top view of the liquid crystal display element for 1 pixel of the liquid crystal display device of Embodiment 1 of this invention. It is process drawing which shows a series of processes of one Embodiment of the manufacturing method of the liquid crystal display device of Embodiment 1 of this invention with FIG. It is process drawing which shows a series of processes of one Embodiment of the manufacturing method of the liquid crystal display device of Embodiment 1 of this invention with FIG. It is pixel area sectional drawing for demonstrating the liquid crystal display device of Embodiment 2 of this invention. It is process drawing which shows a series of processes of one Embodiment of the manufacturing method of the liquid crystal display device of Embodiment 2 of this invention with FIG. 9c-e. It is process drawing which shows a series of processes of one Embodiment of the manufacturing method of the liquid crystal display device of Embodiment 2 of this invention with FIG. 9a-b. It is a top view of the liquid crystal display element for 1 pixel of the liquid crystal display device of Embodiment 3 of this invention. It is pixel area sectional drawing for demonstrating the liquid crystal display device of Embodiment 3 of this invention. It is process drawing which shows a series of processes of one Embodiment of the manufacturing method of the liquid crystal display device of Embodiment 3 of this invention with FIG. It is process drawing which shows a series of processes of one Embodiment of the manufacturing method of the liquid crystal display device of Embodiment 3 of this invention with FIG. 12a-c. It is pixel area sectional drawing for demonstrating the liquid crystal display device of Embodiment 4 of this invention. It is process drawing which shows a series of processes of one Embodiment of the manufacturing method of the liquid crystal display device of Embodiment 4 of this invention with FIG. 14c-d. It is process drawing which shows a series of processes of one Embodiment of the manufacturing method of the liquid crystal display device of Embodiment 4 of this invention with FIG. 14a-b. It is a top view of the liquid crystal display element for 1 pixel of the liquid crystal display device of Embodiment 5 of this invention. It is pixel area sectional drawing for demonstrating the liquid crystal display device of Embodiment 5 of this invention. It is process drawing which shows one Embodiment of the manufacturing method of the liquid crystal display device of Embodiment 5 of this invention. It is a schematic block diagram of the liquid crystal display device of Embodiment 1 of this invention.

Explanation of symbols

GL ... Gate line, DL ... Drain line, CL ... Common line, PIX ... Pixel AR ... Liquid crystal display area, Clc ... Liquid crystal capacitor, Cst1 ... Retention capacitor Cst2 ...・ Insulating film capacitance, SCDv ... Gate driver,
SCDh ... drain driver, PX ... pixel electrode, CT ... counter electrode CT1 ... lower layer counter electrode, CT2 ... upper layer counter electrode, TFT ... thin film transistors TH1, TH2, TH3, TH4, ... Contact holes TF, TF1... Trench (groove), SUB1, SUB2... First substrate, glass substrate IN1 .. base film, GI... Gate insulating film, PASi. ··· Planarizing film, CI ··· Capacitance insulating film ·················································· .... Black matrix, LC ... Liquid crystal layer CF ... Color filter, ORI1, ORI2 ... Alignment film, PL ... Polarizing plate TI ... Trench insulation film

Claims (7)

A plurality of pixels arranged in a matrix, and a first substrate and a second substrate opposed to each other via a liquid crystal layer;
A first electrode formed in a planar shape at least in each pixel on the first substrate side;
A plurality of linear second electrodes formed on the first electrode over the first electrode and overlaid on the first electrode, the first electrode; A liquid crystal display device for driving the liquid crystal layer by an electric field generated by the second electrode,
A liquid crystal display device comprising: a linear third electrode having the same potential as the first electrode, formed in the same layer as the second electrode, and disposed between the second electrodes. . The liquid crystal display device according to claim 1.
A liquid crystal display device comprising a conductive layer in which the first electrode and the third electrode are integrally formed. The liquid crystal display device according to claim 1 or 2,
A liquid crystal display device, wherein a groove is formed in the planarization layer, and a part of the first electrode is formed in the groove. The liquid crystal display device according to claim 1 or 2,
A liquid crystal display device comprising: a second insulating layer formed on a planarizing layer; and a part of the first electrode formed in a groove formed in the second insulating layer. The liquid crystal display device according to claim 1.
The liquid crystal display device, wherein the first electrode and the third electrode are connected via a contact portion formed in the first insulating layer. The liquid crystal display device according to claim 1 or 5,
The liquid crystal display device, wherein the first insulating layer is formed of a capacitive insulating layer, and the second electrode and the third electrode are formed on the first insulating layer. The liquid crystal display device according to any one of claims 1 to 7,
A liquid crystal display, comprising: a thin film transistor that inputs display charges to the second electrode; and a contact portion connecting the source electrode of the thin film transistor and the second electrode is planarized by the first insulating layer. apparatus.

Images