JP2003216063A - Electrode substrate and planar display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that since the operation of an amplifier circuit becomes unstable in a planar display device having the small wiring capacity of a signal line, a line defect due to the shortage of the writing of video data occurs. <P>SOLUTION: This electrode substrate is constituted so that a wiring width in an area A where wirings 21, 22 of a memory power source intersect a signal line 11 becomes larger than a wiring width in an area B where the wirings 21, 22 do not intersect the signal line by making the wiring capacity of the area A wider than the wiring capacity of the area B. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrode substrate having a memory element in a pixel, and a flat panel display device including the electrode substrate.

[0002]

2. Description of the Related Art In recent years, flat panel display devices represented by liquid crystal display devices have become mainstream as displays for small information terminals such as mobile phones and electronic books by taking advantage of their light weight, thinness and low power consumption. Since these small information terminals are generally battery driven, low power consumption is an important issue. For example, a mobile phone is required to be able to display a still image with low power consumption during a standby period, and as a technique for realizing this, a liquid crystal display device having a memory element in a pixel (Japanese Patent Laid-Open No. 2001-2648).
No. 14, etc.) has been proposed. In such a liquid crystal display device having a memory element in the pixel, the pixel is driven by using the video data supplied from the outside in the normal display period, and the circuit for driving the memory element is stopped in this period.
In the still image display period (standby period), the pixels are driven using the still image data held in the memory element, and the operation of the peripheral drive circuit is stopped during this period, so that the power consumption in the still image display period is reduced. We are trying to reduce it.

[0003]

By the way, as a peripheral drive circuit for driving a pixel, there is a signal line drive circuit for supplying video data to the pixel. For example, a latch circuit, D
In the signal line drive circuit composed of the A / A conversion circuit and the amplifier circuit, the digital video data supplied from the outside is held in the latch circuit, the D / A conversion circuit converts the analog video data into the analog video data, and the amplifier circuit further outputs the current. After amplification, it outputs to the signal line. In such a signal line driving circuit, if the wiring capacitance of the signal line is small, the operation of the amplifier circuit becomes unstable, and the video data may not be written correctly within a predetermined writing time. In particular, when the screen size is small, such as in a mobile phone, the wiring capacity of the signal line is small, so the video data cannot be written correctly, and the pixels connected to that signal line become defective in display. Above, there is a problem that it is recognized as a line defect and the display quality is degraded.

An object of the present invention is to provide an electrode substrate and a flat panel display device capable of obtaining good display quality by reducing the occurrence of line defects due to insufficient writing of video data.

[0005]

In order to achieve the above object, the invention of claim 1 is such that a plurality of scanning lines and a plurality of signal lines arranged in a matrix on the main surface, and each grid of this matrix. A pixel switch element disposed in the pixel switch element, a pixel electrode provided in each of the grids connected to the signal line through the pixel switch element, and provided in each of the grids capable of holding video data to be written in the pixel electrode. A memory element, a memory power supply wiring for supplying a predetermined power supply voltage to the memory element, an auxiliary capacitance electrically connected in parallel with the pixel electrode, and an auxiliary capacitance power supply wiring for supplying a predetermined power supply voltage to the auxiliary capacitance. In the provided electrode substrate, a wiring width in a region where the memory power supply wiring intersects the signal line is wider than a wiring width in a region where the memory power supply wiring does not intersect the signal line.

According to a second aspect of the present invention, in the first aspect, the wiring width in the area where the auxiliary capacity power supply wiring intersects the signal line is narrower than the wiring width in the area where the auxiliary capacitance power supply wiring does not intersect the signal line. Characterize.

According to a third aspect of the present invention, in the first aspect, the wiring width in the region where the memory power supply wiring intersects the signal line is equal to the wiring width in the region where the auxiliary capacitance power supply wiring intersects the signal line. It is characterized by being wider than.

According to a fourth aspect of the present invention, in the first to third aspects, a scanning line driving circuit for supplying a scanning signal to the scanning line and a signal line driving circuit for supplying video data to the signal line are provided on the main surface. And is provided.

Further, in order to achieve the above-mentioned object, claim 5
In the invention, a plurality of scanning lines and a plurality of signal lines are arranged in a matrix on the main surface, a pixel switch element arranged for each lattice of this matrix, and the signal line via the pixel switch element. A pixel electrode provided for each grid to be connected, a memory element provided for each grid capable of holding video data to be written in the pixel electrode, a memory power supply line for supplying a predetermined power supply voltage to the memory element, An auxiliary capacitance electrically connected in parallel with the pixel electrode, an auxiliary capacitance power supply line for supplying a predetermined power supply voltage to the auxiliary capacitance, and a wiring width in a region where the memory power supply line intersects with the signal line are provided. An array substrate configured to be wider than a wiring width in a region that does not intersect with the signal line, a counter substrate including a counter electrode facing the pixel electrode on a main surface, and the two substrates Characterized in that it comprises a retained displayed layer.

According to a sixth aspect of the present invention, in the fifth aspect, the wiring width in a region where the auxiliary capacitance power supply wiring intersects the signal line is narrower than the wiring width in a region where the auxiliary capacitance power supply wiring does not intersect the signal line. Characterize.

According to a seventh aspect of the present invention, in the fifth aspect, the wiring width in the region where the memory power supply wiring intersects the signal line is equal to the wiring width in the region where the auxiliary capacitance power supply wiring intersects the signal line. It is characterized by being wider than.

According to an eighth aspect of the present invention, in any one of the fifth to seventh aspects, a scanning line drive circuit for supplying a scanning signal to the scanning line and a video data to the signal line are provided on the main surface of the array substrate. And a signal line driver circuit.

In a preferred form, the memory power supply wiring is composed of a first memory power supply wiring for supplying a high power supply voltage and a second memory power supply wiring for supplying a low power supply voltage, and these two power supply wirings are provided as described above. It is configured to be wired in parallel with the scanning line along with the auxiliary capacity power supply wiring.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment in which an electrode substrate and a flat panel display device according to the present invention are applied to a liquid crystal display device will be described below.

FIG. 2 is a schematic configuration diagram of the liquid crystal display device 100 according to this embodiment. Here, a drive circuit built-in type liquid crystal display device in which a pixel portion, a scanning line drive circuit, and a signal line drive circuit are integrally formed on an array substrate is taken as an example. However, the scanning line driving circuit and the signal line driving circuit may be arranged on an external substrate.

The pixel section 110 is composed of a plurality of signal lines 11 and a plurality of scanning lines 12 (only one line is shown in FIG. 2) wired on the array substrate 101, and the pixels 10. One end of each signal line 11 has a signal line drive circuit 1
30, and one end of each scanning line 12 is connected to the scanning line driving circuit 120. The pixel 10 is formed for each lattice of a matrix composed of the signal lines 11 and the scanning lines 12. Further, on the array substrate 101, auxiliary capacitance power supply wirings 19 and memory power supply wirings 21 and 22, which will be described later, are arranged in parallel with the scanning lines 12.

The pixel 10 is composed of a pixel switch element 13, a pixel electrode 14, a counter electrode 15, a liquid crystal layer 16, an auxiliary capacitance 17 and a memory element 18.

The source of the pixel switch element 13 is the signal line 1
1, the gate is connected to the scanning line 12, and the drain is connected to the pixel electrode 14, the auxiliary capacitor 17, and the memory element 18. ON / OFF of the pixel switch element 13 is controlled by a scan signal supplied to the scan line 12, and the signal line 11 and the pixel electrode 14 are electrically connected to each other when the pixel switch element 13 is turned on, so that the video data supplied to the signal line 11 is transferred to the pixel electrode. 14 (or memory element 18).

The counter electrode 15 facing the pixel electrode 14 is
It is formed on a counter substrate (not shown), and a predetermined counter voltage is supplied from a counter electrode driver circuit (not shown). A liquid crystal layer 16 is filled between the pixel electrode 14 and the counter electrode 15, and the periphery of the array substrate 101 and the counter substrate (not shown) are sealed by a seal material (not shown). Pixel electrode 1
The video data written in 4 is charged as a signal voltage between the pixel electrode 14 and the counter electrode 15, and the liquid crystal layer 16 responds to this to display a video in the pixel 10.

A predetermined auxiliary capacitance voltage is applied to the auxiliary capacitance 17 from the auxiliary capacitance driver circuit 140 through the auxiliary capacitance power supply line 19. In addition, the memory element 18 includes
From the memory element driver circuit 150 to the memory power supply wiring 21
Through the power supply voltage SVDD through the memory power supply wiring 22
The power supply voltage SVSS is respectively supplied through.
In this embodiment, the power supply voltage SVDD is a high power supply voltage and the power supply voltage SVSS is a low power supply voltage. For example, the power supply voltage SVDD is 5V and the power supply voltage SV is
A fixed potential of 0V is supplied to SS.

The scanning line driving circuit 120 is composed of a shift register, a level shifter and a buffer circuit (not shown), and each scanning line 12 is based on a clock signal / start signal supplied from an external control IC (not shown).
The scanning signal is output every predetermined period.

The signal line drive circuit 130 includes a latch circuit 131 for holding video data for one line for a predetermined time and a D / A for converting digital video data into analog video data.
It is composed of a conversion circuit 132 and an amplifier circuit 133 for current-amplifying the D / A converted video data. The signal line drive circuit 130 is supplied with a clock signal / start signal from an external control IC (not shown) and video data via a video bus (not shown). In the signal line drive circuit 130, by operating each of the circuits based on the clock signal / start signal supplied from the external control IC,
The video data for one line is output to the signal line 11 every predetermined period.

The liquid crystal display device 10 constructed as described above.
The operation of 0 will be briefly described. In the normal display period, the electrical connection between the memory element 18 and the pixel electrode 14 is cut off, and the video data supplied to the signal line 11 is supplied to the pixel switch element 1.
Display is performed by writing in the pixel electrode 14 through 3.
In the still image display period, the memory element 18 and the pixel electrode 1
4 is made conductive, and still image video data is written from the signal line 11 to the memory element 18 through the pixel switch element 13. After that, the operations of the scanning line driving circuit 120 and the signal line driving circuit 130 are stopped, and the still image video data held in the memory element 18 is written in the pixel electrode 14 to perform display.

FIG. 1 is a schematic plan view of the pixel 10, and the same parts as those in FIG. 2 are designated by the same reference numerals. However, since FIG. 2 described above illustrates the circuit configuration of the pixel 10 in an equivalent manner, the arrangement of each unit in FIG. 1 is not necessarily the same as that in FIG. Further, in FIG. 1, the pixel switch elements 13 and the scanning lines 12 are not shown.

In this embodiment, the memory power supply wiring 2
By setting the wiring width of the region A where the signal lines 1 and 22 intersect with the signal line 11 to be wider than the wiring width of the region B where the memory power supply lines 21 and 22 do not intersect with the signal line 11, the wiring capacitance in the region A becomes large. It is configured to be larger than the wiring capacitance at B.

With such a wiring structure, the wiring capacitance of each signal line 11 is increased, and the amplifier circuit 133 is provided.
Since the operation of (FIG. 2) can be stabilized, the video data can be correctly written within the writing time. FIG. 3 is a waveform diagram showing writing characteristics from the signal line 11 to the pixel electrode 14 when the wiring widths of the memory power supply wirings 21 and 22 are constant, and FIG.
FIG. 3 is a waveform diagram showing a writing characteristic from the signal line 11 to the pixel electrode 14 when the wiring structure shown in FIG. Figure 3
4, the vertical axis (V) represents the signal voltage of the video data written from the signal line 11 to the pixel electrode 14, and the horizontal axis (t) represents the time.

When the wiring widths of the memory power supply wirings 21 and 22 are constant, the operation of the amplifier circuit becomes unstable because the wiring capacity of the signal line 11 is small, and as shown in FIG. Can not be written correctly. On the other hand, when the memory power supply wirings 21 and 22 have the wiring structure as shown in FIG. 1, the wiring capacity of the signal line 11 becomes large and the operation of the amplifier circuit can be stabilized,
As shown in FIG. 4, the video data can be correctly written within the writing time. Therefore, according to the wiring structure of the present embodiment, it is possible to reduce the occurrence of line defects on the screen and obtain good display quality. Incidentally, according to the experiments by the present inventors, it is confirmed that the wiring capacitance per signal line is 7 pF to 10 pF on the screen of 2 inch size, and the video data can be written correctly.

Further, in the present embodiment, the wiring width of the region C where the auxiliary capacitance power supply wiring 19 intersects the signal line 11 is set as follows.
Area D where the auxiliary capacity power supply wiring 19 does not intersect with the signal line 11
The wiring capacitance in the area C is smaller than the wiring capacitance in the area D by making the wiring width narrower than the wiring width. Further, in the present embodiment, the wiring width of the area A where the memory power supply wirings 21 and 22 intersect the signal line 11 is made wider than the wiring width of the area C where the auxiliary capacitance power supply wiring 19 intersects the signal line 11. Thus, the wiring capacitance in the area A is larger than the wiring capacitance in the area C. That is, in order to drive the liquid crystal in an alternating current, the common inversion drive (the pixel electrode 14 and the counter electrode 15 at a predetermined cycle is
(The voltage level of (1) is inverted), the auxiliary capacitance power supply wiring 19 is driven with an amplitude of 3V to 5V, for example. At this time, the signal line 11 and the auxiliary capacity power supply line 19
If the wiring capacitance formed between the counter electrode 15 and
It takes time to switch the voltage level of from low to high and from high to low, which causes a lateral stroke. However, by adopting the wiring structure as in the present embodiment, it becomes possible to smoothly switch the voltage level of the counter electrode 15, reduce the occurrence of lateral stroke, and obtain good display quality. You can

In the above embodiment, the wiring width of the two memory power supply wirings 21 and 22 intersects with the signal line 11 is widened. However, one of the memory power supply wirings 21 and 22 is arranged. The wiring width may be increased. Further, in the configuration in which the wiring width of the region where the auxiliary capacitance power supply wiring 19 intersects with the signal line 11 is narrowed, the position where the wiring width is narrowed is not limited to the example of FIG. It can be changed.

In the above embodiment, an example in which the present invention is applied to a liquid crystal display device has been described, but the display layer, which is one of the constituent features of the flat panel display device according to the present invention, is limited to the liquid crystal layer. It can be replaced by another substance rather than one.

[0031]

As described above, according to the present invention,
Since the wiring capacity of the signal line can be increased, occurrence of line defects due to insufficient writing of video data can be reduced, and good display quality can be obtained.

[Brief description of drawings]

FIG. 1 is a schematic plan view of the pixel shown in FIG.

FIG. 2 is a schematic configuration diagram of a liquid crystal display device according to the present embodiment.

FIG. 3 is a waveform diagram showing writing characteristics from the signal line to the pixel electrode when the wiring width of the memory power supply wiring is constant.

FIG. 4 is a waveform diagram showing writing characteristics from a signal line to a pixel electrode when the memory power supply wiring has a wiring structure as shown in FIG.

[Explanation of symbols]

10 ... Pixel, 11 ... Signal line, 12 ... Scan line, 13 ... Pixel switch element, 14 ... Pixel electrode, 15 ... Counter electrode, 16
... liquid crystal layer, 17 ... auxiliary capacitance, 18 ... memory element, 19 ...
Auxiliary capacity power supply wiring 21, 22 ... Memory power supply wiring, 10
0 ... Liquid crystal display device, 101 ... Array substrate, 110 ... Pixel part, 120 ... Scan line drive circuit, 130 ... Signal line drive circuit, 140 ... Auxiliary capacitance driver circuit, 150 ... Memory element driver circuit

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 2H092 GA40 GA61 JA24 JB25 JB34                       JB69 NA01 NA26 PA06                 5C094 AA02 AA09 AA53 BA03 BA09                       BA43 CA19 DA09 DA13 EA05                       FA04                 5F033 GG04 MM21 NN21 VV10 VV15

Claims (8)

[Claims] 1. A plurality of scanning lines and a plurality of signal lines arranged in a matrix on the main surface, a pixel switch element arranged for each lattice of this matrix, and the signal line via the pixel switch element. A pixel electrode provided for each of the grids connected to the memory element, a memory element provided for each of the grids capable of holding video data to be written in the pixel electrode, and a memory power supply line for supplying a predetermined power supply voltage to the memory element ,
In an electrode substrate provided with an auxiliary capacitor electrically connected in parallel with the pixel electrode and an auxiliary capacitor power supply line supplying a predetermined power supply voltage to the auxiliary capacitor, in a region where the memory power supply line intersects with the signal line. The electrode substrate is characterized in that the wiring width thereof is wider than the wiring width in a region which does not intersect with the signal line. 2. The electrode according to claim 1, wherein a wiring width in a region where the auxiliary capacitance power supply wiring intersects with the signal line is narrower than a wiring width in a region where the auxiliary capacitance power supply wiring does not intersect with the signal line. substrate. 3. The wiring width in a region where the memory power supply wiring intersects with the signal line is wider than the wiring width in a region where the auxiliary capacity power supply wiring intersects with the signal line. 1. The electrode substrate according to 1. 4. The scanning line drive circuit for supplying a scanning signal to the scanning line and the signal line drive circuit for supplying video data to the signal line are provided on the main surface. The electrode substrate according to item 3. 5. A plurality of scanning lines and a plurality of signal lines arranged in a matrix on the main surface, a pixel switch element arranged for each lattice of this matrix, and the signal line through the pixel switch element. A pixel electrode provided for each of the grids connected to the memory element, a memory element provided for each of the grids capable of holding video data to be written in the pixel electrode, and a memory power supply line for supplying a predetermined power supply voltage to the memory element ,
An auxiliary capacitance electrically connected in parallel with the pixel electrode, an auxiliary capacitance power supply line for supplying a predetermined power supply voltage to the auxiliary capacitance, and a wiring width in a region where the memory power supply line intersects with the signal line are provided. An array substrate configured to be wider than a wiring width in a region that does not intersect with the signal line, a counter substrate including a counter electrode facing the pixel electrode on the main surface, and between the two substrates. A flat display device comprising: a retained display layer. 6. The plane according to claim 5, wherein a wiring width in a region where the auxiliary capacity power supply wiring intersects with the signal line is narrower than a wiring width in a region where the auxiliary capacitance power supply wiring does not intersect with the signal line. Display device. 7. The wiring width in a region where the memory power supply wiring intersects with the signal line is wider than the wiring width in a region where the auxiliary capacity power supply wiring intersects with the signal line. The flat panel display device according to item 5. 8. A scan line drive circuit for supplying a scan signal to the scan line and a signal line drive circuit for supplying video data to the signal line are provided on the main surface of the array substrate. The flat panel display device according to claim 5.