JP2004354741A - Liquid crystal display device and its driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent display unevenness due to unsettled storage contents of a digital memory in switching from normal display to still picture display. <P>SOLUTION: When normal electric power is supplied to the digital memory 18 to switch the normal display to the still picture display, the potential of a counter electrode 15, the potential of an auxiliary capacitor 20, and plus-side electric power and minus-side electric power of inverter elements 23 and 24 are held at high level and then the potential of a memory control line 19a is held at high level to electrically connect a pixel electrode 13 and the digital memory 18 to each other; and the potential of the counter electrode 15, the potential of the auxiliary capacitor 20, and the plus-side electric power and minus-side electric power of the inverter elements 23 and 24 are held at low level and then only the plus-side electric power is held at high level. Thus, a time difference is provided between the timing where the minus-side electric power of the inverter elements 23 and 24 are held at the low level and the timing where the plus-side electric power is held at the high level. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a liquid crystal display device having a digital memory for each pixel and a driving method thereof.
[0002]
[Prior art]
In recent years, liquid crystal display devices have been used for small information terminals such as mobile phones and electronic books, taking advantage of the advantages of light weight, thinness, and low power consumption. Since such a small information terminal is generally driven by a battery, low power consumption is an important issue.
[0003]
In particular, mobile phones are required to be able to display with low power consumption during standby time. As a technique for realizing this, a digital memory is provided for each pixel, and when displaying a still image, the still image data stored in the digital memory is read out and displayed, and the operation of the peripheral driving circuit is controlled. There is one in which the power consumption is greatly reduced by stopping the operation (see Patent Document 1).
[0004]
[Patent Document]
JP 2001-264814 A
[Problems to be solved by the invention]
However, in this liquid crystal display device, the digital memory acts as a parasitic capacitance at the time of normal display for displaying a moving image. Therefore, the display quality when reading and displaying still image data from the digital memory at the time of still image display is displayed. Cause deterioration. In order to prevent such a deterioration in display quality, the power supply to the digital memory is inverted in a short period with the same polarity as the counter electrode during the normal display period so that the digital memory maintains the reset state. It is conceivable to improve the display quality.
[0006]
However, in this case, when the normal power is turned on to the digital memory when switching from the normal display to the still image display, the stored content of the digital memory becomes indeterminate because it has been in the reset state, and display unevenness is instantaneously generated. This can cause it to occur.
[0007]
The present invention has been made in view of the above, and an object of the present invention is to prevent the occurrence of display unevenness due to indefinite data stored in a digital memory when switching from normal display to still image display. An object of the present invention is to provide a liquid crystal display device and a driving method thereof.
[0008]
[Means for Solving the Problems]
A liquid crystal display device according to a first aspect of the present invention includes a digital memory having at least two inverter elements for each pixel, an array substrate having a pixel electrode and an auxiliary capacitor, and a counter substrate having a counter electrode facing the pixel electrode. The substrate, the liquid crystal layer held between the array substrate and the opposing substrate, and in a normal display, the positive power supply and the negative power supply of each inverter element are inverted and driven with the same polarity as the potential of the counter electrode and the potential of the auxiliary capacitor. When the normal power is turned on to the digital memory when switching from the normal display to the still image display, the potential of the counter electrode, the potential of the auxiliary capacitor, the positive power supply and the negative power supply of each inverter element are set to the high level, After the pixel electrode and the digital memory are electrically connected, the potential of the counter electrode, the potential of the auxiliary capacitor, the positive power supply and the negative power supply of each inverter element are set to low level, and then each inverter is turned on. Characterized in that it has control means for the positive-side power device to a high level, the.
[0009]
A driving method of a liquid crystal display device according to a second aspect of the present invention includes a digital memory having at least two inverter elements for each pixel, an array substrate having a pixel electrode and an auxiliary capacitor, and a counter electrode facing the pixel electrode. In a normal display, a positive power supply and a negative power supply of each inverter element are connected to a potential of a counter electrode with respect to a liquid crystal display device having a liquid crystal layer held between an array substrate and a counter substrate. When the normal power is supplied to the digital memory at the time of switching from the normal display to the still image display, the potential of the counter electrode, the potential of the storage capacitor, and the positive The side power supply and the negative power supply are set to the high level to conduct electricity between the pixel electrode and the digital memory, and the potential of the counter electrode, the potential of the auxiliary capacitor, the positive power supply and the negative power supply of each inverter element. The characterized in that it after the low level to the high level positive side power of each inverter element.
[0010]
In the first and second aspects of the present invention, in the normal display, the positive power supply and the negative power supply of each inverter element in the digital memory are inverted and driven with the same polarity as the potential of the auxiliary capacitor and the potential of the common electrode. In order to prevent the digital memory from acting as a parasitic capacitance and to switch the normal power supply to the digital memory when switching from the normal display to the still image display, the timing of setting the negative power supply of each inverter element to low level and the positive side By providing a time difference in the timing when the power supply is set to the high level, the contents stored in the digital memory are prevented from becoming unstable.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment in which the present invention is applied to an active matrix type liquid crystal display device will be described with reference to the drawings.
[0012]
As shown in the circuit diagram of FIG. 1, a liquid crystal display device 100 according to the present embodiment has a display unit 110 in which a plurality of pixels 10 are formed, and a scan that drives a scan line 12 for transmitting a scan signal to each pixel. The configuration includes a line drive circuit 120, a signal line drive circuit 130 for driving the signal line 11 for transmitting video data to each pixel, and a control circuit 140 for controlling the operation of each circuit.
[0013]
As shown in the cross-sectional view of FIG. 2, in the liquid crystal display device 100, the array substrate 101 and the counter substrate 102 are arranged to face each other with the liquid crystal layer 16 interposed therebetween, and the periphery of the liquid crystal layer 16 is sealed with a sealant 103. . The display unit 110, the scanning line driving circuit 120, and the signal line driving circuit 130 are integrally formed on the array substrate 101, and the counter electrode 15 electrically facing the pixel electrode 13 in the display unit 110 is formed on the counter substrate 102. You. In FIG. 2, illustration of an alignment film, a polarizing plate, and the like is omitted.
[0014]
In the display unit 110, a plurality of signal lines 11 and a plurality of scanning lines 12 intersecting the signal lines 11 are arranged in a matrix on the array substrate 101, and the pixels 10 are formed for each matrix of the matrix.
[0015]
The scanning line driving circuit 120 includes a shift register 121 and a buffer circuit (not shown). The scanning line driving circuit 120 controls one scanning line 12 based on a vertical clock signal and a vertical start signal supplied from the control circuit 140 as control signals. A scanning signal is output every horizontal scanning period. When the scanning line 12 is set to a high level by this scanning signal, all the switching elements 14 connected to the scanning line 12 are turned on. The scanning line drive circuit 120 sets the potentials of the scanning lines 12 to the high level sequentially from the top during normal display for displaying a moving image, and sets the potentials of all the scanning lines 12 to the low level when displaying a still image. I do.
[0016]
The signal line driving circuit 130 includes a shift register 131, an analog switch 132, and the like. A horizontal clock signal and a horizontal start signal are supplied as control signals from the control circuit 140, and video data is supplied through the video bus 133. Is done. The signal line drive circuit 130 supplies an on / off signal to the analog switch 132 based on the horizontal clock signal and the horizontal start signal, thereby sampling video data from the video bus 133 and outputting the sampled data to the signal line 11.
[0017]
As shown in the circuit diagram of FIG. 3, the pixel 10 has a pixel electrode 13 to which video data is written, a switch element 14 for controlling writing of video data to the pixel electrode 13, and a pixel electrode 13 opposed to the pixel electrode 13 with a liquid crystal layer 16 interposed therebetween. And a digital memory 18 for storing still image data, a switch circuit 17 for controlling writing and reading of still image data to and from the digital memory 18, and an auxiliary capacitor 20. The pixel electrode 13 is connected to a digital memory 18 via a switch circuit 17. A voltage is supplied to the counter electrode 15 and the auxiliary capacitance 20 under the control of the control circuit 140.
[0018]
The switch element 14 is composed of a CMOS transistor, and its source is connected to the signal line 11, its gate is connected to the scanning line 12, and its drain is connected to one terminal of the pixel electrode 13 and one of the auxiliary capacitors 20. A storage capacitor line (not shown) is connected to the other terminal of the storage capacitor 20, and a voltage is supplied through the storage capacitor line.
[0019]
The switch circuit 17 includes two switch elements 21 and 22 formed of CMOS transistors. The gate of the switch element 21 is connected to the memory control line 19a, the source is connected to the pixel electrode 13, and the drain is connected to the output terminal 27 of the digital memory 18. The gate of the switch element 22 is connected to the memory control line 19b, the source is connected to the pixel electrode 13, and the drain is connected to the inverted output terminal 28 of the digital memory 18. The scanning line drive circuit 120 separately supplies a memory control signal to these memory control lines 19a and 19b in accordance with an instruction from the control circuit 140, thereby independently controlling the switch elements 21 and 22.
[0020]
The digital memory 18 includes two inverter elements 23 and 24 and a switch element 25. An output terminal of the inverter element 23 is connected to an input terminal and an inverted output terminal 28 of the inverter element 24 so that a loop is formed by the inverter elements 23 and 24, and an output terminal of the inverter element 24 is connected via the switch element 25 to the inverter element. 23 are connected to an input terminal and an output terminal 27. The switch element 25 is formed of a CMOS transistor having a channel opposite to that of the switch element 14, and the gate of the switch element 25 is connected to the scanning line 12 similarly to the gate of the switch element 14. The switching element 14 and the switching element 25 are controlled by the scanning signal supplied to the scanning line 12 so that the on / off of the switching element 14 is reversed. That is, when the switch element 14 is turned on, the switch element 25 is turned off, and when the switch element 14 is turned off, the switch element 25 is turned on.
[0021]
As shown in the circuit diagram of FIG. 4, the inverter element 24 includes switch elements 31 and 32 connected in series. The switch element 31 has an inverted channel structure. The switch element 31 is supplied with positive power via a positive power supply line 33a, and the switch element 32 is supplied with negative power via a negative power supply line 33b. The supply of each power is controlled by the control circuit 140. The inverter element 23 has basically the same configuration.
[0022]
Next, the operation of the liquid crystal display device 100 configured as described above will be described with reference to a timing chart shown in FIG.
[0023]
First, in the normal display period, the potentials of the memory control lines 19a and 19b are set to a low level to turn off both the switch elements 21 and 22, and the pixel electrode 13 and the digital memory 18 are turned off. Then, the switch element 14 is turned on for a predetermined period, and the moving image data supplied from the signal line 11 is written to the pixel electrode 13 so that a full-color moving image is displayed.
[0024]
Specifically, the control circuit 140 supplies a vertical clock signal and a vertical start signal to the scanning line driving circuit 120, and supplies a horizontal clock signal, a horizontal start signal and moving image data to the signal line driving circuit 130. I do. The scanning line driving circuit 120 outputs a memory control signal based on the vertical clock signal and the vertical start signal to set the potentials of the memory control lines 19a and 19b to a low level, and outputs a scanning signal to cause each scanning line 12 to output. The high level is sequentially set for each horizontal scanning period. All the switch elements 14 connected to the scanning line 12 which has become the high level are turned on. In synchronization with this, the signal line drive circuit 130 samples the moving image data, outputs the sampled data to the signal line 11, and writes the moving image data to the pixel electrode 13 through the switch element 14. The moving image data is charged between the pixel electrode 13 and the auxiliary capacitor 20 and the counter electrode 15, and the liquid crystal layer 16 responds according to the magnitude of the writing voltage to control the amount of transmitted light from each pixel 10. By performing such a writing operation for all the scanning lines 12 within one frame period, an image for one screen is displayed.
[0025]
In the normal display period, the control unit 140 sets the potential of the positive power supply line 33a (positive power supply) and the potential of the negative power supply line 33b (negative power supply) in the inverter elements 23 and 24 to the counter electrode. Inversion is performed in a short cycle so as to have the same polarity as the potential of the storage capacitor 15 and the potential of the storage capacitor 20. This prevents the digital memory 18 from resetting and acting as a parasitic capacitance.
[0026]
When switching from the normal display to the still image display, the control unit 140 sets the potential of the counter electrode 15, the potential of the auxiliary capacitor 20, and the positive side of each of the inverter elements 23 and 24 during the vertical blanking period after the normal display. The power supply and the negative power supply are set to high level. After a certain period of time, the potential of the memory control line 19a is set to the high level, and at the same time, the potential of the counter electrode 15, the potential of the auxiliary capacitor 20, the positive power supply and the negative power supply of each of the inverter elements 23 and 24 are set to the low level. I do. When the potential of the memory control line 19a becomes high level, the pixel electrode 13 and the digital memory 18 are brought into a conductive state. When the potential of the negative power supply line 33b becomes low level, normal power for causing the inverter elements 23 and 24 to function as a memory is supplied to the negative power supply line 33b. Thereafter, the potential of the positive power supply line 33a is set to a high level. As a result, regular power is supplied to the positive power supply line 33a. As described above, by providing a time difference between the timing when the negative power supply of each of the inverter elements 23 and 24 is set to the low level and the timing when the positive power supply is set to the high level, the storage contents of the digital memory 18 can be prevented from becoming indefinite. I do. Then, in the last one frame (still image writing frame) at the time of shifting from the normal display to the still image display, the still image data is written to the digital memory 18 through the switch elements 14 and 21.
[0027]
In the still image display period, the switch element 14 is turned off and the switch element 25 is turned on by setting the potential of the scanning line 12 to a low level. Thereby, the signal line 11 and the pixel electrode 13 are made non-conductive, and the inverter elements 23 and 24 are connected in a loop. The voltages at the output terminals of the inverter elements 23 and 24 are held in this loop circuit.
[0028]
At the start of the still image display, the potential of the memory control line 19a is set to the low level, the potential of the memory control line 19b is set to the high level, the switch element 21 is turned off, and the switch element 22 is turned on. As a result, the still image data stored in the digital memory 18 is written to the pixel electrode 13 through the inverted output terminal 28 and the switch element 22. In the still image display period, power consumption is reduced by stopping the operation of peripheral circuits such as the scanning line driving circuit 120 and the signal line driving circuit 130.
[0029]
In the still image display period, the still image data written to the pixel electrode 13 can be held in this state for a short time, but if held for a long time, the DC component deteriorates the liquid crystal layer 16. 16 needs to be AC-driven. In the present embodiment, the switch elements 21 and 22 are alternately turned on by alternately setting the potentials of the memory control lines 19a and 19b to a high level in one frame cycle, and are stored in the digital memory 18. The alternating-current drive is realized by alternately extracting the still image data from the output terminal 27 or the inverted output terminal 28 and writing the still image data to the pixel electrode 13 and inverting the potential of the counter electrode 15 and the potential of the auxiliary capacitor 20 in accordance with this cycle. I do.
[0030]
That is, by turning on the switch element 21 and the switch element 22 alternately, the still image data is alternately output to the pixel electrode 13 at the positive potential or the negative potential. Are alternately inverted, so that no voltage is applied to the liquid crystal layer 16 in the pixel 10 in which the counter electrode 15 and the pixel electrode 13 have the same polarity, and a voltage is applied to the liquid crystal layer 16 in the pixel 10 of the opposite polarity. , Multi-color display by black display or white display can be performed.
[0031]
Subsequently, a comparative example prepared for comparison with the liquid crystal display device 100 of the present embodiment will be described. Since the basic configuration of the comparative example is the same as that of the present liquid crystal display device, a duplicate description will be omitted, and only the operation timing of the pixel, which is the difference, will be described.
[0032]
As shown in the timing chart of FIG. 6, in the comparative example, in the vertical blanking period after the normal display, the potential of the positive power supply line 33a of each of the inverter elements 23 and 24 reverses from the inversion drive in the normal display and becomes high. Switch to level and maintain this level. On the other hand, the potential of the negative power supply line 33b of the inverter elements 23 and 24 is changed from the inversion drive in the normal display to the low level, and is maintained at this level. Similarly to the present liquid crystal display device 100, the digital memory 18 is in the reset state in the normal display up to that time, and when the normal power is turned on when the digital memory 18 is switched from the normal display to the still image display, the normal state is displayed. Since the timing at which the potential of the side power supply line 33a becomes high level and the timing at which the potential of the negative power supply line 33b becomes low level are simultaneous, the contents stored in the digital memory 18 are undefined.
[0033]
Therefore, according to the present embodiment, when switching from the normal display to the still image display, when the normal power is supplied to the digital memory 18, the potential of the counter electrode 15, the potential of the auxiliary capacitor 20, , And 24, the potential of the memory control line 19 a is set to the high level to make the pixel electrode 13 and the digital memory 18 conductive, and the potential of the counter electrode 15 and the potential of the auxiliary capacitor 20 are changed. The potential, the positive power supply and the negative power supply of each of the inverter elements 23 and 24 are set to low level, and then only the positive power supply is set to high level. As described above, by providing a time difference between the timing when the negative power supply of each of the inverter elements 23 and 24 is set to the low level and the timing when the positive power supply is set to the high level, the storage contents of the digital memory 18 do not become unstable. In addition, it is possible to prevent the occurrence of display unevenness.
[0034]
【The invention's effect】
As described above, according to the liquid crystal display device and the driving method thereof according to the present invention, when switching from the normal display to the still image display, it is possible to prevent the occurrence of display unevenness due to indefinite storage contents of the digital memory. be able to.
[Brief description of the drawings]
FIG. 1 is a circuit diagram illustrating a configuration of a liquid crystal display device according to an embodiment.
FIG. 2 is a cross-sectional view schematically showing a cross-sectional configuration of the liquid crystal display device.
FIG. 3 is a circuit diagram showing a configuration of one pixel in the liquid crystal display device.
FIG. 4 is a circuit diagram showing a configuration of an inverter element used for a digital memory in the pixel.
FIG. 5 is a timing chart showing the operation of the pixel.
FIG. 6 is a timing chart illustrating an operation of a pixel in a comparative example.
[Explanation of symbols]
Reference Signs List 10 pixel, 11 signal line, 12 scanning line 13 pixel electrode, 14 switch element 15 counter electrode, 16 liquid crystal layer 17 switch circuit, 18 digital memories 19a and 19b memory control line 20 auxiliary Capacitors 21 and 22 Switch elements 23 and 24 Inverter elements 25 Switch elements 27 Output terminals 28 and inverted output terminals 31 and 32 Switch elements 33a and 33b Memory power supply line 100 Liquid crystal display device 101 Array Substrate 102: Counter substrate, 110: Display unit 120: Scan line drive circuit 130: Signal line drive circuit, 140: Control circuit

Claims (2)

An array substrate including a digital memory having at least two inverter elements for each pixel, a pixel electrode, and an auxiliary capacitor;
A counter substrate having a counter electrode facing the pixel electrode,
A liquid crystal layer held between an array substrate and a counter substrate,
In the normal display, the positive power supply and the negative power supply of each inverter element are driven to be inverted with the same polarity as the potential of the counter electrode and the potential of the auxiliary capacitance, and the normal power supply is supplied to the digital memory when switching from the normal display to the still image display. When turned on, the potential of the counter electrode, the potential of the storage capacitor, the positive power supply and the negative power supply of each inverter element are set to the high level, the pixel electrode and the digital memory are electrically connected, the potential of the counter electrode, the potential of the storage capacitor. Control means for setting the positive power supply and the negative power supply of each inverter element to low level, and then setting the positive power supply of each inverter element to high level,
A liquid crystal display device comprising: An array substrate including a digital memory having at least two inverter elements for each pixel, a pixel electrode, and an auxiliary capacitor;
A counter substrate having a counter electrode facing the pixel electrode,
For a liquid crystal display device having a liquid crystal layer held between an array substrate and a counter substrate,
In the normal display, the positive power supply and the negative power supply of each inverter element are driven to be inverted with the same polarity as the potential of the counter electrode and the potential of the auxiliary capacitor, and the normal power supply is supplied to the digital memory when switching from the normal display to the still image display. When turned on, the potential of the counter electrode, the potential of the storage capacitor, the positive power supply and the negative power supply of each inverter element are set to the high level, the pixel electrode and the digital memory are electrically connected, the potential of the counter electrode, the potential of the storage capacitor. A method of driving the liquid crystal display device, wherein the positive power supply and the negative power supply of each inverter element are set to low level, and then the positive power supply of each inverter element is set to high level.

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