JP2005136942A - Drive circuit for field controlled semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a drive circuit of a simple circuit configuration that accelerates turn-off by reliably applying inverse bias to FET and IGBT and simultaneously reduces a power loss caused by the excitation energy of a pulse transformer. <P>SOLUTION: The drive circuit is provided with: an inverse bias capacitor of which one terminal is connected to the collector of a transistor that is turned on when an FET is turned off and the other terminal is connected to a terminal of the secondary winding of a pulse transformer and the source of the FET; and a diode that is connected between the base and emitter of the transistor. The circuit charges the capacitor with the excitation energy of the pulse transformer when the FET is turned off, and imparts an inverse bias voltage to the FET by using the voltage of the capacitor. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

The present invention relates to a drive circuit for an electric field control type semiconductor switch such as a MOSFET or IGBT, and more particularly to a drive circuit capable of turning off an electric field control type semiconductor switch at high speed by applying a reverse bias with a simple configuration.

  An FET is a voltage-driven semiconductor device that is driven by applying a voltage to the gate, that is, an electric field control type semiconductor device. Essentially, it is not necessary to pass a current through the gate, but a considerably large capacitance between the gate and the source. Therefore, a current for charging the capacitance flows during on-drive, and it is necessary to discharge the charge of the capacitance during off-drive. Therefore, in order to drive such an electric field control type semiconductor device at a high speed, particularly at a high speed, a reverse bias voltage is applied between the gate and the source at the time of off driving, and the static voltage between the gate and the source is as short as possible. The electric charge of the capacitance must be discharged.

  A drive circuit as shown in FIG. 12 has been proposed as a conventional example for driving an electric field control type semiconductor element such as an FET or IGBT at high speed (see, for example, Patent Document 1). This drive circuit includes a control power supply 41, a control semiconductor switch 42 such as an FET connected in series to the control power supply 41, a reset circuit 43 formed by connecting a diode and a Zener diode in series in the reverse direction, and a primary winding. A pulse transformer 44 having N1 and a secondary winding N2, a rectifying diode 45, a forward bias diode 46, and an electric field control type semiconductor element (hereinafter referred to as FET) 20 that is turned on and off is turned off when it is on. Thus, the transistor 47 which is turned on at the time of off driving, the resistor 48 connected between its base and emitter, the reverse bias capacitor 49 for applying a reverse bias to the FET 20, and the charging circuit for charging the reverse bias capacitor 49 50, a high frequency source 51, an insulating transformer 52, a diode 53, a constant voltage diode 54, and Consisting of a bypass circuit 55.

  Here, the bypass circuit 55 applies a steep current directly to the source of the FET 20 through the drain-gate capacitance C2 of the FET 20 when a short rise time (dv / dt) is applied between the drain and source of the FET 20. By flowing, the gate and the source of the FET 20 are bypassed to prevent the FET 20 from conducting erroneously. The bias circuit 55 includes a diode 56, a capacitor 57, and a resistor 58.

  Next, the operation of this drive circuit will be described. When the FET 20 is turned on, the control semiconductor switch 42 is turned on. When the control semiconductor switch 42 is turned on, a positive voltage is generated on the black dot side indicating the polarity of the secondary winding N2 of the pulse transformer 44, and this positive voltage is applied to the gate electrode of the FET 20 through the diodes 45 and 46. Then, a current flows through the gate-source capacitance C1 of the FET 20 and charges it with the polarity shown in the figure, and the FET 20 is turned on. At this time, the transistor 47 is turned off because it is reverse-biased by the voltage drop of the biasing diode 46. During this period, the charging circuit 50 charges the reverse bias capacitor 49 with the illustrated polarity. The charging voltage of the reverse bias capacitor 49 is limited by the constant voltage diode 54.

  Next, when the FET 20 is driven off, the control semiconductor switch 42 is turned off. As the control semiconductor switch 42 is turned off, the black dot side indicating the polarity of the secondary winding N2 of the pulse transformer 44 becomes negative. At this time, the transistor 47 is forward-biased and turned on by the charge voltage of the reverse bias capacitor 49 and the voltage of the gate-source capacitance C1 of the FET 20, and the FET 20 is surely turned on by the voltage of the reverse bias capacitor 49. Reverse biased. As a result, the charge of the gate-source capacitance C1 is rapidly discharged through the transistor 47, so that the FET 20 is turned off at high speed.

  When the control semiconductor switch 42 is on, a voltage of the control power supply 41, for example, 15V is applied to the primary winding N1 of the pulse transformer 44, and an exciting current flows through the primary winding N1. The excitation energy by the excitation current is magnetically saturated at the core of the pulse transformer 44 unless the control semiconductor switch 42 is turned off to the initial value, generally zero, after the control semiconductor switch 42 is turned off. To consume and return to zero. The so-called pulse transformer 44 is reset. In this circuit, due to the blocking action of the diode 45, no reset current flows on the secondary winding N2 side.

Therefore, this conventional drive circuit can reliably reverse-bias voltage-driven semiconductor elements such as FETs and IGBTs and turn them off at high speed. Although it has the effect of not causing the voltage-driven semiconductor element to malfunction even when applied with a steep rising voltage, all of the excitation energy due to the excitation current of the pulse transformer is lost, resulting in large power loss and circuit configuration. Is complicated and uneconomical.
JP-A-7-283707

The present invention simplifies the circuit configuration of a drive circuit that reliably gives a reverse bias to voltage-driven semiconductor elements such as FETs and IGBTs and achieves high turn-off speed, and at the same time, the excitation energy of a pulse transformer is reduced. The problem is how to reduce power loss effectively.

  According to a first aspect of the present invention, a control power source, a primary winding connected in series to the control power source, and the primary winding are magnetically coupled, and one terminal is connected to the source of the electric field control type semiconductor element. A pulse transformer having a secondary winding, a control semiconductor switch connected in series to the control power source and the primary winding, the other terminal of the secondary winding, and an electric field control type semiconductor element A first diode connected in series between the gate of the transistor, a transistor having a base and an emitter connected to the anode and cathode of the first diode, and one end connected to the collector of the transistor, respectively. A capacitor having the other end connected to the one terminal of the secondary winding, and an excitation current flowing through the secondary winding of the pulse transformer when the control semiconductor switch is turned off. Thus by charging the capacitor, there is provided a driving circuit of the electric field control type semiconductor device characterized by reverse biasing the gate-source of the field-controlled semiconductor device at the charging voltage of the capacitor.

  According to a second aspect of the invention, in the first aspect of the invention, the second diode is connected in parallel between the collector and base of the transistor from the collector toward the base. Provide a circuit.

  A third invention provides a driving circuit for an electric field control type semiconductor device according to the second invention, wherein the second diode is a Schottky barrier diode.

  A fourth invention provides a drive circuit for an electric field control type semiconductor device according to the first invention, wherein a resistor is connected in parallel between the collector and base of the transistor.

  A fifth invention is characterized in that, in the first invention, a third diode is connected in parallel with the capacitor so that a cathode is connected to one terminal of the secondary winding. A drive circuit for an electric field control type semiconductor device is provided.

  In a sixth aspect based on the first aspect, the secondary winding comprises two first and second secondary windings connected in series, and the first and second secondary windings are connected to the collector of the transistor. A drive circuit for an electric field control type semiconductor device, characterized in that a fourth diode is connected toward a series connection point with two secondary windings.

  According to a seventh invention, in any one of the first to sixth inventions, there is provided a switch element for preventing the electric charge charged in the capacitor from being discharged to the secondary winding of the pulse transformer. The switching element is connected in series between the capacitor and the secondary winding, and the switching element is turned on / off together with the on / off of the electric field control type semiconductor element, and when the switching part is turned off. And a diode section that charges the capacitor by charging the excitation energy of the pulse transformer as a reset current.

  According to an eighth aspect of the present invention, in the seventh aspect, the diode section is provided in antiparallel with the switching section or is separately connected in reverse parallel. I will provide a.

  In a ninth aspect based on the eighth aspect, the switching element is an FET including the switching portion and the diode portion, or a control semiconductor element having a control terminal and a diode connected in reverse parallel thereto. A drive circuit for an electric field control type semiconductor device is provided.

  In a tenth aspect based on any one of the seventh aspect to the ninth aspect, the main terminal of the switching unit is between the other terminal of the secondary winding and the first diode. Connected in series, the control terminal of the switching unit is connected to the one terminal of the secondary winding, to the midpoint of the secondary winding, or to an additional winding provided in the pulse transformer. An electric field control type semiconductor device driving circuit is provided.

  In an eleventh aspect based on any one of the seventh aspect to the ninth aspect, the main terminal of the switching unit is connected in series between the one terminal of the secondary winding and the capacitor. The control terminal of the switching unit is connected to the other terminal of the secondary winding, the midpoint of the secondary winding, or an additional winding provided in the pulse transformer. An electric field control type semiconductor device driving circuit is provided.

In a twelfth aspect based on any one of the seventh aspect to the ninth aspect, the main terminal of the switching unit is between the other terminal of the secondary winding and the first diode. Alternatively, it is connected in series between the one terminal of the secondary winding and the capacitor, and the control terminal of the switching unit receives a drive signal synchronized with the control signal of the control semiconductor switch. An electric field control type semiconductor device driving circuit is provided.

  According to the first aspect, with a very simple circuit configuration, when the electric field control type semiconductor element is turned off, the reverse bias voltage can be applied to the electric field control type semiconductor element to turn it off at high speed. Further, since the reverse bias capacitor is charged with the excitation energy of the pulse transformer and the electric field control type semiconductor switch is reverse biased using the charged voltage, the excitation energy of the pulse transformer can be effectively used. Furthermore, without providing a special circuit, the electric field control semiconductor element does not malfunction even for a steep rising voltage (dv / dt) applied between the drain and source of the electric field control semiconductor element.

  According to the second aspect of the invention, since the second diode accepts and flows the charging current flowing through the reverse bias capacitor, the burden on the transistor can be reduced and the life can be extended.

  According to the third aspect of the invention, since the Schottky barrier diode having a small forward drop is used, higher stabilization of circuit operation can be achieved.

  According to the fourth aspect of the invention, even when a rapidly changing voltage (voltage having a large dv / dt) is applied between the drain and source of the electric field control type semiconductor element, the drive circuit is operated more stably. be able to.

  According to the fifth aspect of the invention, when a steep rising voltage (dv / dt) is applied between the drain and source of the electric field control type semiconductor element, the steep large current flowing through the transistor is the third diode. So that the charging voltage of the reverse bias capacitor is hardly affected, and therefore, the fast turn-off of the electric field control type semiconductor switch is made more reliable.

  According to the sixth aspect, the magnitude of the reverse bias voltage applied between the gate and the source of the electric field control type semiconductor element can be adjusted.

According to the seventh to twelfth aspects of the present invention, even if the control pulse width of the electric field control type semiconductor device is drastically and significantly reduced as the load is lightened rapidly, no malfunction occurs. The electric field control type semiconductor element can be driven stably.

  First, the drive circuit 100 of Example 1 which is the best mode for carrying out the present invention will be described.

[Example 1]
In FIG. 1 showing the drive circuit 100 according to the first embodiment of the present invention, the control semiconductor switch 2 and the primary winding N1 of the pulse transformer 3 are connected across the control power supply 1. Although not shown, the control power source 1 is a DC power source obtained by rectifying and smoothing a commercial AC power source voltage, and the control semiconductor switch 2 is an FET or a transistor. The black dot side indicating the polarity of the secondary winding N2 of the pulse transformer 3 is an electric field control type semiconductor element 20 that is driven on and off through the terminal a and the first diode 4 (hereinafter described as an N-channel FET). Connected to the gate G. An emitter of a PNP transistor 5 is connected between the gate G of the FET 20 and the cathode of the first diode 4, and its collector is connected to the source S of the FET 20 through a reverse bias capacitor 6. The first diode 4 is located between the emitter and base of the transistor 5. Further, the terminal b on the opposite side to the black dot side of the secondary winding N2 of the pulse transformer 3 is also connected to the source S of the FET 20.

  A second diode 7 and a resistor 8 connected in parallel to each other are connected between the base and collector of the PNP transistor 5, and the cathode of the second diode 7 is connected to the base of the transistor 5. The anode is connected to the collector of the transistor 5. Further, a third diode 9 is connected in parallel to the reverse bias capacitor 6, and the third diode 9 is in a direction in which a current flows from the terminal a to the terminal b. Reference numeral 10 denotes a general control circuit of the control semiconductor switch 2.

  Next, the operation of the drive circuit 100 according to the first embodiment will be described. When the control semiconductor switch 2 is turned on by a control signal from the control circuit 10, a voltage with the terminal a being positive with respect to the terminal b is generated in the secondary winding N2 of the pulse transformer 3, and the positive voltage is The voltage is applied to the gate G of the FET 20 through the first diode 4 to charge the gate-source capacitance C1. As the gate-source capacitance C1 is charged, the voltage at the gate G of the FET 20 increases and the FET 20 is turned on. At this time, the PNP transistor 5 is off because the base voltage becomes higher than the emitter, that is, reverse-biased by the forward voltage drop of the first diode 4. At this time, a current flows from the terminal a through the resistor 8 and the third diode 9 or the capacitor 6 to the terminal b, but this current path is not always necessary. The resistance value of the resistor 8 is selected so that the charging current for charging the capacitor 6 in the direction opposite to the illustrated polarity becomes small. The third diode 9 prevents the capacitor 6 from being charged with a polarity opposite to the illustrated polarity.

  Next, when the control semiconductor switch 2 is turned off, a voltage is generated in the secondary winding N2 of the pulse transformer 3 so that the terminal b is positive with respect to the terminal a. At this time, the excitation energy due to the excitation current flowing in the primary winding N1 of the pulse transformer 3 during the ON period of the control semiconductor switch 2 is transmitted to the secondary winding N2, and the current due to the excitation energy is transferred from the terminal b to the capacitor 6. And the second diode 7 to the terminal a to rapidly charge the reverse bias capacitor 6 to the polarity shown. Since the charging current for charging the capacitor 6 to the illustrated polarity is larger than the charging current flowing through the resistor 8 in the opposite direction to the illustrated polarity, the capacitor 6 is connected to the terminal b of the secondary winding N2 of the pulse transformer 3 in a steady state. It is charged to a voltage approximately equal to the voltage between? a. Then, the pulse transformer 3 is reset by the charging voltage of the capacitor 6 that increases as the excitation energy of the pulse transformer 3 is released.

  Here, when the second diode 7 and the resistor 8 are not present, the current between the collector and base of the transistor 5 is the same as that of the PN diode. Flowing. Alternatively, even if the second diode 7 exists, if the forward voltage drop is larger than the voltage drop between the collector and base of the transistor 5, no current flows through the second diode 7, and the current does not flow through the transistor 5. Flows between collector and base. Therefore, the second diode 7 and the resistor 8 are not necessarily required. However, the second diode 7 is preferably present in consideration of the burden and life of the transistor 5, and the resistor 8 is also connected for the reason described later. Is preferred.

  On the other hand, when the control semiconductor switch 2 is turned off and a voltage having the terminal b positive with respect to the terminal a is generated in the secondary winding N2 of the pulse transformer 3, this voltage and the gate-source voltage of the FET 20 As a result, a forward bias current flows between the emitter and base of the PNP transistor 5, and the transistor 5 is turned on. When the transistor 5 is turned on, a closed circuit of the transistor 5, the capacitor 6, and the gate-source capacitance C1 of the FET 20 is formed. Along with this, the voltage of the reverse bias capacitor 6 gives a reverse bias voltage between the gate and source of the FET 20, rapidly discharges the charge of the gate-source capacitance C1 of the FET 20, and makes the FET 20 reliable and fast. Turn off.

  That is, in this embodiment, when the FET 20 is turned off, the excitation energy of the pulse transformer 3 is stored in the capacitor 6 to form a reverse bias source, and the reverse bias source is applied to the FET 20 with the reverse bias source voltage. Thus, not only the FET 20 can be driven off, but also the excitation energy is not wasted, so that the power loss can be reduced.

  Next, when a rapidly rising voltage such as a surge voltage (voltage having a large dv / dt) is applied between the drain D and the source S of the FET 20, the voltage having a large dv / dt is the drain D of the FET 20. A forward bias current is passed from the emitter to the base of the transistor 5 through the capacitance C2 between the gates G to turn on the transistor 5. When the transistor 5 is turned on, the gate G of the FET 20 is connected to the source S through a low-impedance bypass path consisting of the emitter and collector of the transistor 5 and the third diode 9 or the capacitor 6, so that the voltage of the gate G almost increases. Therefore, the transistor 5 does not malfunction due to a large voltage of dv / dt. In this embodiment, since a voltage having a large dv / dt is bypassed through a circuit forming the reverse bias source, a bypass circuit only for bypassing a voltage having a large dv / dt is not necessary. The third diode 9 is not always necessary.

  For a voltage of large dv / dt, the emitter-base current of the transistor 5 flows through the resistor 8 and the transistor 5 is turned on to limit the rise of the gate voltage to prevent malfunction. Depending on the capacitance of the capacitor 6 for use, the voltage of the capacitor 6 may increase in the opposite direction to the polarity of FIG. 1, and the voltage between the gate and source of the FET 20 is changed to the PNP transistor 5 and the second diode 7. Ensures in forward voltage. The resistance 8 is not necessarily required as long as the dv / dt countermeasure is not particularly strengthened, as will be apparent from the experimental results described later.

  In this drive circuit 100, when the forward voltage of the collector-base junction (PN junction) of the PNP transistor 5 is lower than the forward voltage exhibited by the PN junction of the second diode 7, the second diode 7 becomes conductive. In this case, the collector-base junction of the transistor 20 may become conductive, and the meaning of having the second diode 7 disappears. Therefore, the second diode 7 is connected to the collector-base junction (PN junction) of the transistor 5. A diode with a PN junction or barrier that exhibits a forward voltage drop that is less than the forward voltage, such as a Schottky barrier diode, is desirable.

Next, the main four experimental results are described below from the results of various experiments.
[Experimental result 1]
In the driving circuit 100 of FIG. 1, the experimental result with the reverse bias capacitor 6 being 1 μF and the resistor 8 being 1 kΩ is that the waveform of the gate-source voltage Vgs when the FET 20 is turned off is as shown in FIG. Thus, the waveform of the gate-source voltage Vgs when the FET 20 is turned on is as shown in FIG. In FIG. 2, the horizontal axis indicates a time of 250 ns per division (div), and the vertical axis indicates a voltage of 10 V per division (div).

  From FIG. 2A, it takes only less than 1 div, that is, less than 250 ns, for the gate-source voltage Vgs of the FET 20 to drop from the positive constant voltage to the negative constant voltage when the FET 20 is turned off. I understand. This indicates that the time until the gate-source capacitance C1 of the FET 20 is discharged from the illustrated polarity and charged to the opposite polarity is less than 250 ns, and the gate-source capacitance of the FET 20 is reduced in a very short time. The voltage of the inter-source capacitance C1 is inverted. Therefore, the FET 20 is quickly turned off in a short time of less than 250 ns.

Also, as can be seen from FIG. 2B, the rise time of the gate-source voltage Vgs when the FET 20 is turned on is about 500 ns, which is sufficiently fast when a normal converter is used. Moreover, although an overshoot (a rising part at the end of rising) occurs, this is not a problem in practice.
[Experimental result 2]
In the driving circuit 100 of FIG. 1, the experimental result in which the reverse bias capacitor 6 is 1 μF and the resistor 8 is removed (the resistor 8 is made infinite, and only the diode 7 exists between the base and collector of the transistor 5). The waveform of the gate-source voltage Vgs when the FET 20 is turned off is as shown in FIG. 3A, and the waveform of the gate-source voltage Vgs when the FET 20 is turned on is as shown in FIG. . In FIG. 3, the horizontal axis indicates a time of 250 ns / div, and the vertical axis indicates a voltage of 10 V / div.

  The waveform of the gate-source voltage Vgs when the FET 20 is turned off is almost the same as in the case of the experimental result 1. The time from when the gate-source capacitance C1 of the FET 20 is discharged from the illustrated polarity to being charged to the opposite polarity is less than 250 ns, and the gate-source capacitance C1 of the FET 20 is very short. You can see that the voltage is reversed.

As can be seen from FIG. 3B, the rise time of the gate-source voltage Vgs when the FET 20 is turned on is about 500 ns, which is sufficiently fast when a normal converter is used. Moreover, although an overshoot (a rising part at the end of rising) occurs, this is not a problem in practice.
[Experimental result 3]
In the drive circuit 100 of FIG. 1, the reverse bias capacitor 6 is removed (capacitance is zero) so that only the third diode 9 is removed, and the resistor 8 is also removed (∞). The waveform of the gate-source voltage Vgs is as shown in FIG. 4A, and the waveform of the gate-source voltage Vgs when the FET 20 is turned on is as shown in FIG. In FIG. 4, the horizontal axis indicates a time of 250 ns / div, and the vertical axis indicates a voltage of 10 V / div.

  From FIG. 4A, it can be seen that when the FET 20 is turned off, it takes more than 4 div, that is, 1000 ns or more for the gate-source voltage Vgs of the FET 20 to drop from a positive constant voltage to a negative constant voltage. . This indicates that the time until the gate-source capacitance C1 of the FET 20 is discharged from the illustrated polarity and charged to the opposite polarity exceeds 1000 ns. The voltage of the gate-source capacitance C1 of the FET 20 is inverted over the above long time. This indicates that it takes more than 1000 ns for the FET 20 to turn off.

Also, as can be seen from FIG. 4B, the rise time of the gate-source voltage Vgs when the FET 20 is turned on is about 500 ns, which is sufficiently fast when a normal converter is used. Further, the overshoot (the rising part at the end of the rising) is considerably larger than the experimental result 1 and also larger than the experimental result 2.
[Experimental result 4]
In the driving circuit 100 shown in FIG. 1, the reverse bias capacitor 6 is removed (capacitance is zero) and the resistance 8 is 1 kΩ, and the waveform of the gate-source voltage Vgs when the FET 20 is turned off is shown in FIG. The waveform of the gate-source voltage Vgs when the FET 20 is turned on is as shown in FIG. 5B. In FIG. 5, the horizontal axis indicates a time of 250 ns / div, and the vertical axis indicates a voltage of 10 V / div.

  From FIG. 5 (a), when the FET 20 is turned off, the gate-source voltage Vgs of the FET 20 drops from a positive constant voltage to a negative constant voltage. It can be seen that it takes a long time. This indicates that the time until the gate-source capacitance C1 of the FET 20 is discharged from the illustrated polarity and charged to the opposite polarity exceeds 1000 ns. The voltage of the gate-source capacitance C1 of the FET 20 is inverted over the above long time. This also indicates that it takes a long time exceeding 1000 ns for the FET 20 to turn off.

  Further, as can be seen from FIG. 5B, the rising characteristic of the gate-source voltage Vgs when the FET 20 is turned on is similar to that of the experimental result 3.

  As can be seen from the experimental results 3 and 4 with respect to the above experimental results 1 and 2, the reverse bias action of the capacitor 6 due to the presence of the reverse bias capacitor 6 causes the gate-source capacitance C1 of the FET 20 to be increased at high speed. Discharging and reversing from the illustrated polarity to the opposite polarity in a short time, the FET 20 is turned off at high speed. It can also be seen that the resistor 8 is not necessarily required for increasing the turn-off speed of the FET 20.

  Note that the reverse bias capacitor 6 having a capacitance of 1 μF is an example, and flows to the gate-source capacitance C1 of the FET 20 and the drain-gate capacitance C2 of the FET 20 at dv / dt. It is determined by the value of the charging current and the like, and the capacitance of the capacitor 6 is preferably sufficiently larger than at least the gate-source capacitance C1 of the FET 20. From various experimental results, it has been confirmed that the same functions as those of the experimental results 1 and 2 are performed even if other capacities are obtained. In addition, even when the diodes 7 and 9 are removed, it has been confirmed that this drive circuit operates normally and can achieve the objects and effects of the present invention.

[Example 2]
Next, referring to FIG. 6, a driving circuit 200 according to a second embodiment of the present invention will be described. The same symbols as those used in FIG. 1 indicate members having the same names.

  The difference between the second embodiment and the first embodiment is that in the drive circuit 200 of the second embodiment, the secondary winding of the pulse transformer 3 is changed to two secondary windings N2 and N3 in series. The connection point between them is the terminal c, and the connection point between the reverse bias capacitor 6 and the collector of the transistor 5 is connected to the terminal c through the diode 7 '.

  When the terminal a of the secondary winding of the pulse transformer 3 is positive with respect to the terminal b, the operation is the same as that of the drive circuit 100 of the first embodiment, and the description thereof is omitted.

  When the control semiconductor switch 2 is turned off, the terminal a of the secondary winding N2 of the pulse transformer 3 has a negative polarity with respect to the terminal c, and the terminal b of the secondary winding N3 has a positive polarity with respect to the terminal c. The excitation energy of the primary winding N1 of the pulse transformer 3 is transferred to the secondary windings N2 and N3, from the terminal b to the terminal 6 through the capacitor 6 and the diode 7 ', and from the terminal b to the terminal through the capacitor 6 and the resistor 8. flows to a. In this case, the current flowing through the resistor 8 is smaller than the current flowing through the diode 7 '. With this charging current, the capacitor 6 is charged to the voltage of the secondary winding N3 with the polarity shown. If the number of turns of the secondary windings N2 and N3 is equal, the charging voltage of the reverse bias capacitor 6 is approximately half the voltage between the terminals a and b. This voltage is approximately ½ of the voltage of the gate-source capacitance C1 of the FET 20.

  Here, in the illustrated polarity direction, compared to the current for charging the capacitor 6 for reverse bias through the diode 7 ′, in the illustrated polarity direction compared to the magnitude of the current for charging the capacitor 6 through the resistor 8 in the opposite direction. Since the resistance value of the resistor 8 is selected so that the current to be charged becomes larger, the voltage of the illustrated polarity of the capacitor 6 is almost half of the voltage between the terminal a and the terminal b in the steady state. The fluctuation is small.

  On the other hand, when the control semiconductor switch 2 is turned off, the terminal a of the secondary winding of the pulse transformer 3 becomes negative with respect to the terminal c and the terminal b becomes positive with respect to the terminal c. Similarly, the transistor 5 is forward-biased and turned on, and a closed circuit including the transistor 5, the capacitor 6, and the gate-source capacitance C1 of the FET 20 is formed. By forming this closed circuit, the gate-source of the FET 20 is reverse-biased by the voltage of the capacitor 6, the charge of the gate-source capacitance C1 of the FET 20 is rapidly discharged, and the FET 20 is turned off at high speed. . Even if the voltage of the capacitor 6 for reverse bias is about half of the gate-source forward bias voltage of the FET 20, the FET 20 can be driven off at high speed. In this embodiment, the magnitude of the reverse bias voltage can be adjusted by adjusting the number of turns of the secondary windings N2 and N3 of the pulse transformer 3.

  In the case where a rapidly rising voltage such as a noise voltage (voltage having a large dv / dt) is applied between the drain D and the source S of the FET 20, the transistor 5 and the diode 9 Since the current that changes sharply through the capacitor 6 is bypassed, the description is omitted.

[Example 3]
Next, a third embodiment of the present invention will be described with reference to FIGS. FIG. 7 is a diagram showing a driving circuit 300 according to the third embodiment of the present invention. FIG. 8A shows the drive voltage-time characteristics of the drive circuits 100 and 200, and FIG. 8B shows the drive voltage-time characteristics of the drive circuit 300 of the third embodiment.

  According to the driving circuit 100 of the first embodiment and the driving circuit 200 of the second embodiment described above, an electric field control type semiconductor device such as an FET or an IGBT can be turned off at a high speed, but the driving pulse width is abrupt. When it becomes significantly smaller, it may malfunction. The drive circuit 300 according to the third embodiment shown in FIG. 7 is characterized in that it operates normally even when the drive pulse width is drastically reduced.

  First, before the driving circuit 300 according to the third embodiment is described with reference to FIGS. 7 and 8B, the driving circuit 100 according to the first embodiment and the driving circuit 200 according to the second embodiment have a sudden driving pulse width. The reason for malfunction when it becomes significantly smaller will be described. As shown in FIG. 8A, when the width of the drive pulse applied to the gate of the FET 20 suddenly decreases from W1 (for example, about 10 μs) to W2 (for example, about 2 μs), the positive / negative of the core of the pulse transformer 3 Phenomenon in which the voltage / time product of the pulse transformer 3 greatly differs temporarily occurs, and then, the negative voltage / time product P1 and the positive voltage / time product P2 of the core of the pulse transformer 3 work to be substantially the same. . The reason for this is that the off-period of the FET 20 becomes abruptly long, and during that off-period, the voltage of the polarity shown in the capacitor 6 causes a direct current in the direction from the terminal b to the terminal a to flow through the secondary winding N2 of the pulse transformer 3. Therefore, the pulse transformer 3 is excessively reset in that direction, and then the negative voltage / time product P1 and the positive voltage / time product P2 work to be equal depending on the core characteristics of the pulse transformer 3. It is.

  Therefore, as apparent from FIG. 8A, the voltage / time product P2 generated by the positive drive pulse is smaller than the negative voltage / time product P1 of the pulse transformer 3, so that these voltage / time products are equal. Thus, at time t0 before time t1 when the original positive drive pulse is generated, the terminal a of the secondary winding N2 of the pulse transformer 3 generates a voltage that is positive with respect to the terminal b. The positive voltage generated at time t0 turns on the FET 20 at time t0. That is, the FET 20 malfunctions.

  As described above, the drive circuit 300 according to the third embodiment includes the switch element 30 for preventing a direct current from flowing from the capacitor 6 to the secondary winding N2 of the pulse transformer 3. The switch element 30 is preferably a three-terminal electric field control type semiconductor element having a control terminal, particularly an FET. In this embodiment, an N-channel type FET is used. This N-channel FET is a general FET and has a body diode 30a. In FIG. 7, the same symbols as those used in FIG. 1 indicate members having the same names.

  The switch element 30 must be turned on and off almost simultaneously when the FET 20 driven by the drive circuit 300 is turned on and off. That is, the switch element 30 must prevent a direct current from flowing through the secondary winding N2 of the pulse transformer 3 due to the voltage of the illustrated polarity charged in the capacitor 6, and the capacitor 6 is illustrated as described above. Do not prevent the battery from being charged to a polarity voltage. Accordingly, the switching element 30 includes a switching unit that performs an on / off function, such as an FET, and a diode that charges the capacitor 6 by passing the excitation energy of the pulse transformer 3 as a reset current when the switching unit is turned off. And must have a part. This diode part may be provided in parallel in the opposite direction so that a current flows in the opposite direction to the switching part, that is, in antiparallel with the switching part, or may be separately connected.

  In terms of both main terminals of the switch element 30, that is, an N-channel FET, the drain terminal and the source terminal are between the terminal b of the secondary winding N 2 of the pulse transformer 3 and the terminal x of the capacitor 6. Connected in series, the control terminal of the switch element 30, the N-channel FET, the gate terminal is connected to the terminal a of the secondary winding N2.

  Since this drive circuit 300 is the same as that of the first embodiment except for the operation of the switch element 30, only the operation related to the switch element 30 will be described here. The N-channel FET used as the switch element 30 is turned on when a positive voltage higher than a certain value is applied to the gate, and turned off when the voltage is removed, or turned off when a negative voltage is applied. Is.

  When the control semiconductor switch 2 is turned on by a control signal from the control circuit 10, a voltage that causes the terminal a to be positive with respect to the terminal b is generated in the secondary winding N <b> 2 of the pulse transformer 3. Applied to the gate G of the FET 20 through the first diode 4 to turn on the FET 20. At the same time, the N-channel FET that is the switch element 30 is also turned on by the positive voltage generated at the terminal a. Therefore, the switch element 30 does not have any adverse effect when the FET 20 is turned on.

  Next, when the control semiconductor switch 2 is turned off, the secondary winding N2 of the pulse transformer 3 generates a voltage in which the terminal a is a negative electrode with respect to the terminal b. Although the N-channel FET, which is the switching element 30, is also turned off by the negative voltage generated at the terminal a, the body diode 30a is forward biased and becomes conductive. Due to the conduction of the body diode 30a, the excitation energy of the pulse transformer 3 is changed from the secondary winding N2 to its terminal b, the body diode 30a of the N-channel FET, the capacitor 6, the second diode 7, the anode of the diode 4 and the diode 7 As a reset current flows instantaneously through the connection point y and the terminal a, the reverse bias capacitor 6 is charged to the polarity shown in the figure. The pulse transformer 3 is reset by the charging voltage of the capacitor 6 due to the release of the excitation energy of the pulse transformer 3. At this time, the voltage of the terminal b and the charging voltage of the capacitor 6 become substantially equal, so the body diode 30a is non-conductive. It becomes.

  That is, the body diode 30a of the N-channel FET becomes non-conductive when the pulse transformer 3 is reset, and at this time, the switch element 30 cuts off between the terminal b and the terminal x of the capacitor 6. By this interruption, the voltage of the capacitor 6 is not applied to the secondary winding N2 of the pulse transformer 3 through the switch element 30, and therefore the pulse transformer 3 is not excessively reset. This is shown in FIG. 8B. Since the pulse transformer 3 is not excessively reset, even when the pulse width of the drive pulse is suddenly reduced from P3 to P4, as shown in FIG. 8A. In addition, since a positive voltage is not generated at the terminal a at time t0 before the time t1 when the original positive drive signal is generated, and a predetermined narrow pulse width is maintained, the FET 20 does not malfunction.

  In this embodiment, for the purpose of overvoltage protection between the gate and the source of the N-channel type FET which is the switch element 30, two Zener diodes 30b and 30c are connected in the opposite directions between the gate and the source, or voltage protection is performed. The elements are connected. Although not shown, a current limiting resistor may be provided in series with the gate terminal of the switch element 30.

[Example 4]
The drive circuit 400 of the fourth embodiment shown in FIG. 9 uses a P-channel FET that is turned on when a negative voltage of a certain magnitude or more is applied to the gate terminal. When a P-channel FET is used, the source terminal and the drain terminal, which are the main terminals of both P-channel FETs, are opposite to the N-channel FET, respectively, and the connection point between the terminal a of the secondary winding N2. and the gate terminal of the secondary winding N2 is connected to the terminal b of the secondary winding N2. However, the P-channel FET has a body diode 30a having a polarity in which the terminal a side is a cathode and the anode side of the diode 4 is an anode. The P-channel FET 30 is turned on when the terminal a of the secondary winding N2 of the pulse transformer 3 is positive and the terminal b is a negative voltage, and turned off when the voltage is the opposite. When this is off, the body diode 30a becomes conductive, and the excitation energy of the pulse transformer 3 flows as a reset current from the secondary winding N2 through its terminal b, capacitor 6, diode 7, connection point y, body diode 30a, and terminal a. 6 is charged to the polarity shown, and the pulse transformer 3 is reset. Since the function of the P-channel FET is the same as that of the N-channel FET, further explanation is omitted. In addition, the symbol same as the symbol used in FIG. 7 shall show the member of the same name.

  Although not shown, in Example 3 and Example 4, the pulse transformer 3 is provided with an additional winding having an appropriate number of turns (not shown), and an N-channel FET or P-channel type used as the switch element 30 in the additional winding. Of course, an appropriate magnitude of driving voltage may be obtained by connecting the gate terminals of the FETs.

[Example 5]
A drive circuit 500 according to the fifth embodiment illustrated in FIG. 10 is obtained by connecting the switch element 30 to the drive circuit 200 according to the second embodiment illustrated in FIG. 6. Also in this embodiment, an N-channel FET is used as the switch element 30. The drain terminal and the source terminal, which are the main terminals of the N-channel FET 30, are connected to the terminal x of the capacitor 6 and the terminal b of the secondary winding N3 of the pulse transformer 3, and the gate terminals thereof are connected to the secondary windings N2 and N3. Is connected to a terminal c which is a midpoint tap. When the terminal c is positive and the terminal b is a negative polarity voltage, the N-channel FET 30 is turned on. When the terminal b is the opposite polarity voltage, the N-channel FET 30 is turned off. Since it is the same as that, the description is omitted.

  Also in this embodiment, a P-channel FET can be used. As in the case of Embodiment 3, the P-channel FET is connected between the terminal a and the connection point y between the anode of the diode 4 and the resistor 8. The main terminals may be connected in series and the gate terminal connected to the terminal c. In FIG. 10, the same symbols as those used in FIGS. 6 and 7 indicate members having the same names.

[Example 6]
As shown in FIG. 11, the drive circuit 600 according to the sixth embodiment uses the NPN transistor 30 as the switch element shown in FIG. 7 and a diode 30a connected in reverse parallel thereto, and uses the base of the transistor 30 as shown in FIG. The terminal receives a drive signal from the control circuit 10. As described above, the control semiconductor switch 2 is turned on by the control signal from the control circuit 10, and accordingly, the FET 20 is also turned on by the voltage generated in the secondary winding N2 of the pulse transformer 3. In FIG. 11, the same symbols as those used in FIG. 7 indicate members having the same names.

  On the other hand, at the same time that the control circuit 10 gives a control signal to the gate terminal of the control semiconductor switch 2, the control circuit 10 gives a drive signal to the base terminal of the transistor 30 that is a switch element to turn on the transistor 30. Then, the control circuit 10 stops supplying the control signal to the gate terminal of the control semiconductor switch 2 and simultaneously stops supplying the drive signal to the base terminal of the transistor 30. As described above, the transistor 30 that is a switch element performs an on / off operation in synchronization with the on / off of the control semiconductor switch 2, that is, the FET 20, by the drive signal from the control circuit 10.

  As the control semiconductor switch 2 is turned off, the secondary winding N2 of the pulse transformer 3 generates a voltage at which the terminal b is positive with respect to the terminal a as described above. When this voltage causes a diode 30a such as a Schottky barrier diode with a small forward drop to conduct, the excitation energy of the pulse transformer 3 flows as a reset current to the capacitor 6 to be charged, and the reset of the pulse transformer 3 is completed in a short time. The diode 30a becomes non-conductive, and the switch element 30 is completely turned off. As a result, the transistor 30 cuts off between the terminal x and the terminal b of the capacitor 6, so that the voltage of the capacitor 6 is not applied to the secondary winding N <b> 2 of the pulse transformer 3 after the reset of the pulse transformer 3 is completed. In this embodiment, the transistor 30 may of course be a PNP type. In this case, only the polarity of the drive signal is different. An FET may be used in place of such a junction type transistor. In the case of an FET, there is a body diode, but in the above embodiments, a diode may be further connected in parallel to the FET. It is preferable to use a Schottky barrier diode with a small forward drop as the diode in terms of reducing power loss.

  In the above embodiments, the electric field control type semiconductor element 20 has been described as an N-channel type FET, and the transistor 5 has been described as a PNP type transistor. However, even if the electric field control type semiconductor element 20 is a P-channel type FET. It can be driven in the same manner as described above. In this case, in the driving circuit 100 shown in FIG. 1, an NPN type transistor may be used as the transistor 5, and the polarities of the diodes 4, 7, and 9 may be reversed. The charging polarity of the reverse bias capacitor 5 is opposite to that shown in the figure. Naturally, the capacitance between the gate and the source of the P-channel FET is also charged opposite to the polarity shown. The pulse transformer 3 is provided with two secondary windings, and a drive circuit is formed by connecting the transistor 5 and the capacitor 6 to each secondary winding. According to this drive circuit, the bridge inverter circuit Two FETs crossing (not shown) are turned on at the same time, or not shown, but two FETs connected in series across the primary winding of the transformer, and each FET and primary winding Two FETs of a double forward converter composed of two feedback diodes connected across each other can be driven simultaneously.

In the above embodiments, the electric field control type semiconductor device has been described as an FET. However, it is a matter of course that the same effect can be obtained even with an IGBT.

It is a figure which shows the drive circuit 100 of the electric field control type semiconductor switch element which is the 1st Example of this invention. The waveform of the gate-source voltage Vgs of the FET 20 when the reverse bias capacitor 6 of the drive circuit 100 is 1 μF and the resistance 8 is 1 kΩ is shown, (a) is the waveform at the time of turn-off, and (b) is the waveform at the time of the turn-on. Waveform is shown. The waveform of the gate-source voltage Vgs of the FET 20 when the reverse bias capacitor 6 of the drive circuit 100 is 1 μF and the resistance 8 is infinite (∞) is shown, (a) is the waveform at turn-off, (b) Indicates the waveform at turn-on. The waveform of the gate-source voltage Vgs of the FET 20 when the reverse bias capacitor 6 of the drive circuit 100 is infinite (∞) and the resistance 8 is infinite (∞) is shown. Waveform (b) shows the waveform at turn-on. The waveform of the gate-source voltage Vgs of the FET 20 when the reverse bias capacitor 6 of the drive circuit 100 is infinite (∞) and the resistance 8 is 1 kΩ is shown, (a) is the waveform at turn-off, (b ) Shows the waveform at turn-on. It is a figure which shows the drive circuit 200 of the electric field control type semiconductor switch element which is the 2nd Example of this invention. It is a figure which shows the drive circuit 300 of the electric field control type semiconductor switch element which is the 3rd Example of this invention. FIG. 6 is a diagram illustrating a drive voltage-time characteristic in a drive circuit according to an embodiment of the present invention, in which (A) is for the drive circuit 100 and (B) is for the drive circuit 300; It is a figure which shows the drive circuit 400 of the electric field control type semiconductor switch element which is the 4th Example of this invention. It is a figure which shows the drive circuit 500 of the electric field control type semiconductor switch element which is the 5th Example of this invention. It is a figure which shows the drive circuit 600 of the electric field control type semiconductor switch element which is the 6th Example of this invention. It is a figure which shows the drive circuit of the conventional electric field control type semiconductor switch element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Control power supply 2 ... Control semiconductor switch 3 ... Pulse transformer 4 ... Diode 5 ... PNP transistor 6 ... Reverse bias capacitor 7 ... Diode
DESCRIPTION OF SYMBOLS 8 ... Resistance 9 ... Diode 10 ... Control circuit 20 ... Electric field control type semiconductor element 30 ... Switch element 100 ... Drive circuit of 1st Example 200 ... 2nd Driving circuit 300 of the embodiment 300 ... Driving circuit of the third embodiment 400 ... Driving circuit of the fourth embodiment 500 ... Driving circuit of the fifth embodiment 600 ... Sixth embodiment Drive circuit

Claims (12)

A control power source, a primary winding connected in series to the control power source, and a secondary winding magnetically coupled to the primary winding and having one terminal connected to the source of the electric field control type semiconductor device; A control transformer connected in series with the control power source and the primary winding, and between the other terminal of the secondary winding and the gate of the electric field control type semiconductor element. A first diode connected in series; a transistor having a base and an emitter connected to each of an anode and a cathode of the first diode; one end connected to the collector of the transistor; A capacitor connected to the one terminal of the next winding,
When the control semiconductor switch is turned off, the capacitor is charged by an exciting current flowing through the secondary winding of the pulse transformer, and the gate-source of the electric field control type semiconductor element is reverse-biased by the charging voltage of the capacitor. A drive circuit for an electric field control type semiconductor element. In claim 1,
A drive circuit for an electric field control type semiconductor device, wherein a second diode is connected in parallel between the collector and base of the transistor from the collector toward the base. In claim 2,
The drive circuit of the electric field control type semiconductor device, wherein the second diode is a Schottky barrier diode. In claim 1,
A drive circuit for an electric field control type semiconductor device, wherein a resistor is connected in parallel between a collector and a base of the transistor. In claim 1,
3. A drive circuit for an electric field control type semiconductor device, wherein a third diode is connected in parallel with the capacitor so that a cathode is connected to one terminal of the secondary winding. In claim 1,
The secondary winding comprises two first and second secondary windings connected in series,
A drive circuit for an electric field control type semiconductor device, wherein a fourth diode is connected from a collector of the transistor toward a series connection point of the first and second secondary windings. In any one of Claims 1 thru | or 6,
A switch element for preventing the electric charge charged in the capacitor from being discharged to the secondary winding of the pulse transformer, and connected in series between the capacitor and the secondary winding;
The switching element is turned on and off together with the on / off of the electric field control type semiconductor element, and charged when the switching part is turned off by passing excitation energy of the pulse transformer as a reset current to the capacitor. A drive circuit for an electric field control type semiconductor device, characterized by comprising a diode section. In claim 7,
The drive circuit of the electric field control type semiconductor device, wherein the diode unit is provided in antiparallel with the switching unit or separately connected in antiparallel. In claim 7,
The switch element is an FET including the switching unit and the diode unit, or a control semiconductor element having a control terminal and a diode connected in reverse parallel to the control semiconductor element. Drive circuit. In any one of claims 7 to 9,
The main terminal of the switching unit is connected in series between the other terminal of the secondary winding and the first diode,
The control terminal of the switching unit is connected to the one terminal of the secondary winding, the midpoint of the secondary winding, or an additional winding provided in the pulse transformer. An electric field control type semiconductor device driving circuit. In any one of claims 7 to 9,
The main terminal of the switching unit is connected in series between the one terminal of the secondary winding and the capacitor,
The control terminal of the switching unit is connected to the other terminal of the secondary winding, a midpoint of the secondary winding, or an additional winding provided in the pulse transformer. Driving circuit for electric field control type semiconductor element. In any one of claims 7 to 9,
The main terminal of the switching unit is connected in series between the other terminal of the secondary winding and the first diode, or between the one terminal of the secondary winding and the capacitor. ,
The drive circuit of the electric field control type semiconductor element, wherein the control terminal of the switching unit receives a drive signal synchronized with a control signal of the control semiconductor switch.

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