JP2005116604A - Substrate with built-in electronic component, and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a substrate with a built-in electronic component which includes an accurate capacitor. <P>SOLUTION: In the substrate with a built-in electronic component, the capacitor is included in a multilayer printed wiring board in which insulator layers and conductor layers are formed alternately. In the capacitor, a capacitor lower electrode is arranged on a part of any one of insulators which form the multilayer printed wiring board. In the substrate, a dielectric layer is arranged so as to cover the capacitor lower electrode, and a capacitor upper electrode whose area is larger than that of the capacitor lower electrode is arranged at an upper part of the dielectric layer. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an electronic component built-in substrate in which electronic components are pre-fabricated on a multilayer printed wiring board and a method for manufacturing the same.

  In recent years, with the demand for higher performance and smaller size of electronic devices, the density and functionality of circuit components are increasing. Therefore, when mounting electronic components on a printed wiring board, a printed wiring board having a structure in which passive components such as a capacitor (C), a resistor (R), and an inductor (L) are built in the substrate in order to increase the mounting efficiency. Is attracting attention.

  For example, a method of embedding a leadless circuit component in a through hole provided in a printed circuit board (for example, refer to Patent Document 1), and a method of embedding a passive component such as a ceramic capacitor in a through hole provided in an insulating substrate ( For example, refer to Patent Document 2), and a method of embedding a bypass capacitor of a semiconductor element in a hole of a printed circuit board (for example, refer to Patent Documents 3 and 4).

  However, when embedding and mounting a chip capacitor having a large capacity in advance by the above method in a through-hole, the layer thickness is 0.3 mm or 0.6 mm even if the smallest size 0603 chip is used at present. Therefore, it is difficult to realize a thin multilayer substrate, and there is a concern that cracks may occur due to a difference in thermal expansion coefficient between the insulating resin and the chip component.

  In addition, many methods have been devised for making capacitors in printed wiring boards. Capacitors are formed from two conductive foil-coated electrodes and a dielectric sheet, and these capacitors are printed wiring. There has been a proposal (for example, see Patent Document 5) that is built in the plate. Of the conductive foil surface, one surface (barrel surface) that has been treated to reduce the degree of roughness is in contact with the inner dielectric sheet, and the other surface (matte) that has been roughened and roughened. The surface) contacts the outer member and is firmly attached by the anchor effect.

However, in the method of forming a capacitor by forming a dielectric layer on the entire surface of the substrate as shown in Patent Document 5, a dielectric is present in a portion other than between the capacitor electrodes. From the viewpoint of impedance matching in the circuit of the printed circuit board, it is not preferable that such a high dielectric constant material exists in an unnecessary place. As a technique for avoiding such problems, a dielectric is partially formed on the capacitor lower electrode formed on the inner layer core substrate side by screen printing or the like, and the capacitor upper electrode is formed on the dielectric. However, it has been difficult to form a capacitor having excellent accuracy due to the mismatch between the upper and lower electrodes and the problem of dielectric formation accuracy by screen printing. Regarding the problem of mismatch between the upper and lower electrodes, in Patent Document 6, the upper electrode is made smaller than the lower electrode, and the capacitance is defined by the upper electrode area, thereby solving the capacity reduction due to the mismatch between the upper and lower electrodes. .
JP-A-54-38561 Japanese Patent Publication No. 60-41480 JP-A-4-73992 JP-A-5-218615 Japanese Patent No. 27389590 JP 2003-45742 A

  However, the accuracy of dielectric formation by screen printing is limited, which affects the capacitance tolerance of the capacitor.

  Furthermore, even if the capacitor electrode and the dielectric layer are accurately manufactured, the dielectric layer is slightly laminated on the wiring connected to the capacitor electrode (FIG. 4). In particular, it was difficult to accurately form a small size capacitor.

In order to achieve the above object, a first invention according to claim 1 is an electronic component built-in substrate in which a capacitor is built in a multilayer printed wiring board formed by alternately forming insulating layers and conductor layers, Capacitor is
A capacitor lower electrode is provided on a part of any of the insulating layers forming the multilayer printed wiring board,
A dielectric layer is provided so as to cover the capacitor lower electrode,
An electronic component-embedded substrate, wherein a capacitor upper electrode having a larger area than the capacitor lower electrode is provided on the dielectric layer.

  According to the present invention, the capacitor capacity tolerance derived from the electrode area can be suppressed by accurately creating the capacitor lower electrode area. Further, since the dielectric layer is formed so as to cover the capacitor lower electrode, the thickness of the dielectric layer on the capacitor lower electrode becomes uniform. Further, according to the present invention, since the accuracy of the area of the dielectric layer and the capacitor upper electrode is not required, an efficient method such as a printing method is used for forming the dielectric layer and the capacitor upper electrode. The dielectric resin that can be used for forming the dielectric layer can be freely selected, and the filling rate of the high dielectric filler in the dielectric layer can be increased to 90 wt% or more.

  A second invention according to claim 2 is characterized in that the capacitor lower electrode is formed on a via formed so that the lower electrode is electrically connected to a wiring circuit below the insulating layer. It is an electronic component built-in board of description.

  According to the present invention, the conduction of the capacitor lower electrode is made by arranging a via directly under the capacitor lower electrode, so that the influence of the wiring portion is affected even if the electrode area is defined by changing the electrode size above and below the capacitor. It became possible to lose.

  A third invention according to claim 3 is characterized in that a pattern for preventing flow of the dielectric material forming the dielectric layer is formed around the capacitor lower electrode. 2. The electronic component built-in substrate according to 2.

  By providing an anti-flow prevention pattern for the dielectric material around the capacitor lower electrode, it is possible to prevent the dielectric material from flowing out of a predetermined area even when a low viscosity dielectric material is used to make the thickness of the dielectric layer uniform. In addition, the accuracy of the thickness of the dielectric layer on the capacitor lower electrode can be increased.

A fourth invention according to claim 4 is a method of manufacturing a substrate with built-in electronic components in which a capacitor is incorporated in a multilayer printed wiring board formed by alternately forming insulating layers and conductor layers, and includes the following steps: It is a manufacturing method of the electronic component built-in board | substrate characterized.
a. Providing a capacitor lower electrode on a part of any insulating layer forming the multilayer printed wiring board;
b. A step of providing a dielectric layer by screen printing a high dielectric resin paste mainly composed of a thermosetting resin so as to cover the capacitor lower electrode on a part of the insulating layer;
c. Forming a capacitor upper electrode occupying a larger area than the capacitor lower electrode, and a connecting portion between the capacitor upper electrode and the wiring circuit in the multilayer printed wiring board by a conductive paste;

  According to the present invention, the capacitor capacity tolerance derived from the electrode area can be suppressed by accurately creating the capacitor lower electrode area. Further, since the dielectric layer is formed so as to cover the capacitor lower electrode, the thickness of the dielectric layer on the capacitor lower electrode becomes uniform. Further, according to the present invention, an efficient screen printing method can be used for forming the dielectric layer, and an improvement in productivity can be expected, and the dielectric resin that can be used for forming the dielectric layer can be freely selected. It is possible to increase the filling rate of the high dielectric filler in the dielectric layer to 90 wt% or more. Furthermore, since the connection portion between the capacitor upper electrode and the wiring circuit in the multilayer printed wiring board is formed of a conductive paste, an efficient method such as a printing method can be adopted.

A fifth aspect of the invention according to claim 5 is the method of manufacturing an electronic component built-in substrate according to claim 4, which includes the following two steps instead of step a according to claim 4.
d. A step of forming a via hole for establishing electrical connection with a wiring circuit below the insulating layer in any insulating layer forming the multilayer printed wiring board;
And e. Applying via filling to the via hole and forming a via and a capacitor lower electrode that are electrically connected to the lower wiring circuit;
According to the present invention, the conduction of the capacitor lower electrode is made by arranging a via directly under the capacitor lower electrode, so that the influence of the wiring portion is affected even if the electrode area is defined by changing the electrode size above and below the capacitor. It can be lost. In addition, a capacitor lower electrode having an accurate area can be formed in the same process as that for forming the conduction portion of the capacitor. Since a conventional printed wiring board manufacturing method such as via formation and filled via plating can be used, there is no need for new equipment and productivity is good.

According to a sixth aspect of the present invention, between the step b and the step c according to the fourth aspect,
f. Performing mechanical polishing of the dielectric layer;
The method of manufacturing a substrate with built-in electronic components according to claim 4 or 5, wherein

  By performing mechanical polishing, the accuracy of the capacitor upper electrode can be improved.

According to a seventh aspect of the present invention, before the step a according to the fourth aspect or before the step d according to the fifth aspect,
g. Forming an insulating layer by laminating an insulating resin sheet mainly composed of a thermosetting resin on an insulating substrate on which a wiring circuit is formed;
The method for manufacturing a substrate with built-in electronic components according to claim 4, wherein:

  By using an insulating resin sheet formed with a constant thickness, it is possible to efficiently manufacture a substrate with a built-in electronic component having a stable quality.

According to an eighth aspect of the invention, instead of the step a of the fourth aspect,
h. A step of providing a capacitor lower electrode on a part of any of the insulating layers forming the multilayer printed wiring board, and forming a dielectric layer anti-flow pattern around the capacitor lower electrode;
The method of manufacturing a substrate with built-in electronic components according to claim 4, wherein

  By providing an anti-flow prevention pattern for the dielectric material around the capacitor lower electrode, it is possible to prevent the dielectric material from flowing out of a predetermined area even when a low viscosity dielectric material is used to make the thickness of the dielectric layer uniform. In addition, the accuracy of the thickness of the dielectric layer on the capacitor lower electrode can be increased.

According to a ninth aspect of the present invention, in place of the step e of the fifth aspect,
i. Applying via filling to the via hole, forming a via and a capacitor lower electrode conductive with the lower wiring circuit, and forming a dielectric layer anti-flow pattern around the capacitor lower electrode;
The method for manufacturing an electronic component built-in substrate according to claim 5, comprising:

  According to the present invention, it is possible to form the capacitor lower electrode and the dielectric layer anti-flow pattern having the correct area in the same process as the formation of the conductive portion of the capacitor. Since the capacitor lower electrode and the anti-flow prevention pattern can be formed with the same thickness, it is more effective for smoothing the dielectric layer formed thereon. Further, since a conventional printed wiring board manufacturing method such as via formation and filled via plating can be used, there is no need for new equipment and productivity is good.

  According to the present invention, the capacitor capacity tolerance derived from the electrode area can be suppressed by accurately creating the capacitor lower electrode area. Further, since the dielectric layer is formed so as to cover the capacitor lower electrode, the thickness of the dielectric layer on the capacitor lower electrode becomes uniform. Furthermore, since accurate accuracy is not required for the area of the dielectric layer and the capacitor upper electrode, it is possible to use an efficient method such as a printing method for forming the dielectric layer and the capacitor upper electrode. The dielectric resin that can be used to form the dielectric layer is free to be selected, and the filling rate of the high dielectric filler in the dielectric layer can be increased to 90 wt% or more. By subjecting the dielectric layer to mechanical polishing, the capacitor upper electrode laminated thereon can also be formed smoothly. By laminating the insulating layer that will form the capacitor lower electrode using an insulating resin sheet formed with a constant thickness, it is possible to efficiently manufacture a substrate with a built-in electronic component having a stable quality.

  In addition, it is possible to eliminate the influence of the wiring part even if the electrode area is defined by changing the electrode size above and below the capacitor by placing vias directly under the capacitor lower electrode to conduct the capacitor lower electrode. I was able to. In the present invention, the capacitor lower electrode having an accurate area can be formed in the same process as that for forming the conductive portion of the capacitor. Since a conventional printed wiring board manufacturing method such as via formation and filled via plating can be used, there is no need for new equipment and productivity is good.

  In addition, by providing a dielectric material flow prevention pattern around the capacitor lower electrode, even if a low viscosity dielectric material is used to make the thickness of the dielectric layer uniform, the dielectric material is prevented from flowing out of the specified area. In addition, the accuracy of the thickness of the dielectric layer on the capacitor lower electrode could be increased.

  Therefore, according to the present invention, it is possible to provide an inexpensive electronic component built-in board incorporating a highly accurate and high-capacitance capacitor with excellent reliability.

  The manufacturing method of the electronic component built-in substrate of the present invention will be briefly described. First, a wiring circuit is formed on an insulating layer, and an insulating layer is further laminated thereon. In FIG. 1, an insulating resin sheet is laminated with a vacuum laminator on the core substrate (10) (FIG. 1 (a)) on which the wiring circuit (11) is formed, and cured in a hot air oven set at a predetermined temperature. The case where the insulating layer (12) is formed is shown (FIG. 1B). Via holes (13) that reach the lower wiring circuit are formed by UV-YAG laser at predetermined positions on the insulating layer where capacitor electrodes are formed (FIG. 1 (c)), and then via electrical via plating is performed. The vias (14) and the capacitor lower electrodes (15) for conducting electrical connection with the lower wiring circuit are formed by etching, filling the holes and forming the conductor layer (FIG. 1 (c)). Hereinafter, among the electrodes facing each capacitor, the small electrode formed on the insulating layer is referred to as a capacitor lower electrode, and the other large electrode is referred to as a capacitor upper electrode. There are no particular limitations on the via connection / hole filling method as long as it is used in an ordinary printed wiring board manufacturing method.

  A high dielectric resin paste made of a thermosetting resin and a high dielectric constant filler is patterned on the capacitor lower electrode (15) on the insulating layer (12) thus formed. The screen printing method is preferable because it has moderate accuracy and productivity. The high dielectric resin paste laminated on the necessary part on the substrate is heated and cured to form a dielectric layer (16) on each electrode (FIG. 1 (d)). Thereafter, the surface of the dielectric is polished with a buff or the like to smooth the surface (not shown), and then a conductive paste is screen-printed on the dielectric to form the capacitor upper electrode (17), the capacitor upper electrode and the wiring. The connecting portion (18) is formed (FIG. 1E). Thereafter, the insulating resin film is again laminated and thermally cured to form an insulating layer (12), and via processing and plating are performed to form a predetermined wiring circuit pattern. By repeating the above steps a plurality of times, a desired electronic component built-in substrate can be obtained (FIG. 1 (f)).

  Examples of the material constituting the insulating layer in the present invention include an insulating resin mainly composed of a thermosetting resin. Examples of such thermosetting resins include epoxy resins, cyanate resins, addition polymers of bismaleimides and diamines, phenol resins, resole resins, isocyanates, triallyl isocyanurates, triallyl cyanurates, and vinyl groups. Examples include, but are not limited to, polyolefin compounds. Among these thermosetting resins, an epoxy resin, particularly a polyfunctional epoxy resin is preferable from the viewpoint of balance between performance such as heat resistance and insulation and cost.

  Known epoxy resins can be used in the present invention. For example, phenol novolac type epoxy resin, cresol novolac type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, biphenyl type epoxy resin, biphenyl novolac type epoxy resin, trishydroxyphenylmethane type epoxy resin, Hydrogenated compounds of epoxy compounds containing aromatic rings such as tetraphenylethane type epoxy resins, dicyclopentadiene phenol type epoxy resins, alicyclic epoxy resins and various derivatives of cyclohexene oxide, tetrabromobisphenol A type epoxy resins, etc. Examples thereof include halogen-containing epoxy resins, and these can be used alone or in combination.

  The curing agent used in the present invention is not particularly limited, but a curing agent corresponding to the curing agent can be selected by selecting a thermosetting resin. For example, when an epoxy resin is used as the thermosetting resin, a known epoxy resin curing agent can be used. Examples of such epoxy resin curing agents include polyhydric phenols such as phenol novolak, amine curing agents such as dicyandiamide, diaminodiphenylmethane, and diaminodiphenylsulfone, pyromellitic anhydride, trimellitic anhydride, benzophenonetetracarboxylic acid, and the like. An acid anhydride curing agent or a mixture thereof may be used. Among these, the use of polyhydric phenols such as phenol novolac is particularly preferable from the viewpoint of low water absorption.

  The blending ratio of the epoxy resin curing agent can be used in any ratio in combination with the epoxy resin, but the blending ratio is usually determined so that Tg becomes high. For example, when phenol novolac is used as the epoxy resin curing agent, it is preferable that the epoxy equivalent and the hydroxyl equivalent be 1: 1.

  A semi-cured insulating resin (B stage) is obtained by applying a varnish mainly composed of the above-described insulating resin dissolved in a predetermined solvent to a support with a roll coater or the like, and then drying to a semi-cured state. A sheet can be produced. The insulating resin varnish may be adjusted to an appropriate viscosity and directly laminated on the wiring circuit by a method such as printing or coating, but in the present invention, the insulating resin sheet is formed in a semi-cured state. It is preferable to carry out by laminating. Examples of the support for the insulating resin sheet include polyolefins such as polyethylene and polyvinyl chloride, polyesters such as PET, polycarbonate, and release paper. Among these, it is particularly preferable to use a polyester film in terms of price, heat resistance, dimensional stability, and the like. The thickness of the support is generally 10 to 150 μm. Note that the support may be subjected to a release treatment in addition to the matting and embossing. Furthermore, if necessary, the surface of the insulating resin sheet without the support can be covered with a protective film, and wound into a roll and stored. Examples of the protective film include polyolefins such as polyethylene and polyvinyl chloride, polyesters such as PET, and release paper. The thickness of the protective film is generally 10 to 100 μm. Further, the protective film may be subjected to a releasing treatment in addition to the matting and embossing.

In the present invention, the method of laminating the insulating resin sheet with a vacuum laminator may be a batch type or a continuous type with a roll under reduced pressure, and it is preferable to laminate both surfaces simultaneously. Lamination conditions differ depending on the hot melt viscosity of the insulating resin, the resin thickness, the pattern area of the inner layer circuit board, etc., but generally the pressure bonding temperature is 70-200 ° C., the pressure bonding pressure is 1-10 kgf / cm ² , and 20 Torr. The laminate can be satisfactorily laminated under the following reduced pressure.

  A known inorganic or organic filler can be added to the insulating resin varnish used for forming the insulating layer in the present invention for the purpose of modifying mechanical, thermal, or electrical properties. In order to form a fine pattern, those fillers having a smaller average particle diameter are preferred, and those having an average particle diameter of 3 μm or less are used. The blending ratio varies depending on the selection of the thermosetting resin, and is preferably in the range of 5 to 40 wt% with respect to the entire insulating layer. Examples of the organic filler include epoxy resin powder, melamine resin powder, urea resin powder, guanamine resin powder, and polyester resin powder, and examples of the inorganic filler include silica, alumina, and titanium oxide. Among these, silica fillers are more preferred because they have a low dielectric constant, a low coefficient of linear expansion, and are easy to form anchors by detaching from the insulating resin constituting the insulating layer by surface roughening. ing.

  A thermoplastic resin can be added to the insulating resin varnish used for forming the insulating layer in the present invention. The purpose of adding the thermoplastic resin is to improve the toughness of the resin and to give the insulating layer a tenacity. Usually, a thermosetting resin such as an epoxy resin is excellent in plating adhesion with copper and heat resistance, but has a hard and brittle characteristic and may cause problems such as a resin crack in a thermal shock test. In the present invention, an insulating layer with excellent reliability can be formed by adding a thermoplastic resin such as polyethersulfone, phenoxy resin, or polyimide. As such a thermoplastic resin, it is desirable that it can be dissolved and mixed in the same solvent as the above-mentioned thermosetting resin and curing agent. The blending ratio of the thermoplastic resin is preferably in the range of 10 to 40% of the total resin solid content. This is because when the thermoplastic resin content is 10% by weight or less of the total resin solid content, the toughness effect by the thermoplastic resin tends not to be obtained so much, and when it is 40% by weight or more, sufficient plating adhesion tends not to be obtained. Because it is in.

  The capacitor lower electrode (15) in the present invention is preferably formed by plating. Although depending on the thickness of the dielectric layer (16) formed on the capacitor lower electrode (15) and the size of the capacitor lower electrode itself, the thickness of the capacitor lower electrode is preferably 18 μm or less. When the capacitor lower electrode thickness is 18 μm or more, the dielectric layer is formed on the capacitor lower electrode so as to be larger than the area of the capacitor lower electrode, so that a large step is formed in the dielectric layer on the capacitor lower electrode edge. Even if the surface of the body layer is polished, the surface cannot be sufficiently smoothed, and there remains concern about the connection reliability of the capacitor upper electrode (17) formed on the dielectric layer.

  In the present invention, electrical continuity to the capacitor lower electrode is preferably taken from below the capacitor lower electrode by a via (14). This is because, according to this structure, the capacitance of the capacitor is accurately defined only by the capacitor lower electrode without considering the tolerance of the capacitance due to the influence of the dielectric layer on the wiring circuit. Specifically, a via hole (13) that reaches the lower wiring circuit from the capacitor lower electrode is provided, and filled via plating is applied to the via hole (13) to establish conduction with the lower wiring circuit and to form the capacitor lower electrode (15).

  Further, in the present invention, when the anti-flow prevention pattern (19) of the dielectric material is formed around the capacitor lower electrode (15) as shown in FIGS. 2 and 3, the dielectric layer laminated on and around the capacitor lower electrode is formed. Since the high dielectric constant resin paste used as the body layer (16) is laminated with a uniform thickness, it is preferable. This dielectric material anti-flow pattern (19) is provided around the capacitor lower electrode, especially if it is a material or structure that is not electrically connected to the wiring circuit and does not affect the capacitance of the capacitor. Although there is no limitation, when filled via plating is performed in the same process as the formation of the capacitor lower electrode (FIG. 2C), the flow is prevented because the process is simple and the thickness can be the same as that of the capacitor lower electrode. The effect is large and preferable.

  The high dielectric resin paste used for forming the dielectric layer (16) in the present invention is composed mainly of a thermosetting resin, a curing agent and a high dielectric constant filler. As the thermosetting resin and the curing agent, those similar to those used in the insulating resin varnish can be used. Examples of the high dielectric constant filler include titanates such as barium titanate, strontium titanate, calcium titanate, magnesium titanate, zinc titanate and lead titanate, or calcium zirconate, barium zirconate and zirconate. Various dielectric ceramic compositions mainly composed of a zirconate such as lead can be used.

  In the present invention, the dielectric layer (16) of the capacitor is formed so as to cover the capacitor lower electrode (15). At this time, wiring circuits (11) and electronic elements other than the capacitor lower electrode are usually formed on the insulating layer (12) on which the capacitor lower electrode is formed, and the dielectric layer (16) is formed below these capacitors. It must be partially formed so as not to be applied to a conductive wiring circuit or electronic element other than the electrodes. Specifically, it is preferable to form the capacitor lower electrode and the periphery thereof by a screen printing method capable of patterning with appropriate accuracy.

  In the present invention, polishing is performed for the purpose of smoothing the surface of the dielectric layer (16) formed on the capacitor lower electrode (15). In general, when a dielectric layer is formed by using a high dielectric paste filled with a high dielectric constant filler, the filler on the surface of the dielectric layer is not sufficiently covered with the resin due to the effect of resin curing shrinkage, etc. Becomes worse. Therefore, when the surface layer of the dielectric layer is polished, the filler-rich region is removed, and a smooth dielectric layer surface can be obtained. Examples of the polishing method include buffing with a ceramic or non-woven fabric buff, belt sander polishing with an abrasive belt, etc. Among them, polishing with a non-woven buff with a relatively soft buff is preferable.

  A capacitor upper electrode (17) that covers the capacitor lower electrode (15) and has a large area on the dielectric layer (16) whose surface is adjusted by polishing, and a wiring circuit in the capacitor upper electrode and the multilayer printed wiring board The connection part (18) is formed with a conductive paste (FIG. 1 (e), FIG. 2 (e), FIG. 3 (c)). As a method, screen printing that can be processed with appropriate accuracy and high productivity is preferable.

  The insulating material is laminated again on the capacitor thus manufactured to form an insulating layer, and the capacitor upper electrode or other internal wiring circuit is made conductive, and the above process is repeated once or a plurality of times, so that An electronic component built-in substrate having a capacitor element as an electronic component can be manufactured (FIGS. 1 (f) and 2 (f)).

  EXAMPLES The present invention will be specifically described below with reference to examples and comparative examples, but the present invention is not limited thereto.

First, production examples of the insulating resin sheet and the high dielectric resin paste used in the examples of the present invention are shown. The compositions of the insulating resin varnish and the high dielectric resin paste are as shown in Table 1. The numerical values in Table 1 are parts by weight unless otherwise indicated.
<Insulation resin sheet production example 1>
90 parts by weight of Epicoat 1001 (manufactured by Yuka Shell Epoxy) as an epoxy resin component which is a thermosetting resin, 10 parts by weight of Epicoat 828EL (manufactured by Yuka Shell Epoxy), and phenol novolak (Nippon Kayaku Co., Ltd.) as an epoxy resin curing agent 24.6 parts by weight and 37.4 parts by weight of a phenoxy resin (Phenato YP-50, manufactured by Tohto Kasei Co., Ltd.) as a thermoplastic resin were dissolved in a mixed solvent of cyclohexanone and MEK. To this solution, 40.5 parts by weight of silica filler AEROSIL RY200 (manufactured by Nippon Aerosil Co., Ltd.) and curing catalyst 2-ethyl-4-methylimidazole (manufactured by Tokyo Chemical Industry Co., Ltd.) 0.32 parts by weight are added. After the dispersion, stirring and defoaming were performed to prepare an insulating resin varnish. The insulating resin varnish thus obtained was applied on a 30 μm thick PET support with a roll coater so that the film thickness after drying was 50 μm, and dried at 80 ° C. for 10 minutes. Furthermore, a 20 μm-thick polyethylene protective film was laminated on the insulating resin surface opposite to the support laminate surface to protect the insulating resin surface.
<Insulation resin sheet production example 2>
EPPN-502H (manufactured by Nippon Kayaku Co., Ltd.) 90 parts by weight as an epoxy resin component which is a thermosetting resin, Epicoat 828EL (manufactured by Yuka Shell Epoxy Co., Ltd.) 10 parts by weight, and Kayahard NHN (Nippon Kayaku Co., Ltd.) as an epoxy resin curing agent 99.4 parts by weight and 59.8 parts by weight of polyethersulfone (Sumika Excel 5003P, manufactured by Sumitomo Chemical Co., Ltd.) as a thermoplastic resin were dissolved in a mixed solvent of 4-butyrolactone and N-methyl-2-pyrrolidone. . To this solution, 77.8 parts by weight of silica filler Admafine SO-C1 (manufactured by Admatechs) and 0.78 part by weight of 2-ethyl-4-methylimidazole (manufactured by Tokyo Chemical Industry Co., Ltd.) as a curing catalyst are added and kneaded. After dispersing with a dough roll, stirring and defoaming were performed to prepare an insulating resin varnish. The insulating resin varnish thus obtained was applied on a 30 μm thick PET support with a roll coater so that the film thickness after drying was 50 μm, and dried at 80 ° C. for 10 minutes. Furthermore, a 20 μm-thick polyethylene protective film was laminated on the insulating resin surface opposite to the support laminate surface to protect the insulating resin surface.
<Production Example 1 of High Dielectric Resin Paste>
EPPN-502H (manufactured by Nippon Kayaku Co., Ltd.) 90 parts by weight as an epoxy resin component which is a thermosetting resin, Epicoat 828EL (manufactured by Yuka Shell Epoxy Co., Ltd.) 10 parts by weight, and Kayahard NHN (Nippon Kayaku Co., Ltd.) as an epoxy resin curing agent 99.4 parts by weight were dissolved in cyclohexanone. To this solution was added 1801.6 parts by weight of barium titanate (Fuji Titanium Industry Co., Ltd.) as a high dielectric constant filler, 0.78 parts by weight of 2-ethyl-4-methylimidazole (Tokyo Chemical Industry Co., Ltd.) as a curing catalyst, After dispersing with a kneading roll, stirring and defoaming were performed to prepare a high dielectric resin paste. After applying and curing this high dielectric resin paste on a polyimide film, the relative dielectric constant at 1 MHz was measured with an LCR meter to be 51.
<Production Example 2 of High Dielectric Resin Paste>
90 parts by weight of Epototo YDCN-703 (manufactured by Toto Kasei Co., Ltd.) as an epoxy resin component which is a thermosetting resin, 10 parts by weight of Epototo YD-128 (manufactured by Toto Kasei Co., Ltd.), phenol novolak (Nippon Kayaku Co., Ltd.) as an epoxy resin curing agent 53.3 parts by weight were dissolved in γ-butyllactone. To this solution, 1417.5 parts by weight of strontium titanate (manufactured by Fuji Titanium Industry Co., Ltd.) as a high dielectric constant filler, 0.78 parts by weight of 2-ethyl-4-methylimidazole (manufactured by Tokyo Chemical Industry Co., Ltd.) as a curing catalyst, After dispersing with a kneading roll, stirring and defoaming were performed to prepare a high dielectric resin paste. After applying and curing this high dielectric resin paste on a polyimide film, the relative dielectric constant at 1 MHz was measured with an LCR meter and found to be 12.

[Example 1]
On the core substrate (10) (core thickness 0.8 mm) on which the wiring circuit (11) is formed (FIG. 1 (a)), the insulating resin sheet produced in Production Example 1 of the insulating resin sheet is applied with a protective film. It peeled off and it laminated by the temperature of 130 degreeC and the pressure of 3 kgf / cm < ² > with the vacuum laminator. After cooling to room temperature and peeling off the insulating resin support, the insulating resin was cured by heating in an oven at 170 ° C. for 30 minutes to obtain an insulating layer (12). After this, a predetermined via hole forming portion was drilled with a UV-YAG laser (FIG. 1 (b)), surface roughening with alkaline permanganate was performed, and the via hole (13) was formed by panel-filled via plating. Electrical connection and formation of the capacitor lower electrode (15) were performed (FIG. 1 (c)). The design of the capacitor lower electrode was a square shape with a side of 2 mm.

  On the capacitor lower electrode (15) formed as described above, the high dielectric resin paste produced in Production Example 1 of the high dielectric resin paste is screen-printed in a square shape with a thickness of 20 μm and a side of 6 mm, and the dielectric layer (16) was formed so as to cover the capacitor lower electrode with a larger area than the capacitor lower electrode (FIG. 1D). As the screen plate, a stainless steel plate (manufactured by Tokyo Process Service Co., Ltd.) having a 200 mesh and emulsion thickness of 15 μm was used. Thereafter, after drying in an oven at 80 ° C. for 30 minutes, the dielectric layer was cured by heating in an oven at 180 ° C. for 1 hour. Further, the surface of the dielectric layer was polished with nonwoven fabric buffs # 320, # 600, # 1000 (manufactured by Kakuda Brush Co.). On the dielectric layer (16) thus formed, conductive silver paste XA-436 (manufactured by Fujikura Kasei Co., Ltd.) is printed in a rectangular shape of 4 mm in length and 8 mm in width to form the capacitor upper electrode (17). At the same time, the capacitor upper electrode and the conductive pattern on the insulating resin were electrically connected (FIG. 1 (e)).

Furthermore, the protective resin sheet was peeled off again from the insulating resin sheet produced in Production Example 1 of the insulating resin sheet on this substrate, and laminated with a vacuum laminator at a temperature of 130 ° C. and a pressure of 3 kgf / cm ² . After cooling to room temperature and peeling off the insulating resin support, the insulating resin was cured by heating in an oven at 170 ° C. for 30 minutes to obtain an insulating layer (12). Via holes (13) were formed by UV-YAG laser in predetermined via hole forming portions, vias were electrically connected by panel-filled via plating, and conductive circuits (11) and capacitor lower electrodes (15) were formed by etching. By repeating the above steps twice, a build-up two-layer electronic component built-in substrate was manufactured (FIG. 1 (f)). Note that the capacitor lower electrode was not formed when the surface conductor circuit was formed.
[Example 2]
Build-up two-layer electronic component built-in substrate in the same manner as in Example 1 except that the insulating resin sheet produced in Production Example 1 of the insulating resin sheet and the high dielectric resin paste produced in Production Example 2 of the high dielectric resin paste were used Manufactured.
[Example 3]
Build-up two-layer electronic component built-in substrate in the same manner as in Example 1 except that the insulating resin sheet produced in Production Example 2 of the insulating resin sheet and the high dielectric resin paste produced in Production Example 1 of the high dielectric resin paste were used Manufactured.
[Example 4]
Build-up two-layer electronic component built-in substrate in the same manner as in Example 1 except that the insulating resin sheet produced in Production Example 2 of the insulating resin sheet and the high dielectric resin paste produced in Production Example 2 of the high dielectric resin paste were used Manufactured.
[Example 5]
On the core substrate (10) (core thickness 0.8 mm) on which the wiring circuit (11) is formed (FIG. 2 (a)), the insulating resin sheet produced in Production Example 1 of the insulating resin sheet is coated with a protective film. It peeled off and it laminated by the temperature of 130 degreeC and the pressure of 3 kgf / cm < ² > with the vacuum laminator. After cooling to room temperature and peeling off the insulating resin support, the insulating resin was cured by heating in an oven at 170 ° C. for 30 minutes to obtain an insulating layer (12). After this, a predetermined via hole forming portion was drilled with a UV-YAG laser (FIG. 2 (b)), surface roughening with alkaline permanganate was performed, and the via hole (13) was formed by panel-filled via plating. Electrical connection and capacitor lower electrode (15) and a dielectric material flow stop pattern (19) were formed (FIG. 2C). The design of the capacitor lower electrode was a square shape with a side of 2 mm.

  On the capacitor lower electrode (15) and the dielectric material anti-flow pattern (19) formed as described above, the high dielectric resin paste produced in Production Example 1 of the high dielectric resin paste has a thickness of 20 μm and a side of 6 mm. The dielectric layer (16) was formed so as to cover the capacitor lower electrode and the anti-flow prevention pattern with a larger area than the capacitor lower electrode by screen printing in a square shape (FIG. 2D). As the screen plate, a stainless steel plate (manufactured by Tokyo Process Service Co., Ltd.) having a 200 mesh and emulsion thickness of 15 μm was used. Thereafter, after drying in an oven at 80 ° C. for 30 minutes, the dielectric layer was cured by heating in an oven at 180 ° C. for 1 hour. Further, the surface of the dielectric layer was polished with nonwoven fabric buffs # 320, # 600, # 1000 (manufactured by Kakuda Brush Co.). On the dielectric layer (16) thus formed, conductive silver paste XA-436 (manufactured by Fujikura Kasei Co., Ltd.) is printed in a rectangular shape of 4 mm in length and 8 mm in width to form the capacitor upper electrode (17). At the same time, the capacitor upper electrode and the conductive pattern on the insulating resin were electrically connected (FIG. 2E).

Furthermore, the protective resin sheet was peeled off again from the insulating resin sheet produced in Production Example 1 of the insulating resin sheet on this substrate, and laminated with a vacuum laminator at a temperature of 130 ° C. and a pressure of 3 kgf / cm ² . After cooling to room temperature and peeling off the insulating resin support, the insulating resin was cured by heating in an oven at 170 ° C. for 30 minutes to obtain an insulating layer (12). A via hole (13) is formed by a UV-YAG laser in a predetermined via hole forming portion, the via is electrically connected by panel-filled via plating, and a conductor circuit (11), a capacitor lower electrode (15) and a flow prevention are prevented by etching. A pattern (19) was formed. By repeating the above process twice, a build-up two-layer electronic component built-in substrate was manufactured (FIG. 2F). Note that the capacitor lower electrode was not formed when the surface conductor circuit was formed.

A 0.8 mm double-sided copper-clad laminate serving as a core substrate was etched to form a wiring circuit and a capacitor lower electrode. The capacitor lower electrode had a square shape with a side of 4 mm, and the wiring connected to the capacitor lower electrode was formed on the same layer as the electrode by etching. On the capacitor lower electrode thus formed, the high dielectric resin paste produced in Production Example 1 of the high dielectric resin paste is screen-printed in a square shape having a thickness of 20 μm and a side of 6 mm, and the dielectric layer is formed into a capacitor. The capacitor lower electrode was formed so as to cover a larger area than the lower electrode. The same screen plate as in Example 1 was used. Thereafter, after drying in an oven at 80 ° C. for 30 minutes, the dielectric layer was cured by heating in an oven at 180 ° C. for 1 hour. On the dielectric layer formed in this manner, a square-shaped capacitor upper electrode having a side of 2 mm with the same conductive silver paste as in Example 1, and a connection wiring portion (line width 0) of the capacitor upper electrode to the wiring circuit .2 mm) was printed and formed. Subsequent steps were performed in the same manner as in Example 1 except for the sizes of the upper and lower electrodes, and a build-up two-layer electronic component built-in substrate was manufactured.
[Comparative Example 2]
The copper foil of the 0.8mm double-sided copper-clad laminate used as the core substrate was etched to form the wiring circuit and the capacitor lower electrode, and the built-in capacitor lower electrode of the second build-up layer was the same instead of the via hole directly below A built-up two-layer electronic component built-in substrate was produced in the same manner as in Example 1 except that the wiring circuit pattern formed in the plane was electrically connected in a plane.

The evaluation method of the material produced as described above was as follows. The results are shown in Table 2.
<Capacitance>
With the evaluation board | substrate produced in Examples 1-5 and Comparative Examples 1-2, the electrostatic capacitance of the capacitor | condenser which the electronic component built-in board | substrate incorporates was measured with the material analyzer. The design value of the capacitance is a value calculated from the dielectric constant and thickness of the dielectric and the effective area of the electrode. The electrode area is all designed to be ² mm × 2 mm 4 mm ² .

It is explanatory drawing which shows an example of the manufacturing method of one form of the electronic component built-in board | substrate by this invention. It is explanatory drawing which shows an example of the manufacturing method of the other form of the electronic component built-in board | substrate by this invention. It is explanatory drawing which looked at an example of the manufacturing method of the other form of the electronic component built-in substrate by this invention from the top. It is explanatory drawing which looked at an example of the conventional electronic component built-in board | substrate from the top. DESCRIPTION OF SYMBOLS 10 ... Core board | substrate 11 ... Wiring circuit 12 ... Insulating layer 13 ... Via hole 14 (being reached to lower wiring circuit) ... Via 15 connected with lower wiring circuit ... Capacitor lower electrode 16 ... Dielectric layer 17 ... Upper part of capacitor Electrode 18 ... Connection portion 19 with wiring circuit in multilayer printed wiring board ... Dielectric material flow prevention pattern 20 ... Electronic component built-in substrate 21 ... Conductor wiring circuit pattern for capacitor lower electrode

Claims (9)

An electronic component-embedded board in which a capacitor is built in a multilayer printed wiring board formed by alternately forming insulating layers and conductor layers,
A capacitor lower electrode is provided on a part of any of the insulating layers forming the multilayer printed wiring board,
A dielectric layer is provided so as to cover the capacitor lower electrode,
A substrate with a built-in electronic component, wherein a capacitor upper electrode having a larger area than the capacitor lower electrode is provided on the dielectric layer.   2. The electronic component built-in substrate according to claim 1, wherein the capacitor lower electrode is formed on a via formed so that the lower electrode is electrically connected to a wiring circuit below the insulating layer.   3. The electronic component built-in substrate according to claim 1, wherein a pattern for preventing flow of a dielectric material forming the dielectric layer is formed around the capacitor lower electrode. A method for manufacturing an electronic component built-in substrate in which a capacitor is embedded in a multilayer printed wiring board formed by alternately forming insulating layers and conductor layers, the method including the following steps.
a. Providing a capacitor lower electrode on a part of any insulating layer forming the multilayer printed wiring board;
b. A step of providing a dielectric layer by screen printing a high dielectric resin paste mainly composed of a thermosetting resin so as to cover the capacitor lower electrode on a part of the insulating layer;
c. Forming a capacitor upper electrode occupying a larger area than the capacitor lower electrode, and a connecting portion between the capacitor upper electrode and the wiring circuit in the multilayer printed wiring board by a conductive paste; Instead of step a according to claim 4,
d. A step of forming a via hole for establishing electrical connection with a wiring circuit below the insulating layer in any insulating layer forming the multilayer printed wiring board;
And e. Applying via filling to the via hole and forming a via and a capacitor lower electrode that are electrically connected to the lower wiring circuit;
5. The method for manufacturing an electronic component built-in substrate according to claim 4, comprising the following two steps. Between step b and step c according to claim 4,
f. Performing mechanical polishing of the dielectric layer;
The method for manufacturing an electronic component-embedded substrate according to claim 4 or 5, wherein: Before step a according to claim 4 or before step d according to claim 5,
g. Forming an insulating layer by laminating an insulating resin sheet mainly composed of a thermosetting resin on an insulating substrate on which a wiring circuit is formed;
The method of manufacturing an electronic component built-in substrate according to claim 4, wherein: Instead of step a according to claim 4,
h. A step of providing a capacitor lower electrode on a part of any of the insulating layers forming the multilayer printed wiring board, and forming a dielectric layer anti-flow pattern around the capacitor lower electrode;
The method for manufacturing an electronic component built-in substrate according to claim 4, comprising: Instead of step e according to claim 5,
i. Applying via filling to the via hole, forming a via and a capacitor lower electrode conductive with the lower wiring circuit, and forming a dielectric layer anti-flow pattern around the capacitor lower electrode;
The method of manufacturing an electronic component built-in substrate according to claim 5, comprising: