JP2004146495A

JP2004146495A - Built-in chip capacitor for printed wiring board, and element-containing board built therein

Info

Publication number: JP2004146495A
Application number: JP2002308158A
Authority: JP
Inventors: Mitsuteru Endo; 遠藤　充輝; Kenji Kawamoto; 河本　憲治
Original assignee: Toppan Printing Co Ltd
Current assignee: Toppan Inc
Priority date: 2002-10-23
Filing date: 2002-10-23
Publication date: 2004-05-20

Abstract

<P>PROBLEM TO BE SOLVED: To develop a chip capacitor assuring a static capacitance similar to that of the existing chip capacitor while it is a laminated thin ceramic capacitor suitable for use as a capacitor built in between interlayer insulating layers in a multilayer printed wiring board, and to provide an element-containing board with the thin chip capacitor built therein and a method for manufacturing the same. <P>SOLUTION: The built-in chip capacitor for a printed wiring board is thinner than an interlayer insulating layer. More specifically, its thickness t falls in a range covered by 10μm≤t≤100μm, its length L in a range covered by 1mm≤L≤10mm and its width W in a range covered by 1mm≤W≤10mm. Electrodes are provided on its side faces for connection to the outside. The thickness t<SB>z</SB>of an insulating layer that contains the chip capacitor is in a range covered by t+10μm≤t<SB>z</SB>≤t+50μm relative to the thickness t of the chip capacitor. For the element-containing wiring board, insulating layers are formed by thermocuring a liquid insulating resin. The method results in a thin chip capacitor assuring a static capacitance similar to that of the existing chip capacitor despite its thinness. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は多層プリント配線板に内蔵可能なチップコンデンサ、及び、該チップコンデンサを内蔵した素子内蔵基板とその製造方法に関するものである。
【０００２】
【従来の技術】
近年、電子機器の高性能化、小型化の要求に伴い回路部品の高密度化、高機能化が強まっている。そのため、プリント配線板に電子部品を実装する場合においてはその実装効率を高めるためにコンデンサ（Ｃ）、レジスタ（Ｒ）、インダクタ（Ｌ）等の受動部品を基板内に内蔵した構造のプリント配線板が注目されている。
【０００３】
例えば、プリント基板に設けた透孔内にリードレスの回路部品を埋設した特開昭５４−３８５６１号公報、絶縁基板に設けた貫通孔内にセラミックコンデンサ等の受動部品を埋設した特公昭６０−４１４８０号公報、半導体素子のバイパスコンデンサをプリント基板の孔に埋設した特開平４−７３９９２号公報及び特開平５−２１８６１５号公報等が開示されている。
【０００４】
また、セラミック配線基板に設けたビアホール内に導電性物質と誘電性物質を充填して同時焼成した特開平８−２２２６５６号公報、有機系絶縁基板に設けた貫通孔に電子部品形成材料を埋め込んだ後、固化させてコンデンサや抵抗器を形成した特開平１０−５６２５１号公報等が開示されている。
【０００５】
上記従来の開示技術はいずれも二つの方式に大別できる。すなわちその一つは配線基板に設けられた貫通孔にチップ抵抗器またはチップコンデンサ等の既に完成されたリードレス部品を埋設した後、このリードレス部品の外部接続用電極と配線基板上の導体回路パターンとを導電性ペーストまたははんだ付けによって接続するものである。また、他の一つは有機系配線基板の場合、配線基板に設けた貫通孔にコンデンサ等の電子部品形成材料を埋め込み、固化させることによって所望のコンデンサとした後、その上下の端面にめっきを施して電極を形成し、電子部品内蔵配線基板を形成する。また、無機系配線基板の場合は、セラミックグリーンシートに設けられたビアホール内に誘電体ペーストや導電性ペーストを充填した後、高温で焼成することにより、所望のコンデンサを内蔵した配線基板を形成するというものである。
【０００６】
しかしながら、これらの貫通孔を利用して焼成あるいは固化したコンデンサは単層であるため大容量を得ることは困難である。一方、あらかじめ大容量が確保されているチップコンデンサ等を貫通孔へ埋設、実装する場合は、現行で最小サイズの０６０３チップを用いたとしても０．３ｍｍあるいは０．６ｍｍの層厚みが伴うため、薄い多層プリント配線板を実現することは困難であった。
【０００７】
また、チップ部品単体でみた場合、市場には１００５、０６０３に代表される側面に電極が構成されたチップコンデンサが代表的であり、それらを基板に内蔵した例は、特開平１１−２２０２６２号公報等に既に提案されているが、内蔵用に特性、形状を考慮したチップコンデンサ、またそれを基板に内蔵させた例はほとんど報告されていない。数少ない例として特許文献１に、転写法を利用してアルミナ、エポキシ樹脂を主成分とするコンポジット材料より成るシート状基材（Ｂステージ）中に長さＬ及び幅Ｗに比べて厚みｔを小さくした、多層プリント配線板の絶縁層への埋め込みに適した形状の受動部品を埋め込む方法が開示されている。
【０００８】
特許文献１で開示されたシート状基材を用いた方法では、Ｂステージ状態のコンポジット材料が流動性に乏しいため、ｔ≧１０μｍ以上の積層チップコンデンサを埋め込むことは難しく、特に静電容量を確保するために誘電体の面積を大きくすると埋め込み性は悪化する。したがって、この方法では比較的静電容量の小さなコンデンサしか埋め込むことができない。また、むき出しのチップを真空プレスで埋没させるためチップ本体及びその周辺部へのダメージや樹脂の染み出しによる内蔵基板表面の平滑性の悪化等が懸念される。
また、チップコンデンサの上下端面に電極を形成してしまうと、基板上の導電性ペーストや導体回路パターン上へチップコンデンサを配置・実装し、絶縁層を形成して埋め込んだ際に、上部の端面から導通をとるためにコンデンサ上にビアを形成したり、絶縁層を研磨するなどの処理をしなくてはならない。コンデンサの真上にコンデンサを傷つけないようにビアホールを形成するのは技術的に困難であり、また端面を出すために絶縁層を研磨すると、内部のコンデンサ等の素子を傷めるおそれがある。
【０００９】
【特許文献１】
特開２００２−７６６３７号公報（第７頁、段落３４及び段落４２）
【００１０】
【発明が解決しようとする課題】
本発明の目的は、多層プリント配線板の層間絶縁層に内蔵するのに適した薄型積層セラミックコンデンサでありながら、既存のチップコンデンサと同等の静電容量を確保することが可能なチップコンデンサを開発することにある。本発明者らは鋭意検討した結果、プリント配線板の層間絶縁層に内蔵できる厚み、具体的には厚みｔが１０μｍ≦ｔ≦１００μｍであり、長さＬ及び幅Ｗが１ｍｍ≦Ｌ≦１０ｍｍ、１ｍｍ≦Ｗ≦１０ｍｍのチップコンデンサであれば、既存チップコンデンサと同等の静電容量を確保でき、尚かつ多層プリント配線板の層間絶縁層に埋没可能であることがわかった。また、電極はチップコンデンサの側面に形成し、チップコンデンサを基板に実装する際には導体回路パターンが設けられていない場所へ配置するとより薄い層間絶縁層でも埋没が可能となる。さらに、絶縁層の形成に液状絶縁性樹脂を用いると容易に本発明のチップコンデンサを絶縁層へ埋没させることでき、液状絶縁性樹脂を硬化させた後研磨を必要とせず、その上へ樹脂付き銅箔を真空プレスするため、チップコンデンサ等内蔵素子へのダメージが無く、また容易に平滑な導体層を形成することが可能である。
【００１１】
【課題を解決するための手段】
上記目的を達成するため本発明は成されたものであり、請求項１に係る第１の発明は、厚みｔが、自身を内蔵するプリント配線板の層間絶縁層よりも薄く、外部接続用電極が側面に設けられたことを特徴とするプリント配線板内蔵用チップコンデンサである。
【００１２】
請求項２に係る第２の発明は、厚みｔが１０μｍ≦ｔ≦１００μｍ、長さＬが１ｍｍ≦Ｌ≦１０ｍｍ、及び幅Ｗが１ｍｍ≦Ｗ≦１０ｍｍの範囲内であり、２つの外部接続用電極が側面に設けられたことを特徴とする請求項１記載のプリント配線板内蔵用チップコンデンサである。
【００１３】
請求項３に係る第３の発明は、前記チップコンデンサが複数のセラミック誘電体層と内部電極を交互に積層した構成であることを特徴とする請求項１または２記載のプリント配線板内蔵用チップコンデンサである。
【００１４】
請求項４に係る第４の発明は、前記セラミック誘電体層が、６００℃以上で焼成させたチタン酸バリウム、チタン酸ストロンチウム、ジルコン酸カルシウム、ジルコン酸バリウムのいずれかもしくはその混合物を主成分とした誘電体セラミック組成物により形成されたことを特徴とする請求項１から３のいずれかに記載のプリント配線板内蔵用チップコンデンサである。
【００１５】
請求項５に係る第５の発明は、５角柱以上の多角柱、円柱、あるいは一部または全部の角を丸めた形状の多角柱のうちいずれか一つの形態をとることを特徴とする請求項１から４のいずれかに記載のプリント配線板内蔵用チップコンデンサである。
【００１６】
請求項６に係る第６の発明は、導体回路パターンが形成された内層回路基板に絶縁層を積層してなる多層プリント配線板において、前記内層回路基板上で導体回路パターンが形成されていない部分へ、請求項１から５のいずれかに記載のチップコンデンサを装填していることを特徴とする素子内蔵基板である。
【００１７】
請求項７に係る第７の発明は、請求項１から５のいずれかに記載のチップコンデンサの外部接続用電極と、前記導体回路パターンにより形成された配線パッドを電気的に接続したことを特徴とする請求項６記載の素子内蔵基板である。
【００１８】
請求項８に係る第８の発明は、請求項１から５のいずれかに記載のチップコンデンサの外部接続用電極と電気的に接続された配線パッドのうちどちらか一方または両方が、ビアホールランドの形成された導体回路パターンに接続しており、前記ビアホールは絶縁層を介し当該チップコンデンサの積層された層と異なる層にある導体回路パターンと電気的に接続していることを特徴とする請求項６または７に記載の素子内蔵基板である。
【００１９】
請求項９に係る第９の発明は、前記チップコンデンサを内蔵した絶縁層の厚みｔ_ｚがチップコンデンサの厚みｔに対してｔ＋１０μｍ≦ｔ_ｚ≦ｔ＋５０μｍの範囲にあることを特徴とする請求項６から８のいずれかに記載の素子内蔵基板である。
【００２０】
請求項１０に係る第１０の発明は、請求項６から９のいずれかに記載の絶縁層は液状絶縁性樹脂を熱硬化させたものであり、前記液状絶縁性樹脂が少なくとも
（Ａ）熱硬化性樹脂
（Ｂ）硬化剤
（Ｃ）無機または有機フィラー
を含むものであることを特徴とする請求項６から９のいずれかに記載の素子内蔵基板である。
【００２１】
請求項１１に係る第１１の発明は、前記（Ａ）熱硬化性樹脂が、少なくとも
（Ａ_１）軟化点６０℃以上の固形多官能エポキシ樹脂
（Ａ_２）常温で液状の多官能エポキシ樹脂
を含むものであることを特徴とする請求項６から１０のいずれかに記載の素子内蔵基板である。
【００２２】
請求項１２に係る第１２の発明は、前記液状絶縁性樹脂が（Ｄ）熱可塑性樹脂を含むものであることを特徴とする請求項６から１１のいずれかに記載の素子内蔵基板である。
【００２３】
請求項１３に係る第１３の発明は、導体回路パターンが形成された内層回路基板に絶縁層を積層してなる多層プリント配線板の製造工程において、請求項１から４のいずれかに記載のチップコンデンサを内蔵した絶縁層上に真空プレスによって樹脂付き銅箔を積層する工程と、加熱により樹脂付き銅箔の樹脂と前記絶縁層とを一体化させる工程を含むことを特徴とする請求項６から１２のいずれかに記載の素子内蔵基板の製造方法である。
【００２４】
請求項１４に係る第１４の発明は、前記樹脂付き銅箔の樹脂が少なくとも
（Ｅ）熱硬化性樹脂
（Ｆ）硬化剤
（Ｇ）無機または有機フィラー
を含むものであることを特徴とする請求項１３に記載の製造方法で製造された素子内蔵基板である。
【００２５】
請求項１５に係る第１５の発明は、前記（Ｅ）熱硬化性樹脂が、少なくとも
（Ｅ_１）軟化点６０℃以上の固形多官能エポキシ樹脂
（Ｅ_２）常温で液状の多官能エポキシ樹脂
を含むものであることを特徴とする請求項１４に記載の素子内蔵基板である。
【００２６】
請求項１６に係る第１６の発明は、前記樹脂付き銅箔の樹脂は、残存溶剤量３％以内であることを特徴とする請求項１４または１５のいずれかに記載の素子内蔵基板である。
【００２７】
【発明の実施の形態】
本発明における実施の形態の１例について図面を用いて簡単に説明する。図１（ｂ）に示すように本発明におけるプリント配線板内蔵用チップコンデンサは、複数のセラミック誘電体層（１）と内部電極（２）が交互に積層された構造のセラミック積層体（３）の両端面に外部接続用電極（４）、及びニッケル、銅などのめっき第一層（５）、はんだ・錫などのめっき第二層（６）が形成されており、既存のチップコンデンサと基本的構造は同一であるが、基板上に熱硬化型接着剤で固定する必要性からチップコンデンサの下面をあらかじめエポキシ樹脂等で穴埋めして平滑にしておくことが好ましい。
【００２８】
既存のチップコンデンサは、目的とする静電容量にもよるが、通常誘電体層及び内部電極を５０層以上積層することにより、小型であっても充分な静電容量を確保している。しかしながら、現在流通しているチップコンデンサは最小の０６０３（（株）村田製作所製）においても３００μｍの厚みを有するため、多層プリント配線板に搭載する場合、層間絶縁層ではなく層間厚の厚いコア層（内層回路基板）に埋め込むより方法が無かった。本発明におけるプリント配線板内蔵用チップコンデンサではセラミック誘電体層及び内部電極の積層数を２０層以下にして、チップコンデンサ（１０）の厚みｔを層間絶縁層よりも薄く、具体的には１０μｍ≦ｔ≦１００μｍとし、多層プリント配線板の層間絶縁層へ埋め込み可能にした。厚みｔは１０μｍ≦ｔ≦８０μｍの範囲とすると、より埋め込みやすく理想的な大きさである。また、コンデンサの長さＬを１ｍｍ≦Ｌ≦１０ｍｍ、及び幅Ｗを１ｍｍ≦Ｗ≦１０ｍｍとし、既存のチップコンデンサに比べて面積を大きくした。その結果、誘電体層１層あたりの静電容量が増し、誘電体層の積層数を減らしたことによる静電容量の低下が相殺され、既存のチップコンデンサと同等の静電容量を得ることができた。
【００２９】
次に、本発明におけるプリント配線板内蔵用チップコンデンサの製造方法について図１に従い製造工程順に説明する。まず、セラミック積層体を以下に示す手順に従って形成する。誘電体セラミック組成物をスラリー化してシート状とした誘電性セラミックシート（グリーンシート）を用意し、その一面にＰｔ、Ｐｄ等のペーストをスクリーン印刷等で塗布し、内部電極（２）を形成する。内部電極を形成された誘電性セラミックシートは必要枚数積層され、最後に内部電極を形成していない誘電性セラミックシートを積層体の外側となっている内部電極上に積層して圧着する。このとき内部電極と誘電性セラミックシートからなる積層体の形状が多角柱や円柱状など、角が鈍角であるか丸められていると焼成後に割れや欠けに強いセラミックコンデンサとすることができる。その後、この内部電極と誘電性セラミックシートからなる積層体を所定の温度にて焼成し、セラミック積層体（３）が形成される。
【００３０】
次にセラミック積層体（３）の両端面に、内部電極（２）と接続するように、２つの外部接続用電極（４ａ）が形成される。この外部接続用電極（４ａ）の材料としては、内部電極と同じ材料を使用することができる。また、銀・パラジウム・銀−パラジウム合金・銅・銅合金等が使用可能である。また、これらの金属粉末にＢ_２Ｏ_３−ＳｉＯ_２−ＢａＯ系ガラス、Ｌｉ_２Ｏ−ＳｉＯ_２−ＢａＯ系ガラス等のガラスフリットを添加したものも使用される。外部接続用電極（４ａ）は、材料となる金属粉末ペーストを焼成により得たセラミック積層体（３）に塗布して焼き付けることで形成されるが、焼成前に塗布してセラミック積層体と同時に形成してもよい。この後、外部接続用電極（４ａ）上にニッケル・銅等のめっきを施し、めっき第一層（４ｂ）を形成する。最後にこのめっき第一層の上にはんだ・錫等のめっき第二層（４ｃ）を形成することで本発明におけるプリント配線板内蔵用チップコンデンサ（１０）が製造される。
【００３１】
本発明のプリント配線板内蔵用チップコンデンサ（１０）の形状を、５角柱以上の多角柱、楕円柱も含む円柱あるいは多角柱の角を丸めた形状のように、角が鈍角であるか丸められている形状とすることで、薄型にも関わらず破損しにくいセラミックチップコンデンサとすることができる。
【００３２】
本発明で用いられる誘電体セラミック層の組成は特に限定されるものではないが、例えばチタン酸バリウム，チタン酸ストロンチウム，チタン酸カルシウム，チタン酸マグネシウム，チタン酸亜鉛，チタン酸鉛等のチタン酸塩、あるいはジルコン酸カルシウム，ジルコン酸バリウム，ジルコン酸鉛等のジルコン酸塩等を主成分とした種々の誘電体セラミック組成物を使用することができる。
【００３３】
また、本発明で用いられる内部電極としては、Ｐｔ，Ｐｄといった貴金属が使用できる他、還元性雰囲気中で誘電性セラミックシートの積層体を焼成させる場合には、Ｎｉ，Ｎｉ合金，Ｃｕ，Ｃｕ合金等の卑金属も用いることができる。尚、内部電極を形成する方法としては、例えばスクリーン印刷や蒸着、めっき等あるが、いずれの方法で形成しても構わない。
【００３４】
以下、本発明における素子内蔵基板の製造方法の一例について図面を参照して説明する。まず、図３（ａ）に示すようにあらかじめ所定のスルーホールが形成されている両面銅貼積層板（１４）を用意し、表層の銅をエッチングして導体回路パターン（１５）を形成する（図３（ｂ））。このようにして作製された内層回路基板（１６）の所定の位置に、本発明におけるプリント配線板内蔵用チップコンデンサ（１０）を接着剤により固定する（図３（ｃ））。ここでいう所定の位置とは図３（ｃ）に示すように、コア基材（１１）上でチップコンデンサの外部接続用電極（４ａ）を接続することになる配線パッドの間、あるいは図４（ｊ）に示すように層間絶縁層（２３）上（つまり導体回路パターン（１５）の形成されていない箇所）である。また接着剤は熱硬化型の接着剤であると加工しやすく硬化後の強度も満足のいくものとなる。さらに、本発明のチップコンデンサ側面の外部接続用電極（４ａ）とコア基材（１１）上あるいは層間絶縁層（２３）上に形成された配線パッドを導電性ペースト（１７）、はんだ等により電気的に接続する（図３（ｄ））。
【００３５】
次に、前記内層回路基板（１６）上に、本発明のチップコンデンサ（１０）を内蔵した絶縁層（１９）の厚みｔ_ｚが当該チップコンデンサの厚みｔに対してｔ＋１０μｍ≦ｔ_ｚ≦ｔ＋５０μｍの範囲に入るように絶縁層（１９）を形成し、当該チップコンデンサを絶縁層に埋め込む（図３（ｅ））。このような範囲で厚みを規定するのは、絶縁層が薄すぎるとコンデンサが露出してしまい樹脂付き銅箔（２２）を積層する際にコンデンサへのダメージが心配され、厚すぎると最終的な基板厚みが厚くなりすぎてしまうためである。絶縁層（１９）の形成には液状絶縁性樹脂を塗布し、加熱硬化することが好ましい。液状絶縁性樹脂は流動性が高いので厚みのあるチップコンデンサ（１０）や導体回路パターン（１５）を効率よく埋め込むことができる。
【００３６】
さらに樹脂付き銅箔（２２）を真空プレスにより積層し、加熱により絶縁層（１９）と樹脂付き銅箔の樹脂（２１）とを一体硬化させて導体層及び層間絶縁層（２３）を形成する（図３（ｆ））。樹脂付き銅箔の銅箔（２０）はレーザー加工で貫通し易い厚み１０μｍ程度の薄いものを使用するのが好ましい。ＵＶ−ＹＡＧレーザーにより所定の位置にビアホールを形成し（図３（ｇ））、デスミア・無電解めっき・パネルめっきを行って、内層回路基板（１６）上の導体回路パターン（１５）とここで設けたビルドアップ層の導体層（２５）を電気的に接続するとともに導体層を所定の厚さにし（図４（ｈ））、この導体層（２５）をエッチングすることで次の層の導体回路パターン（１５）を形成する（図４（ｉ））。以上の工程を複数回繰り返すことにより多層プリント配線板の層間絶縁層（２３）内に本発明のチップコンデンサ（１０）が内蔵された素子内蔵基板（２６）を製造する事ができる（図３（ｊ））。
【００３７】
本発明で用いる液状絶縁性樹脂及び樹脂付き銅箔の樹脂（２１）（接着層）は、熱硬化性樹脂を主成分として成る。例えば、エポキシ樹脂、シアネート樹脂類、ビスマレイミド類とジアミンとの付加重合物、フェノール樹脂、レゾール樹脂、イソシアネート、トリアリルイソシアヌレート、トリアリルシアヌレート及びビニル基含有ポリオレフィン化合物等があげられるが、これらに限定されない。これら熱硬化性樹脂の中でも耐熱性、絶縁性等の性能とコストとのバランスからエポキシ樹脂、特に多官能エポキシ樹脂が好ましい。
【００３８】
本発明で使用されるエポキシ樹脂は公知のものを用いることができる。例えばフェノールノボラック型エポキシ樹脂、クレゾールノボラック型エポキシ樹脂、ビスフェノールＡ型エポキシ樹脂、ビスフェノールＦ型エポキシ樹脂、ビスフェノールＳ型エポキシ樹脂、ビフェニル型エポキシ樹脂、ビフェニルノボラック型エポキシ樹脂、トリスヒドロキシフェニルメタン型エポキシ樹脂、テトラフェニルエタン型エポキシ樹脂、ジシクロペンタジエンフェノール型エポキシ樹脂等の芳香族環を含むエポキシ類化合物の水素添加化合物、脂環式エポキシ樹脂やシクロヘキセンオキシドの各種誘導体、テトラブロモビスフェノールＡ型エポキシ樹脂等の含ハロゲンエポキシ樹脂等があげられ、これらを単独もしくは混合して用いることができる。
【００３９】
熱硬化性樹脂としてこれらエポキシ樹脂を用いる際には、軟化点が６０℃以上で常温では固形である多官能エポキシ樹脂と、常温で液状となる多官能エポキシ樹脂の、物性の異なる２種類のエポキシ樹脂を混合して用いることが好ましい。軟化点が６０℃以上のエポキシ樹脂を用いるのは、液状絶縁樹脂及び樹脂付き銅箔の樹脂に、適度な熱時流動性と耐熱性を付与するためであり、常温で液状となるエポキシ樹脂を用いるのは、特に樹脂付き銅箔の樹脂に対して可撓性を持たせるためである。多官能エポキシ樹脂を用いるのもやはり接着層、そして層間絶縁層への高耐熱性、高剛性の付与のためである。
【００４０】
樹脂付き銅箔の樹脂（接着層）の厚みは２０〜５０μｍの範囲が好ましい。２０μより薄いと銅箔に均一に樹脂を形成することが困難となり、また樹脂付き銅箔とした際に扱いにくくなる。５０μｍより厚いと、素子内蔵基板全体の厚みが大きくなってしまうので好ましくない。最も扱いやすいのは３０μｍ前後であり、最終的な層間絶縁層（２３）の厚みとしては１５０μｍ程度に抑えることができるように形成するとよい。
【００４１】
本発明にて用いられる硬化剤は、特に限定されるものではないが、熱硬化性樹脂の選択によってそれに対応する硬化剤を選ぶことができる。例えば熱硬化性樹脂としてエポキシ樹脂を用いる場合には、公知のエポキシ樹脂硬化剤を用いることができる。このようなエポキシ樹脂硬化剤として、例えばフェノールノボラック等の多価フェノール類、ジシアンジアミド、ジアミノジフェニルメタン、ジアミノジフェニルスルホン等のアミン系硬化剤、無水ピロメリット酸、無水トリメリット酸、ベンゾフェノンテトラカルボン酸等の酸無水物硬化剤またはこれらの混合物等が挙げられる。中でも、低吸水性の点からフェノールノボラック等の多価フェノール類の使用が特に好ましい。
【００４２】
エポキシ樹脂硬化剤の配合割合は、エポキシ樹脂との組み合わせで任意の割合で使用することができるが、通常はＴｇが高くなるようにその配合比が決定される。例えば、エポキシ樹脂硬化剤としてフェノールノボラックを用いる場合は、エポキシ当量と水酸基当量が１：１になるように配合するのが好ましい。
【００４３】
本発明で用いる液状絶縁性樹脂及び樹脂付き銅箔の樹脂（２１）には機械的、熱的、または電気的性質の改質を目的として公知の無機または有機フィラーを加えることができる。ファインパターンを形成するためにはこれらのフィラーの平均粒径が小さいもの程好ましく、平均粒径３μｍ以下のものが使用される。また、その配合比は熱硬化性樹脂の選択によって異なり、樹脂全体に対して５〜４０ｗｔ％の範囲内であることが好ましい。有機フィラーとしては、エポキシ樹脂粉末、メラミン樹脂粉末、尿素樹脂粉末、グアナミン樹脂粉末、ポリエステル樹脂粉末等を、無機フィラーとしては、シリカ、アルミナ、酸化チタン等を挙げることができる。なかでも、シリカフィラーは誘電率が低いこと、線膨張率が低いこと、表面粗化処理により絶縁性樹脂中から脱離してアンカーを形成しやすいことなどからより好ましく用いられている。
【００４４】
本発明にて用いられる熱可塑性樹脂の添加の目的は、絶縁層（１９）にねばり強さを持たせることで強い素子内蔵基板（２６）を提供するためである。通常絶縁性樹脂として用いられるエポキシ樹脂は導体層となる銅とのめっき密着性や耐熱性に優れるが、固くて脆い特性を有しており、冷熱衝撃試験での樹脂クラック等の不具合を生じることがある。本発明によれば液状絶縁性樹脂にポリエーテルスルホン、フェノキシ樹脂、ポリイミド等の熱可塑性樹脂を加えることにより、信頼性に優れた絶縁層を形成することができる。このような熱可塑性樹脂としては、先に述べた熱硬化性樹脂、硬化剤と同一の溶媒に溶解して混合できることが望ましい。また、熱可塑性樹脂の配合比は全樹脂固形分の１０〜４０％の範囲であることが好ましい。これは、熱可塑性樹脂の含量が全樹脂固形分の１０重量％以下では熱可塑性樹脂による靱性効果があまり得られない傾向があり、また４０重量％以上では充分なめっき密着性が得られない傾向にあるためである。
【００４５】
【実施例】
以下に実施例及び比較例を示して本発明を具体的に説明するが、本発明はこれに限定されるものではない。
【００４６】
［実施例１］
（ｉ）まず、本発明におけるプリント配線板内蔵用チップコンデンサの製造法の一例を示す。誘電体粉末としてチタン酸バリウム（富士チタン工業社製）、ポリビニルブチラール系バインダーのデンカブチラート（電気化学工業社製）、さらにエタノールを加えてボールミルにより湿式混合し、セラミックスラリーを調製した。このセラミックスラリーをドクターブレード法によりシート形成し、厚み２０μｍのグリーンシートを得た。次に前記グリーンシート上に、ＰｄペーストのＭＬ−３７１８（昭栄化学工業社製）をスクリーン印刷により塗布し、内部電極を形成した。さらに内部電極を印刷したグリーンシートを、内部電極がグリーンシートを介して重なるように積層して積層体とした後、前記積層体を直方体形状に切断してグリーンチップを作製した。
【００４７】
このグリーンチップをＮ_２雰囲気中にて３５０℃の温度で加熱し脱バインダー処理を行った後、空気下１３００℃で２時間保持して焼成させた。焼成後のセラミック積層体の対向する側面に銀ペーストを塗布し、Ｎ_２雰囲気中において６００℃の温度で焼き付け、内部電極と電気的に接続した外部接続用電極を形成した。この後、外部接続用電極上にＮｉめっき被膜をめっき第１層として形成し、さらにこの被膜の上にはんだめっき被膜をめっき第２層として形成して本発明におけるプリント配線板内蔵用チップコンデンサを作製した。上記のようにして得たプリント配線板内蔵用チップコンデンサの外形寸法は、長さＬ＝５ｍｍ，幅Ｗ＝５ｍｍ，厚みｔ＝５０μｍであり、内部電極間に介在する誘電体セラミック層の厚みは８μｍ、誘電体セラミック層の総数は５層であった。
【００４８】
（ｉｉ）次に本発明における液状絶縁性樹脂及び樹脂付き銅箔の製造例を示す。熱硬化性樹脂であるエポキシ樹脂成分としてエピコート１００１（油化シェルエポキシ社製）９０重量部、エピコート８２８ＥＬ（油化シェルエポキシ社製）１０重量部、硬化剤としてはエポキシ樹脂硬化剤であるフェノールノボラック（日本化薬社製）２４．６重量部、熱可塑性樹脂としてフェノキシ樹脂（フェノートＹＰ−５０、東都化成社製）３７．４重量部をシクロヘキサノンとメチルエチルケトン（ＭＥＫ）の混合溶媒に溶解させた。この溶液にシリカフィラーのＡＥＲＯＳＩＬ　ＲＹ２００（日本アエロジル社製）４０．５重量部、硬化触媒の２−エチル−４−メチルイミダゾール（東京化成工業社製）０．３２重量部を加え、練り込みロールで分散させた後に攪拌及び脱泡し、液状絶縁性樹脂を調製した。このようにして得られた液状絶縁性樹脂を厚み１２μｍの片面処理電解銅箔のマット面に塗布・半硬化させ、厚み３０μｍの接着剤層を形成し、樹脂付き銅箔を作製した。
【００４９】
（ｉｉｉ）さらに素子内蔵基板の製造例を示す。導体回路パターンが形成された内層回路基板（コア基材厚０．８ｍｍ）のコンデンサ実装位置にエポキシ樹脂を主成分とする熱硬化型接着剤を塗布し、上述（ｉ）のようにして作製されたプリント配線板内蔵用チップコンデンサを固定した。さらにコンデンサの外部接続用電極と内層回路基板上の配線パッドを導電性銀ペーストＳＡ−２０２４（藤倉化成社製）にて電気的に接続した。このようにしてコンデンサを実装した基板上に前述の液状絶縁性樹脂を、硬化後の液状絶縁性樹脂（絶縁層）の厚みが７０μｍとなるようにスロットコーターで塗布し、加熱硬化させた。
【００５０】
次に硬化した液状絶縁性樹脂（絶縁層）上に前述の樹脂付き銅箔を樹脂（接着剤層）を絶縁層側にして真空プレスにて圧力４０ｋｇ／ｃｍ^２、温度１７０℃で２時間加熱・加圧することで積層した。続いてＵＶ−ＹＡＧレーザーにより所定のビアホールを形成した後、アルカリ性過マンガン酸塩によるデスミア処理を行った。この後、無電解めっき・電気めっきを行いビアを電気的に接続すると共に導体層厚を２５μｍ前後の厚さにし、エッチングによりビルドアップ層の導体回路パターンを形成した。以上の工程を２回繰り返すことによりビルドアップ２層素子内蔵基板を製造した。
【００５１】
［実施例２］
（ｉ）実施例１の（ｉ）と同様にしてプリント配線板内蔵用チップコンデンサを作製した。
【００５２】
（ｉｉ）熱硬化性樹脂であるエポキシ樹脂成分としてＥＰＰＮ−５０２Ｈ（日本化薬社製）９０重量部、エピコート８２８ＥＬ（油化シェルエポキシ社製）１０重量部、硬化剤としてはエポキシ樹脂硬化剤であるカヤハードＮＨＮ（日本化薬社製）９９．４重量部、熱可塑性樹脂としてポリエーテルスルホン（スミカエクセル５００３Ｐ、住友化学工業社製）５９．８重量部を４−ブチロラクトンとＮ−メチル−２−ピロリドンの混合溶媒に溶解させた。この溶液にシリカフィラーのアドマファインＳＯ−Ｃ１（アドマテックス社製）７７．８重量部、硬化触媒の２−エチル−４−メチルイミダゾール（東京化成工業社製）０．７８重量部を加え、練り込みロールで分散させた後に攪拌及び脱泡し、液状絶縁性樹脂を調製した。このようにして得られた液状絶縁性樹脂を厚み１２μｍの片面処理電解銅箔のマット面に塗布・半硬化させ、厚み３０μｍの接着剤層を形成し、樹脂付き銅箔を得た。
【００５３】
（ｉｉｉ）実施例１の（ｉｉｉ）と同様にしてビルドアップ２層素子内蔵基板を製造した。
【００５４】
［実施例３］
（ｉ）厚み３０μｍのセラミックグリーンシートであるソルフィル（帝人ソルフィル社製）上に、ＰｄペーストのＭＬ−３７１８（昭栄化学工業社製）をスクリーン印刷により塗布し、内部電極を形成した。さらに内部電極を印刷したグリーンシートを、内部電極がグリーンシートを介して重なるように積層して積層体とした後、前記積層体を八角柱形状に切断してグリーンチップを作製した。
【００５５】
このグリーンチップをＮ_２雰囲気中にて６００℃の温度で加熱し脱バインダー処理を行った後、空気下１１４０℃で２時間保持して焼成させた。焼成後のチップ両端面に銀ペーストを塗布し、Ｎ_２雰囲気中において６００℃の温度で焼き付け、内部電極と電気的に接続した外部接続用電極を形成した。この後、外部接続用電極上にＮｉめっき被膜をめっき第１層として形成し、さらにこの被膜の上にはんだめっき被膜をめっき第２層として形成して本発明におけるプリント配線板内蔵用チップコンデンサを作製した。上記のようにして得たプリント配線板内蔵用チップコンデンサの外形寸法は、長さＬ＝１０ｍｍ，幅Ｗ＝１０ｍｍ（但し、長さ及び幅は対向する辺間の距離），厚みｔ＝３５μｍであり、内部電極間に介在する誘電体セラミック層の厚みは１０μｍ、誘電体セラミック層の総数は３層であった。
【００５６】
（ｉｉ）実施例１の（ｉｉ）と同様にして液状絶縁性樹脂及び樹脂付き銅箔を作製した。
【００５７】
（ｉｉｉ）実施例１の（ｉｉｉ）と同様にして素子内蔵基板を製造した。
【００５８】
［実施例４］
（ｉ）実施例３の（ｉ）と同様にしてプリント配線板内蔵用チップコンデンサを作製した。
【００５９】
（ｉｉ）実施例２の（ｉｉ）と同様にして液状絶縁性樹脂及び樹脂付き銅箔を作製した。
【００６０】
（ｉｉｉ）導体回路パターンが形成された内層回路基板（コア基材厚０．８ｍｍ）のコンデンサ実装位置にエポキシ樹脂を主成分とする熱硬化型接着剤を塗布し、上述のようにして作製されたプリント配線板内蔵用チップコンデンサを固定する。さらにコンデンサの外部接続用電極と内層回路基板上の配線パッドを導電性銀ペーストＮ−４９０６（昭栄化学工業社製）にて電気的に接続した。このようにしてコンデンサを実装した基板上に前述の液状絶縁性樹脂を硬化後の液状絶縁性樹脂（絶縁層）の厚みが４５μｍとなるようにスロットコーターで塗布し、加熱硬化させた。
【００６１】
次に硬化した液状絶縁性樹脂（絶縁層）上に前述の樹脂付き銅箔を樹脂（接着剤層）を絶縁層側にして真空プレスにて圧力３０ｋｇ／ｃｍ^２、温度１７０℃で２時間加熱・加圧することで積層した。続いてＵＶ−ＹＡＧレーザーにより所定のビアホールを形成した後、アルカリ性過マンガン酸塩によるデスミア処理を行った。この後、無電解めっき・電気めっきを行いビアを電気的に接続すると共に導体層厚を１８μｍ前後の厚さにし、エッチングによりビルドアップ層の導体回路パターンを形成した。以上の工程を２回繰り返すことによりビルドアップ２層素子内蔵基板を製造した。
【００６２】
［比較例１］
導体回路パターンが形成された内層回路基板（コア基材厚０．８ｍｍ）のコンデンサ実装位置にエポキシ樹脂を主成分とする熱硬化型接着剤を塗布し、市販の０６０３チップコンデンサ（村田製作所製ＧＲＰ０３３Ｂ１０Ｊ１０３　ＫＡ０１Ｂ）を固定した。さらにコンデンサの外部接続用電極と内層回路基板上の配線パッドを導電性銀ペーストＳＡ−２０２４（藤倉化成社製）にて電気的に接続した。このようにしてコンデンサを実装した基板上に実施例１（ｉｉ）における液状絶縁性樹脂を硬化後の液状絶縁性樹脂（絶縁層）の厚みが３２０μｍとなるようにスロットコーターで塗布し、加熱硬化させた。
【００６３】
次に硬化した液状絶縁性樹脂（絶縁層）上に同じく実施例１（ｉｉ）の樹脂付き銅箔を樹脂（接着剤層）を絶縁層側にして真空プレスにて圧力４０ｋｇ／ｃｍ^２、温度１７０℃で２時間加熱・加圧することで積層した。続いてＵＶ−ＹＡＧレーザーにより所定のビアホールを形成した後、アルカリ性過マンガン酸塩によるデスミア処理を行った。この後、無電解めっき・電気めっきを行いビアを電気的に接続すると共に導体層厚を２５μｍ前後の厚さにし、エッチングによりビルドアップ層の導体回路パターンを形成した。以上の工程を２回繰り返すことによりビルドアップ２層素子内蔵基板を製造した。
【００６４】
［比較例２］
実施例３（ｉ）と同様にしてプリント配線板内蔵用チップコンデンサを作製した。次に導体回路パターンが形成された内層回路基板（コア基材厚０．８ｍｍ）のコンデンサ実装位置にエポキシ樹脂を主成分とする熱硬化型接着剤を塗布し、上述のようにして作製されたプリント配線板内蔵用チップコンデンサを固定する。さらにコンデンサの外部接続用電極と内層回路基板上の配線パッドを導電性銀ペーストＳＡ−２０２４（藤倉化成社製）にて電気的に接続した。
【００６５】
このようにしてコンデンサを実装した基板に銅厚１２μｍ，接着剤（樹脂）厚が５０μｍである市販の樹脂付き銅箔（三菱金属社製ＭＲ６００）を真空プレスにて圧力４０ｋｇ／ｃｍ^２、温度１７０℃で２時間加熱・加圧することで積層した。続いてＵＶ−ＹＡＧレーザーにより所定のビアホールを形成した後、アルカリ性過マンガン酸塩によるデスミア処理を行った。この後、無電解めっき・電気めっきを行いビアを電気的に接続すると共に導体層厚を２５μｍ前後の厚さにし、エッチングによりビルドアップ層の導体回路パターンを形成した。以上の工程を２回繰り返すことによりビルドアップ２層素子内蔵基板を製造した。
【００６６】
［比較例３］
あらかじめドリル加工によりコンデンサを作り込むための貫通孔（φ１．０ｍｍ）を設けた両面銅貼り積層板（コア基材厚０．８ｍｍ）を用意し、この貫通孔にチタン酸バリウム粉末をフィラーとして添加したペースト状エポキシ樹脂からなる高誘電率材料をスクリーン印刷により埋め込んだ。この後、１７０℃で１時間加熱をし、高誘電材料を硬化させた後、不織布バフ研磨を行い貫通孔よりはみ出た高誘電率材料を除去した。次にめっきレジストを用いた無電解銅めっきにより、高誘電率材料の上下に外部接続用電極を形成した後、エッチングにより導体回路パターンを形成した。
【００６７】
このようにして形成した内層コアの両面に比較例２で用いた市販の樹脂付き銅箔を、真空プレスにより圧力４０ｋｇ／ｃｍ^２、温度１７０℃で２時間加熱・加圧することで積層した。続いてＵＶ−ＹＡＧレーザーにより所定のビアホールを形成した後、アルカリ性過マンガン酸塩によるデスミア処理を行った。この後、無電解めっき・電気めっきを行いビアを電気的に接続すると共に導体層厚を２５μｍ前後の厚さにし、エッチングによりビルドアップ層の導体回路パターンを形成した。以上の工程を２回繰り返すことによりコア層にコンデンサが内蔵されたビルドアップ２層素子内蔵基板を製造した。
【００６８】
上記実施例及び比較例で得られたプリント配線板内蔵用チップコンデンサ及び素子内蔵基板の評価を以下の（１）〜（５）に示す方法により行った。その結果を表１に示す。
【００６９】
（１）静電容量
各実施例及び比較例で作製あるいは使用したコンデンサの静電容量はピコアンメータを用いて測定した。
【００７０】
（２）基板厚み
各実施例及び比較例で製造した素子内蔵基板の基板厚をマイクロメーターで測定した。
【００７１】
（３）平滑性
各実施例及び比較例で製造した素子内蔵基板表面の銅をエッチングにより除去し、絶縁層表面の平滑性を顕微鏡レーザ変位計で評価した。評価方法はＪＩＳ−Ｂ０６０１に基づき絶縁層表面の段差Ｒｚを測定した。
【００７２】
（４）布線検査（サーマルサイクル前）
各実施例及び比較例で製造した素子内蔵基板１２枚に対してフライングプローブによる布線検査を行い、短絡あるいは断線による接続不良数を調べた。
【００７３】
（５）布線検査（サーマルサイクル後）
項目４で布線検査を行った素子内蔵基板１２枚に対して、１２５℃の雰囲気下と−６５℃の雰囲気下に繰り返しさらされるサーマルサイクル試験を１０００サイクル行い、試験終了後に再度フライングプローブによる布線検査を行い短絡あるいは断線による接続不良を調べた。
【００７４】
【表１】

【００７５】
【発明の効果】
本発明のプリント配線板内蔵用チップコンデンサは、薄型ながら既存のチップコンデンサと同程度の静電容量を確保することができる。また、このチップコンデンサは２つの外部接続用電極が側面にあるために、絶縁層への埋め込み後、研磨やコンデンサ直上へのビアホール形成を必要とせずに導通をとることができ、チップコンデンサへの不要なダメージを抑えることができる。
本発明の素子内蔵基板とその製造方法によれば、層間絶縁層中にチップコンデンサを内蔵したことによる基板厚みの増加や表面平滑性の悪化を軽微なものとすることができ、板厚精度に優れた高信頼性の素子内蔵基板を提供することが可能となる。特に絶縁層形成樹脂として液状絶縁性樹脂を用いた場合、チップコンデンサへのダメージがなく、層間絶縁層表面の平滑性が優れた素子内蔵基板を提供することができる。
【００７６】
【図面の簡単な説明】
【図１】本発明におけるプリント配線板内蔵用チップコンデンサの一例を示す断面図である。
【図２】本発明におけるプリント配線板内蔵用チップコンデンサの実装の一例を示す断面図である。
【図３】本発明における素子内蔵基板の製作工程の一例を示す断面図である。
【図４】本発明における素子内蔵基板の製作工程の一例を示す断面図である。
【符号の説明】
１　…セラミック誘電体層
２　…内部電極
３　…セラミック積層体
４ａ…外部接続用電極
４ｂ…めっき第１層
４ｃ…めっき第２層
５　…配線パッド
６　…配線
７　…絶縁樹脂
１０…チップコンデンサ
１１…コア基材
１２…銅箔
１３…スルーホール
１４…両面銅貼積層板
１５…導体回路パターン
１６…内層回路基板
１７…導電性ペースト
１８…液状絶縁性樹脂硬化物
１９…絶縁層
２０…樹脂付き銅箔の銅箔
２１…樹脂付き銅箔の樹脂
２２…樹脂付き銅箔
２３…層間絶縁層
２４…ビアホール
２５…導体層
２６…素子内蔵基板[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a chip capacitor that can be built in a multilayer printed wiring board, an element-containing substrate having the chip capacitor built therein, and a method of manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art In recent years, with the demand for higher performance and smaller size of electronic devices, higher density and higher functionality of circuit components have been intensified. Therefore, when electronic components are mounted on a printed wiring board, a printed wiring board having a structure in which passive components such as a capacitor (C), a resistor (R), and an inductor (L) are incorporated in a substrate in order to increase the mounting efficiency. Is attracting attention.
[0003]
For example, Japanese Unexamined Patent Publication No. Sho 54-38561 in which leadless circuit components are embedded in through holes provided in a printed circuit board, and Japanese Patent Publication No. 60-1985, in which passive components such as ceramic capacitors are embedded in through holes provided in an insulating substrate. Japanese Patent Application Laid-Open No. 41480/1992 and Japanese Patent Application Laid-Open Nos. 5-218615 and 4-218615 in which a bypass capacitor of a semiconductor element is embedded in a hole of a printed circuit board are disclosed.
[0004]
Japanese Patent Application Laid-Open No. Hei 8-222656, in which a conductive material and a dielectric material are filled in via holes provided in a ceramic wiring substrate and fired simultaneously, an electronic component forming material is embedded in a through hole provided in an organic insulating substrate. Japanese Patent Application Laid-Open No. H10-56251 discloses a method in which a capacitor and a resistor are formed by solidification.
[0005]
Each of the above-mentioned conventional techniques can be roughly classified into two types. That is, one of them is to embed already completed leadless components such as chip resistors or chip capacitors in through holes provided in the wiring board, and then to connect the external connection electrodes of the leadless components and the conductor circuit on the wiring board. The pattern is connected by conductive paste or soldering. On the other hand, in the case of an organic wiring board, an electronic component forming material such as a capacitor is embedded in a through-hole provided in the wiring board, and solidified to obtain a desired capacitor. To form an electrode to form a wiring board with a built-in electronic component. In the case of an inorganic wiring board, a dielectric board or conductive paste is filled in the via holes provided in the ceramic green sheet, and then fired at a high temperature to form a wiring board having a desired capacitor. That is.
[0006]
However, since the capacitor fired or solidified using these through holes is a single layer, it is difficult to obtain a large capacity. On the other hand, when burying and mounting a chip capacitor or the like in which a large capacity is secured in advance in the through hole, a layer thickness of 0.3 mm or 0.6 mm accompanies the use of the currently smallest size 0603 chip. It has been difficult to realize a thin multilayer printed wiring board.
[0007]
Also, when viewed as a single chip component, a chip capacitor having electrodes on the side surface represented by 1005 and 0603 is typical in the market, and an example in which these are built into a substrate is disclosed in Japanese Patent Application Laid-Open No. H11-220262. Although it has already been proposed, almost no reports have been made on chip capacitors in consideration of characteristics and shapes for embedding, and examples of embedding them in a substrate. As a few examples, Patent Document 1 discloses that a thickness t is made smaller than a length L and a width W in a sheet-like base material (B stage) made of a composite material containing alumina and an epoxy resin as a main component by using a transfer method. A method of embedding a passive component having a shape suitable for embedding in an insulating layer of a multilayer printed wiring board is disclosed.
[0008]
In the method using a sheet-shaped base material disclosed in Patent Document 1, it is difficult to embed a multilayer chip capacitor with t ≧ 10 μm or more because the composite material in the B-stage state has poor fluidity, and particularly secures the capacitance. If the area of the dielectric material is increased for this purpose, the embedding property deteriorates. Therefore, only a capacitor having a relatively small capacitance can be embedded by this method. Further, since the bare chip is buried by a vacuum press, there is a concern that the chip body and its peripheral portion may be damaged, or the smoothness of the surface of the built-in substrate may be deteriorated due to resin seepage.
Also, if electrodes are formed on the upper and lower end surfaces of the chip capacitor, the chip capacitor is placed and mounted on the conductive paste or conductive circuit pattern on the substrate, and when the insulating layer is formed and embedded, the upper end surface In order to achieve conduction from the capacitor, a process such as forming a via on the capacitor and polishing the insulating layer must be performed. It is technically difficult to form a via hole directly above the capacitor so as not to damage the capacitor, and if the insulating layer is polished to make an end face, there is a risk of damaging elements such as an internal capacitor.
[0009]
[Patent Document 1]
JP-A-2002-76637 (page 7, paragraphs 34 and 42)
[0010]
[Problems to be solved by the invention]
An object of the present invention is to develop a chip capacitor capable of securing the same capacitance as an existing chip capacitor while being a thin multilayer ceramic capacitor suitable for being incorporated in an interlayer insulating layer of a multilayer printed wiring board. Is to do. The present inventors have conducted intensive studies and found that the thickness that can be built into the interlayer insulating layer of the printed wiring board, specifically, the thickness t is 10 μm ≦ t ≦ 100 μm, and the length L and width W are 1 mm ≦ L ≦ 10 mm, It has been found that a chip capacitor with 1 mm ≦ W ≦ 10 mm can secure the same capacitance as an existing chip capacitor and can be buried in an interlayer insulating layer of a multilayer printed wiring board. Further, the electrodes are formed on the side surfaces of the chip capacitor, and when the chip capacitor is mounted on the substrate, if the electrode is arranged at a place where the conductive circuit pattern is not provided, the electrode can be buried even with a thinner interlayer insulating layer. Furthermore, when a liquid insulating resin is used for forming the insulating layer, the chip capacitor of the present invention can be easily buried in the insulating layer, and after the liquid insulating resin is cured, polishing is not required, and the resin Since the copper foil is vacuum-pressed, there is no damage to built-in elements such as chip capacitors, and a smooth conductor layer can be easily formed.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, the present invention has been made. According to a first aspect of the present invention, a thickness t is smaller than an interlayer insulating layer of a printed wiring board containing the same, and an electrode for external connection is provided. Is provided on a side surface of the chip capacitor for incorporating a printed wiring board.
[0012]
According to a second aspect of the present invention, the thickness t is within a range of 10 μm ≦ t ≦ 100 μm, the length L is within a range of 1 mm ≦ L ≦ 10 mm, and the width W is within a range of 1 mm ≦ W ≦ 10 mm. 2. The chip capacitor according to claim 1, wherein the electrode is provided on a side surface.
[0013]
A third aspect of the present invention according to the third aspect, wherein the chip capacitor has a configuration in which a plurality of ceramic dielectric layers and internal electrodes are alternately laminated. It is a capacitor.
[0014]
According to a fourth aspect of the present invention, the ceramic dielectric layer comprises, as a main component, any one of barium titanate, strontium titanate, calcium zirconate, and barium zirconate fired at 600 ° C. or more, or a mixture thereof. The chip capacitor for incorporating a printed wiring board according to any one of claims 1 to 3, wherein the chip capacitor is formed of the dielectric ceramic composition described above.
[0015]
A fifth invention according to claim 5 is characterized in that it takes one form of a polygonal prism having five or more prisms, a cylinder, or a polygonal prism having a shape in which some or all corners are rounded. 5. The chip capacitor for incorporating a printed wiring board according to any one of 1 to 4.
[0016]
According to a sixth aspect of the present invention, in the multilayer printed wiring board in which an insulating layer is laminated on an inner layer circuit board on which a conductive circuit pattern is formed, a portion where the conductive circuit pattern is not formed on the inner layer circuit board A device-embedded substrate, wherein the chip capacitor according to any one of claims 1 to 5 is mounted.
[0017]
According to a seventh aspect of the present invention, an external connection electrode of the chip capacitor according to any one of the first to fifth aspects is electrically connected to a wiring pad formed by the conductive circuit pattern. An element-embedded substrate according to claim 6.
[0018]
According to an eighth aspect of the present invention, one or both of the wiring pads electrically connected to the external connection electrodes of the chip capacitor according to any one of the first to fifth aspects have a via hole land. The via hole is connected to a formed conductor circuit pattern, and the via hole is electrically connected to a conductor circuit pattern on a layer different from the layer on which the chip capacitor is laminated via an insulating layer. An element-embedded substrate according to 6 or 7.
[0019]
According to a ninth aspect of the present invention, the thickness t of the insulating layer containing the chip capacitor is set. _z Is t + 10 μm ≦ t with respect to the thickness t of the chip capacitor. _z The device-embedded substrate according to any one of claims 6 to 8, wherein the range is ≤ t + 50 µm.
[0020]
According to a tenth aspect of the present invention, the insulating layer according to any one of the sixth to ninth aspects is obtained by thermally curing a liquid insulating resin, and the liquid insulating resin is at least
(A) Thermosetting resin
(B) Curing agent
(C) Inorganic or organic filler
The device-embedded substrate according to any one of claims 6 to 9, further comprising:
[0021]
An eleventh invention according to claim 11 is that the (A) thermosetting resin has at least
(A ₁ ) Solid polyfunctional epoxy resin with softening point of 60 ° C or higher
(A ₂ ) Polyfunctional epoxy resin that is liquid at room temperature
The device-embedded substrate according to any one of claims 6 to 10, further comprising:
[0022]
A twelfth aspect of the present invention is the element-embedded substrate according to any one of claims 6 to 11, wherein the liquid insulating resin contains (D) a thermoplastic resin.
[0023]
A thirteenth invention according to a thirteenth aspect is the chip according to any one of the first to fourth aspects, in a manufacturing process of a multilayer printed wiring board, wherein an insulating layer is laminated on an inner circuit board on which a conductive circuit pattern is formed. 7. The method according to claim 6, further comprising the steps of: laminating a copper foil with resin on the insulating layer containing the capacitor by vacuum pressing; and integrating the resin of the copper foil with resin and the insulating layer by heating. 13. A method for manufacturing a device-embedded substrate according to any one of 12.
[0024]
According to a fourteenth aspect of the present invention, the resin of the copper foil with resin is at least
(E) Thermosetting resin
(F) Curing agent
(G) Inorganic or organic filler
A device-embedded substrate manufactured by the manufacturing method according to claim 13, wherein:
[0025]
According to a fifteenth aspect of the present invention, the thermosetting resin (E) has at least
(E ₁ ) Solid polyfunctional epoxy resin with softening point of 60 ° C or higher
(E ₂ ) Polyfunctional epoxy resin that is liquid at room temperature
15. The device-embedded substrate according to claim 14, comprising:
[0026]
A sixteenth invention according to a sixteenth aspect is the element-embedded substrate according to any one of the fourteenth and fifteenth aspects, wherein the resin of the resin-coated copper foil has a residual solvent amount of 3% or less.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
One example of an embodiment of the present invention will be briefly described with reference to the drawings. As shown in FIG. 1 (b), a chip capacitor with a built-in printed wiring board according to the present invention has a ceramic laminate (3) having a structure in which a plurality of ceramic dielectric layers (1) and internal electrodes (2) are alternately laminated. An external connection electrode (4), a plating first layer (5) of nickel, copper, etc., and a plating second layer (6) of solder, tin, etc. are formed on both end surfaces of the chip capacitor. Although the physical structure is the same, it is preferable that the lower surface of the chip capacitor is previously filled with an epoxy resin or the like and smoothed out from the necessity of being fixed on the substrate with a thermosetting adhesive.
[0028]
The existing chip capacitor usually has a sufficient capacitance even though it is small by stacking 50 or more dielectric layers and internal electrodes, depending on the desired capacitance. However, currently available chip capacitors having a minimum thickness of 0603 (manufactured by Murata Manufacturing Co., Ltd.) have a thickness of 300 μm. Therefore, when mounted on a multilayer printed wiring board, a core layer having a large interlayer thickness rather than an interlayer insulating layer is required. (Inner circuit board) There was no method than embedding. In the printed circuit board built-in chip capacitor of the present invention, the number of laminated ceramic dielectric layers and internal electrodes is set to 20 or less, and the thickness t of the chip capacitor (10) is thinner than the interlayer insulating layer, specifically, 10 μm ≦ It is set to t ≦ 100 μm so that it can be embedded in the interlayer insulating layer of the multilayer printed wiring board. When the thickness t is in the range of 10 μm ≦ t ≦ 80 μm, the thickness is more easily embedded and has an ideal size. Further, the length L of the capacitor was set to 1 mm ≦ L ≦ 10 mm, and the width W was set to 1 mm ≦ W ≦ 10 mm, and the area was larger than that of the existing chip capacitor. As a result, the capacitance per dielectric layer increases, and the decrease in capacitance due to the decrease in the number of stacked dielectric layers is offset, so that the same capacitance as existing chip capacitors can be obtained. did it.
[0029]
Next, a method of manufacturing a chip capacitor for incorporating a printed wiring board according to the present invention will be described in the order of manufacturing steps with reference to FIG. First, a ceramic laminate is formed according to the following procedure. A dielectric ceramic sheet (green sheet) is prepared by slurrying a dielectric ceramic composition, and a paste such as Pt or Pd is applied to one surface of the dielectric ceramic sheet by screen printing or the like to form an internal electrode (2). . The required number of dielectric ceramic sheets on which the internal electrodes are formed are laminated, and finally, the dielectric ceramic sheets on which the internal electrodes are not formed are laminated and pressed on the internal electrodes outside the laminate. At this time, if the shape of the laminated body composed of the internal electrodes and the dielectric ceramic sheet is an obtuse angle or a rounded shape such as a polygonal column or a cylindrical shape, a ceramic capacitor resistant to cracking and chipping after firing can be obtained. Thereafter, the laminate including the internal electrodes and the dielectric ceramic sheet is fired at a predetermined temperature to form a ceramic laminate (3).
[0030]
Next, two external connection electrodes (4a) are formed on both end surfaces of the ceramic laminate (3) so as to be connected to the internal electrodes (2). As the material of the external connection electrode (4a), the same material as that of the internal electrode can be used. Further, silver, palladium, silver-palladium alloy, copper, copper alloy and the like can be used. In addition, B is added to these metal powders. ₂ O ₃ -SiO ₂ -BaO-based glass, Li ₂ O-SiO ₂ A glass frit such as a BaO-based glass is also used. The external connection electrode (4a) is formed by applying a metal powder paste as a material to the ceramic laminate (3) obtained by firing and baking, but is applied before firing and formed simultaneously with the ceramic laminate. May be. Thereafter, plating of nickel, copper or the like is performed on the external connection electrode (4a) to form a first plating layer (4b). Finally, a second layer (4c) of plating of solder, tin or the like is formed on the first layer of plating to manufacture the chip capacitor (10) for incorporating a printed wiring board in the present invention.
[0031]
The shape of the chip capacitor (10) with a built-in printed wiring board according to the present invention may be obtuse or rounded, such as a polygonal prism having five or more prisms, a cylinder including an elliptical cylinder, or a polygonal prism having rounded corners. By adopting such a shape, a ceramic chip capacitor which is hard to be damaged despite being thin can be obtained.
[0032]
The composition of the dielectric ceramic layer used in the present invention is not particularly limited. For example, titanates such as barium titanate, strontium titanate, calcium titanate, magnesium titanate, zinc titanate, lead titanate, etc. Alternatively, various dielectric ceramic compositions containing zirconates such as calcium zirconate, barium zirconate, and lead zirconate as main components can be used.
[0033]
As the internal electrodes used in the present invention, noble metals such as Pt and Pd can be used. In the case where a laminate of dielectric ceramic sheets is fired in a reducing atmosphere, Ni, Ni alloy, Cu, Cu alloy is used. And other base metals can also be used. In addition, as a method of forming the internal electrode, for example, there are screen printing, vapor deposition, plating, and the like, but any method may be used.
[0034]
Hereinafter, an example of a method for manufacturing a device-embedded substrate according to the present invention will be described with reference to the drawings. First, as shown in FIG. 3A, a double-sided copper-clad laminate (14) in which predetermined through holes are formed in advance is prepared, and copper on the surface layer is etched to form a conductive circuit pattern (15) ( FIG. 3 (b). The chip capacitor (10) for embedding a printed wiring board according to the present invention is fixed to a predetermined position of the inner circuit board (16) thus produced with an adhesive (FIG. 3 (c)). The predetermined position here is, as shown in FIG. 3 (c), between the wiring pads for connecting the external connection electrodes (4a) of the chip capacitor on the core base material (11) or in FIG. As shown in (j), it is on the interlayer insulating layer (23) (that is, where the conductive circuit pattern (15) is not formed). If the adhesive is a thermosetting adhesive, it can be easily processed and the strength after curing is satisfactory. Further, the external connection electrodes (4a) on the side surfaces of the chip capacitor of the present invention and the wiring pads formed on the core base material (11) or on the interlayer insulating layer (23) are electrically connected with a conductive paste (17), solder or the like. (FIG. 3D).
[0035]
Next, the thickness t of the insulating layer (19) containing the chip capacitor (10) of the present invention is formed on the inner circuit board (16). _z Is t + 10 μm ≦ t with respect to the thickness t of the chip capacitor. _z An insulating layer (19) is formed so as to fall within a range of ≦ t + 50 μm, and the chip capacitor is embedded in the insulating layer (FIG. 3E). When the thickness is defined in such a range, the capacitor is exposed when the insulating layer is too thin, and the capacitor may be damaged when the resin-coated copper foil (22) is laminated. This is because the substrate becomes too thick. For the formation of the insulating layer (19), it is preferable to apply a liquid insulating resin and to heat and cure. Since the liquid insulating resin has high fluidity, a thick chip capacitor (10) and a conductive circuit pattern (15) can be embedded efficiently.
[0036]
Further, a copper foil with resin (22) is laminated by a vacuum press, and the insulating layer (19) and the resin (21) of the copper foil with resin are integrally cured by heating to form a conductor layer and an interlayer insulating layer (23). (FIG. 3 (f)). As the copper foil (20) of the copper foil with resin, it is preferable to use a thin copper foil having a thickness of about 10 μm, which is easily penetrated by laser processing. Via holes are formed at predetermined positions by a UV-YAG laser (FIG. 3 (g)), desmearing, electroless plating, and panel plating are performed to form a conductor circuit pattern (15) on an inner layer circuit board (16). The conductor layer (25) of the build-up layer provided is electrically connected, the conductor layer is made to have a predetermined thickness (FIG. 4H), and the conductor layer of the next layer is etched by etching the conductor layer (25). A circuit pattern (15) is formed (FIG. 4 (i)). By repeating the above steps a plurality of times, it is possible to manufacture a device built-in substrate (26) in which the chip capacitor (10) of the present invention is built in the interlayer insulating layer (23) of the multilayer printed wiring board (FIG. j)).
[0037]
The resin (21) (adhesion layer) of the liquid insulating resin and the resin-coated copper foil used in the present invention is mainly composed of a thermosetting resin. For example, epoxy resins, cyanate resins, addition polymerization products of bismaleimides and diamines, phenolic resins, resole resins, isocyanates, triallyl isocyanurate, triallyl cyanurate, vinyl group-containing polyolefin compounds, and the like. It is not limited to. Among these thermosetting resins, an epoxy resin, particularly a polyfunctional epoxy resin, is preferred from the viewpoint of a balance between performance such as heat resistance and insulation and cost.
[0038]
Known epoxy resins can be used for the present invention. For example, phenol novolak type epoxy resin, cresol novolak type epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, bisphenol S type epoxy resin, biphenyl type epoxy resin, biphenyl novolak type epoxy resin, trishydroxyphenylmethane type epoxy resin, Hydrogenated compounds of epoxy compounds containing aromatic rings such as tetraphenylethane type epoxy resin and dicyclopentadiene phenol type epoxy resin, alicyclic epoxy resins and various derivatives of cyclohexene oxide, and tetrabromobisphenol A type epoxy resin Halogen-containing epoxy resins and the like can be mentioned, and these can be used alone or in combination.
[0039]
When these epoxy resins are used as thermosetting resins, there are two types of epoxy resins having different physical properties, a polyfunctional epoxy resin having a softening point of 60 ° C. or higher and being solid at room temperature, and a polyfunctional epoxy resin being liquid at room temperature. It is preferable to use a mixture of resins. The reason for using an epoxy resin having a softening point of 60 ° C. or more is to provide a liquid insulating resin and a resin of a copper foil with a resin with appropriate heat fluidity and heat resistance. The reason for this is to make the resin of the copper foil with resin particularly flexible. The use of the polyfunctional epoxy resin is also for imparting high heat resistance and high rigidity to the adhesive layer and the interlayer insulating layer.
[0040]
The thickness of the resin (adhesion layer) of the copper foil with resin is preferably in the range of 20 to 50 μm. If the thickness is less than 20 μm, it becomes difficult to uniformly form a resin on the copper foil, and it becomes difficult to handle the resin-coated copper foil. If the thickness is more than 50 μm, the thickness of the entire substrate with a built-in element is undesirably increased. The most easy to handle is about 30 μm, and it is preferable that the final interlayer insulating layer (23) be formed so that the thickness can be suppressed to about 150 μm.
[0041]
The curing agent used in the present invention is not particularly limited, but a curing agent corresponding thereto can be selected by selecting a thermosetting resin. For example, when an epoxy resin is used as the thermosetting resin, a known epoxy resin curing agent can be used. Examples of such epoxy resin curing agents include polyphenols such as phenol novolak, amine curing agents such as dicyandiamide, diaminodiphenylmethane, diaminodiphenylsulfone, pyromellitic anhydride, trimellitic anhydride, and benzophenonetetracarboxylic acid. An acid anhydride curing agent or a mixture thereof is exemplified. Among them, the use of polyhydric phenols such as phenol novolak is particularly preferable from the viewpoint of low water absorption.
[0042]
The compounding ratio of the epoxy resin curing agent can be used in an arbitrary ratio in combination with the epoxy resin, but usually the compounding ratio is determined so that Tg is increased. For example, when phenol novolak is used as the epoxy resin curing agent, it is preferable to mix the epoxy equivalent and the hydroxyl equivalent at a ratio of 1: 1.
[0043]
A known inorganic or organic filler can be added to the liquid insulating resin and the resin (21) of the resin-coated copper foil used in the present invention for the purpose of improving mechanical, thermal, or electrical properties. In order to form a fine pattern, it is preferable that the average particle size of these fillers is small, and those having an average particle size of 3 μm or less are used. The compounding ratio varies depending on the selection of the thermosetting resin, and is preferably in the range of 5 to 40% by weight based on the whole resin. Examples of the organic filler include epoxy resin powder, melamine resin powder, urea resin powder, guanamine resin powder, and polyester resin powder. Examples of the inorganic filler include silica, alumina, and titanium oxide. Among them, silica fillers are more preferably used because they have a low dielectric constant, a low coefficient of linear expansion, and are easily detached from an insulating resin by surface roughening treatment to form an anchor.
[0044]
The purpose of the addition of the thermoplastic resin used in the present invention is to provide the element-containing substrate (26) which is strong by giving the insulating layer (19) tenacity. Epoxy resin, which is usually used as an insulating resin, has excellent plating adhesion to copper as the conductor layer and excellent heat resistance, but has hard and brittle properties, and may cause defects such as resin cracks in thermal shock tests. There is. According to the present invention, a highly reliable insulating layer can be formed by adding a thermoplastic resin such as polyether sulfone, phenoxy resin, or polyimide to a liquid insulating resin. As such a thermoplastic resin, it is desirable that the above-described thermosetting resin and the curing agent can be dissolved and mixed in the same solvent. The mixing ratio of the thermoplastic resin is preferably in the range of 10 to 40% of the total resin solids. This is because when the content of the thermoplastic resin is 10% by weight or less of the total resin solids, the toughness effect of the thermoplastic resin tends to be hardly obtained, and when the content is 40% by weight or more, sufficient plating adhesion tends not to be obtained. Because it is in.
[0045]
【Example】
Hereinafter, the present invention will be described specifically with reference to Examples and Comparative Examples, but the present invention is not limited thereto.
[0046]
[Example 1]
(I) First, an example of a method for manufacturing a chip capacitor for incorporating a printed wiring board in the present invention will be described. Barium titanate (manufactured by Fuji Titanium Industry Co., Ltd.), polyvinyl butyral-based binder denkabutyrate (manufactured by Denki Kagaku Kogyo Co., Ltd.) and ethanol were further added as dielectric powders, and the mixture was wet-mixed with a ball mill to prepare a ceramic slurry. This ceramic slurry was formed into a sheet by a doctor blade method to obtain a green sheet having a thickness of 20 μm. Next, Pd paste ML-3718 (manufactured by Shoei Chemical Industry Co., Ltd.) was applied on the green sheet by screen printing to form internal electrodes. Furthermore, after laminating the green sheets on which the internal electrodes were printed so that the internal electrodes overlap with the green sheets interposed therebetween, a laminate was formed, and the laminate was cut into a rectangular parallelepiped to produce a green chip.
[0047]
This green chip is N ₂ After performing debinding treatment by heating at a temperature of 350 ° C. in an atmosphere, firing was carried out at 1300 ° C. for 2 hours in air. A silver paste is applied to opposite sides of the fired ceramic laminate, ₂ Baking was performed at a temperature of 600 ° C. in an atmosphere to form an external connection electrode electrically connected to the internal electrode. Thereafter, a Ni plating film is formed as a first plating layer on the external connection electrodes, and a solder plating film is further formed as a second plating layer on the Ni plating film to form the chip capacitor with a built-in printed wiring board according to the present invention. Produced. The external dimensions of the printed wiring board built-in chip capacitor obtained as described above are length L = 5 mm, width W = 5 mm, thickness t = 50 μm, and the thickness of the dielectric ceramic layer interposed between the internal electrodes is 8 μm, the total number of dielectric ceramic layers was 5.
[0048]
(Ii) Next, a production example of the liquid insulating resin and the copper foil with resin in the present invention will be described. 90 parts by weight of Epicoat 1001 (manufactured by Yuka Shell Epoxy) as an epoxy resin component which is a thermosetting resin, 10 parts by weight of Epicoat 828EL (manufactured by Yuka Shell Epoxy), and phenol novolak which is an epoxy resin curing agent as a curing agent 24.6 parts by weight (manufactured by Nippon Kayaku Co., Ltd.) and 37.4 parts by weight of a phenoxy resin as a thermoplastic resin (Fenault YP-50, manufactured by Toto Kasei Co., Ltd.) were dissolved in a mixed solvent of cyclohexanone and methyl ethyl ketone (MEK). To this solution, 40.5 parts by weight of AEROSIL RY200 (manufactured by Nippon Aerosil Co., Ltd.) as a silica filler and 0.32 parts by weight of 2-ethyl-4-methylimidazole (manufactured by Tokyo Chemical Industry Co., Ltd.) as a curing catalyst are added, and the mixture is kneaded with a kneading roll. After the dispersion, the mixture was stirred and defoamed to prepare a liquid insulating resin. The liquid insulating resin thus obtained was applied and semi-cured on a matte surface of a 12 μm-thick single-sided treated electrolytic copper foil to form an adhesive layer having a thickness of 30 μm, thereby producing a resin-coated copper foil.
[0049]
(Iii) Further, an example of manufacturing an element-embedded substrate will be described. A thermosetting adhesive mainly composed of epoxy resin is applied to the capacitor mounting position of the inner layer circuit board (core base material thickness 0.8 mm) on which the conductive circuit pattern is formed, and is manufactured as described in (i) above. The chip capacitor for mounting a printed wiring board was fixed. Further, the external connection electrode of the capacitor and the wiring pad on the inner layer circuit board were electrically connected with conductive silver paste SA-2024 (manufactured by Fujikura Kasei Co., Ltd.). The liquid insulating resin described above was applied on the substrate on which the capacitor was mounted by a slot coater so that the cured liquid insulating resin (insulating layer) had a thickness of 70 μm, and was cured by heating.
[0050]
Next, on the cured liquid insulating resin (insulating layer), the above-mentioned resin-coated copper foil is applied with the resin (adhesive layer) on the insulating layer side by a vacuum press at a pressure of 40 kg / cm. ² The layers were laminated by heating and pressing at a temperature of 170 ° C. for 2 hours. Subsequently, after a predetermined via hole was formed by a UV-YAG laser, a desmear treatment with an alkaline permanganate was performed. Thereafter, electroless plating and electroplating were performed to electrically connect the vias, the thickness of the conductor layer was set to about 25 μm, and a conductor circuit pattern of the build-up layer was formed by etching. By repeating the above steps twice, a build-up two-layer element built-in substrate was manufactured.
[0051]
[Example 2]
(I) A chip capacitor with a built-in printed wiring board was produced in the same manner as (i) of Example 1.
[0052]
(Ii) 90 parts by weight of EPPN-502H (manufactured by Nippon Kayaku), 10 parts by weight of Epicoat 828EL (manufactured by Yuka Shell Epoxy) as an epoxy resin component which is a thermosetting resin, and an epoxy resin curing agent as a curing agent. 99.4 parts by weight of a certain Kayahard NHN (manufactured by Nippon Kayaku Co., Ltd.) and 59.8 parts by weight of a polyether sulfone (Sumika Excel 5003P, manufactured by Sumitomo Chemical Co., Ltd.) as a thermoplastic resin are 4-butyrolactone and N-methyl-2-. It was dissolved in a mixed solvent of pyrrolidone. To this solution were added 77.8 parts by weight of silica filler Admafine SO-C1 (manufactured by Admatechs) and 0.78 parts by weight of 2-ethyl-4-methylimidazole (manufactured by Tokyo Chemical Industry Co., Ltd.) as a curing catalyst. After dispersing with a roll, the mixture was stirred and defoamed to prepare a liquid insulating resin. The liquid insulating resin thus obtained was applied and semi-cured on the matte surface of a 12 μm-thick one-side treated electrolytic copper foil to form an adhesive layer having a thickness of 30 μm, thereby obtaining a resin-coated copper foil.
[0053]
(Iii) A build-up two-layer element-embedded substrate was manufactured in the same manner as (iii) of Example 1.
[0054]
[Example 3]
(I) Pd paste ML-3718 (manufactured by Shoei Chemical Industry Co., Ltd.) was applied by screen printing onto Solfill (manufactured by Teijin Solfill), which is a ceramic green sheet having a thickness of 30 μm, to form internal electrodes. Furthermore, after laminating green sheets on which the internal electrodes were printed so that the internal electrodes overlap each other with the green sheets interposed therebetween, a laminate was cut, and the laminate was cut into an octagonal column to produce a green chip.
[0055]
This green chip is N ₂ After performing debinding treatment by heating at a temperature of 600 ° C. in an atmosphere, the resultant was held at 1140 ° C. for 2 hours in air to be fired. A silver paste is applied to both ends of the fired chip, and N ₂ Baking was performed at a temperature of 600 ° C. in an atmosphere to form an external connection electrode electrically connected to the internal electrode. Thereafter, a Ni plating film is formed as a first plating layer on the external connection electrodes, and a solder plating film is further formed as a second plating layer on the Ni plating film to form the chip capacitor with a built-in printed wiring board according to the present invention. Produced. The external dimensions of the printed wiring board built-in chip capacitor obtained as described above are as follows: length L = 10 mm, width W = 10 mm (the length and width are the distance between opposing sides), and the thickness t = 35 μm. The thickness of the dielectric ceramic layer interposed between the internal electrodes was 10 μm, and the total number of the dielectric ceramic layers was three.
[0056]
(Ii) A liquid insulating resin and a copper foil with resin were produced in the same manner as in (ii) of Example 1.
[0057]
(Iii) A device-embedded substrate was manufactured in the same manner as in (iii) of Example 1.
[0058]
[Example 4]
(I) A chip capacitor with a built-in printed wiring board was manufactured in the same manner as (i) of Example 3.
[0059]
(Ii) A liquid insulating resin and a resin-coated copper foil were produced in the same manner as in (ii) of Example 2.
[0060]
(Iii) A thermosetting adhesive mainly composed of an epoxy resin is applied to the capacitor mounting position of the inner layer circuit board (core substrate thickness: 0.8 mm) on which the conductor circuit pattern is formed, and is manufactured as described above. Fix the chip capacitor for built-in printed wiring board. Further, the external connection electrode of the capacitor and the wiring pad on the inner layer circuit board were electrically connected with conductive silver paste N-4906 (manufactured by Shoei Chemical Industry Co., Ltd.). The liquid insulating resin described above was applied on the substrate on which the capacitor was mounted in such a manner as to have a cured liquid insulating resin (insulating layer) having a thickness of 45 μm by a slot coater, and was cured by heating.
[0061]
Next, on the cured liquid insulating resin (insulating layer), the above-mentioned copper foil with resin is pressed with a resin (adhesive layer) on the insulating layer side by a vacuum press at a pressure of 30 kg / cm. ² The layers were laminated by heating and pressing at a temperature of 170 ° C. for 2 hours. Subsequently, after a predetermined via hole was formed by a UV-YAG laser, a desmear treatment with an alkaline permanganate was performed. Thereafter, electroless plating and electroplating were performed to electrically connect the vias, the thickness of the conductor layer was adjusted to about 18 μm, and a conductor circuit pattern of the build-up layer was formed by etching. By repeating the above steps twice, a build-up two-layer element built-in substrate was manufactured.
[0062]
[Comparative Example 1]
A thermosetting adhesive mainly composed of epoxy resin is applied to the capacitor mounting position of the inner layer circuit board (core base material thickness 0.8 mm) on which the conductive circuit pattern is formed, and a commercially available 0603 chip capacitor (GRP033B10J103 manufactured by Murata Manufacturing Co., Ltd.) KA01B) was fixed. Further, the external connection electrode of the capacitor and the wiring pad on the inner layer circuit board were electrically connected with conductive silver paste SA-2024 (manufactured by Fujikura Kasei Co., Ltd.). The liquid insulating resin in Example 1 (ii) was applied on the substrate on which the capacitor was mounted in this manner with a slot coater so that the thickness of the liquid insulating resin (insulating layer) after curing became 320 μm, and was cured by heating. I let it.
[0063]
Next, the resin-coated copper foil of Example 1 (ii) was pressed on the cured liquid insulating resin (insulating layer) by a vacuum press at a pressure of 40 kg / cm with the resin (adhesive layer) on the insulating layer side. ² The layers were laminated by heating and pressing at a temperature of 170 ° C. for 2 hours. Subsequently, after a predetermined via hole was formed by a UV-YAG laser, a desmear treatment with an alkaline permanganate was performed. Thereafter, electroless plating and electroplating were performed to electrically connect the vias, the thickness of the conductor layer was set to about 25 μm, and a conductor circuit pattern of the build-up layer was formed by etching. By repeating the above steps twice, a build-up two-layer element built-in substrate was manufactured.
[0064]
[Comparative Example 2]
A chip capacitor with a built-in printed wiring board was manufactured in the same manner as in Example 3 (i). Next, a thermosetting adhesive mainly composed of epoxy resin was applied to the mounting position of the capacitor on the inner layer circuit board (core base material thickness: 0.8 mm) on which the conductor circuit pattern was formed, and fabricated as described above. Fix the chip capacitor for built-in printed wiring board. Further, the external connection electrode of the capacitor and the wiring pad on the inner layer circuit board were electrically connected with conductive silver paste SA-2024 (manufactured by Fujikura Kasei Co., Ltd.).
[0065]
A commercially available copper foil with resin (MR600 manufactured by Mitsubishi Metals Co., Ltd.) having a copper thickness of 12 μm and an adhesive (resin) thickness of 50 μm was applied to the substrate on which the capacitor was mounted in this manner by a vacuum press at a pressure of 40 kg / cm. ² The layers were laminated by heating and pressing at a temperature of 170 ° C. for 2 hours. Subsequently, after a predetermined via hole was formed by a UV-YAG laser, a desmear treatment with an alkaline permanganate was performed. Thereafter, electroless plating and electroplating were performed to electrically connect the vias, the thickness of the conductor layer was set to about 25 μm, and a conductor circuit pattern of the build-up layer was formed by etching. By repeating the above steps twice, a build-up two-layer element built-in substrate was manufactured.
[0066]
[Comparative Example 3]
Prepare a double-sided copper-clad laminate (core substrate thickness: 0.8 mm) with through holes (φ1.0 mm) for making capacitors by drilling in advance, and add barium titanate powder as a filler to these through holes The high-permittivity material made of the pasted epoxy resin was embedded by screen printing. Thereafter, the material was heated at 170 ° C. for 1 hour to cure the high dielectric material, and then buffed with a nonwoven fabric to remove the high dielectric material protruding from the through hole. Next, external connection electrodes were formed above and below the high dielectric constant material by electroless copper plating using a plating resist, and then a conductive circuit pattern was formed by etching.
[0067]
The commercially available resin-coated copper foil used in Comparative Example 2 was applied to both sides of the inner core formed in this manner by a vacuum press at a pressure of 40 kg / cm. ² The layers were laminated by heating and pressing at a temperature of 170 ° C. for 2 hours. Subsequently, after a predetermined via hole was formed by a UV-YAG laser, a desmear treatment with an alkaline permanganate was performed. Thereafter, electroless plating and electroplating were performed to electrically connect the vias, the thickness of the conductor layer was set to about 25 μm, and a conductor circuit pattern of the build-up layer was formed by etching. By repeating the above steps twice, a build-up two-layer device built-in substrate having a capacitor built in the core layer was manufactured.
[0068]
The chip capacitors with a built-in printed wiring board and the device-embedded substrates obtained in the above Examples and Comparative Examples were evaluated by the following methods (1) to (5). Table 1 shows the results.
[0069]
(1) Capacitance
The capacitance of the capacitors manufactured or used in each of Examples and Comparative Examples was measured using a picoammeter.
[0070]
(2) Substrate thickness
The substrate thickness of the device-embedded substrate manufactured in each of Examples and Comparative Examples was measured with a micrometer.
[0071]
(3) Smoothness
The copper on the surface of the substrate with a built-in element manufactured in each of the examples and the comparative examples was removed by etching, and the smoothness of the surface of the insulating layer was evaluated with a microscope laser displacement meter. As an evaluation method, a step Rz on the surface of the insulating layer was measured based on JIS-B0601.
[0072]
(4) Wiring inspection (before thermal cycle)
A wiring test was performed with a flying probe on the 12 element-embedded substrates manufactured in each of the examples and the comparative examples, and the number of connection failures due to a short circuit or disconnection was examined.
[0073]
(5) Wiring inspection (after thermal cycle)
A thermal cycle test was repeated 1000 times under the atmosphere of 125 ° C. and the atmosphere of −65 ° C. on the 12 element-embedded substrates on which the wiring test was performed in item 4, and after the test was completed, the fabric was again tested with the flying probe. A wire inspection was performed to check for a connection failure due to a short circuit or disconnection.
[0074]
[Table 1]

[0075]
【The invention's effect】
ADVANTAGE OF THE INVENTION The chip capacitor for printed wiring board built-in of this invention can ensure the same electrostatic capacitance as an existing chip capacitor although being thin. In addition, since this chip capacitor has two external connection electrodes on the side, it can be electrically connected after embedding in the insulating layer without the need for polishing or forming a via hole directly above the capacitor. Unnecessary damage can be suppressed.
According to the device-embedded substrate and the method of manufacturing the same of the present invention, increase in substrate thickness and deterioration in surface smoothness due to the incorporation of a chip capacitor in the interlayer insulating layer can be reduced, and plate thickness accuracy can be reduced. It is possible to provide an element-embedded substrate having excellent high reliability. In particular, when a liquid insulating resin is used as the resin for forming the insulating layer, it is possible to provide a device-embedded substrate having no damage to the chip capacitor and having excellent smoothness of the surface of the interlayer insulating layer.
[0076]
[Brief description of the drawings]
FIG. 1 is a sectional view showing an example of a chip capacitor for incorporating a printed wiring board in the present invention.
FIG. 2 is a cross-sectional view showing an example of mounting a chip capacitor for incorporating a printed wiring board in the present invention.
FIG. 3 is a cross-sectional view illustrating an example of a manufacturing process of the device-embedded substrate according to the present invention.
FIG. 4 is a cross-sectional view illustrating an example of a manufacturing process of the device-embedded substrate according to the present invention.
[Explanation of symbols]
1 ... ceramic dielectric layer
2 Internal electrode
3. Ceramic laminate
4a: External connection electrode
4b: First plating layer
4c ... Plating second layer
5 ... wiring pads
6 ... wiring
7 ... insulating resin
10 ... Chip capacitors
11 ... Core substrate
12 ... Copper foil
13 ... Through hole
14 Double-sided copper-clad laminate
15 Conductor circuit pattern
16 ... Inner circuit board
17 Conductive paste
18: Liquid insulating resin cured product
19 ... insulating layer
20: Copper foil of resin-coated copper foil
21: Resin of copper foil with resin
22 ... Copper foil with resin
23 ... interlayer insulating layer
24 ... Beer hole
25 ... conductor layer
26… Element built-in substrate

Claims

A chip capacitor with a built-in printed wiring board, wherein a thickness t is smaller than an interlayer insulating layer of a printed wiring board containing the same, and external connection electrodes are provided on side surfaces.

2. The chip capacitor according to claim 1, wherein the thickness t is within a range of 10 μm ≦ t ≦ 100 μm, the length L is within a range of 1 mm ≦ L ≦ 10 mm, and the width W is within a range of 1 mm ≦ W ≦ 10 mm. .

3. The chip capacitor according to claim 1, wherein the chip capacitor has a structure in which a plurality of ceramic dielectric layers and internal electrodes are alternately laminated.

The ceramic dielectric layer is formed of a dielectric ceramic composition containing barium titanate, strontium titanate, calcium zirconate, barium zirconate, or a mixture thereof as a main component, which is fired at 600 ° C. or higher. The chip capacitor for incorporating a printed wiring board according to any one of claims 1 to 3, characterized in that:

The printed wiring according to any one of claims 1 to 4, wherein the printed wiring has a shape of any one of a polygonal prism having five or more prisms, a cylinder, and a polygonal prism having a shape in which some or all corners are rounded. Chip capacitor for internal board.

6. A multilayer printed wiring board comprising an insulating layer laminated on an inner circuit board on which a conductor circuit pattern is formed, wherein a portion of the inner circuit board on which the conductor circuit pattern is not formed is provided. A substrate with a built-in element, wherein the chip capacitor according to claim 1 is loaded.

7. The device-embedded substrate according to claim 6, wherein the external connection electrode of the chip capacitor according to claim 1 and a wiring pad formed by the conductive circuit pattern are electrically connected.

6. One or both of the wiring pads electrically connected to the external connection electrode of the chip capacitor according to claim 1 are connected to the conductor circuit pattern in which the via hole land is formed. 8. The device-embedded substrate according to claim 6, wherein the via hole is electrically connected to a conductor circuit pattern on a layer different from a layer on which the chip capacitor is laminated via an insulating layer.

Element-embedded board according to any one of claims 6 8, characterized in that the thickness t _z of the insulation layer which incorporates the chip capacitor is in a range of _{t + 10μm ≦ t z ≦ t} + 50μm with respect to the thickness t of the chip capacitor .

The insulating layer according to any one of claims 6 to 9, wherein a liquid insulating resin is thermoset, and the liquid insulating resin is at least (A) a thermosetting resin (B) a curing agent (C) an inorganic material. The device-embedded substrate according to any one of claims 6 to 9, further comprising an organic filler.

7. The method according to claim 6, wherein (A) the thermosetting resin contains at least (A ₁ ) a solid polyfunctional epoxy resin having a softening point of 60 ° C. or higher (A ₂ ) and a liquid polyfunctional epoxy resin at room temperature. 11. The device-embedded substrate according to any one of items 10.

The device-embedded substrate according to any one of claims 6 to 11, wherein the liquid insulating resin contains (D) a thermoplastic resin.

6. In a manufacturing process of a multilayer printed wiring board obtained by laminating an insulating layer on an inner layer circuit board on which a conductive circuit pattern is formed, a vacuum press is performed on the insulating layer incorporating the chip capacitor according to any one of claims 1 to 5. The element-embedded substrate according to claim 6, further comprising: a step of laminating a resin-coated copper foil; and a step of integrating the resin of the resin-coated copper foil with the insulating layer by heating. Production method.

The device built-in element manufactured by the manufacturing method according to claim 13, wherein the resin of the resin-coated copper foil contains at least (E) a thermosetting resin (F) a curing agent (G) an inorganic or organic filler. substrate.

15. The method according to claim 14, wherein the (E) thermosetting resin contains at least (E ₁ ) a solid polyfunctional epoxy resin having a softening point of 60 ° C. or higher (E ₂ ) and a liquid polyfunctional epoxy resin at room temperature. An element-embedded substrate as described in the above.

16. The device-embedded substrate according to claim 14, wherein the resin of the resin-coated copper foil has a residual solvent amount of 3% or less.