JP2005094009A - 光受信機パッケージ - Google Patents
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- JP2005094009A JP2005094009A JP2004268066A JP2004268066A JP2005094009A JP 2005094009 A JP2005094009 A JP 2005094009A JP 2004268066 A JP2004268066 A JP 2004268066A JP 2004268066 A JP2004268066 A JP 2004268066A JP 2005094009 A JP2005094009 A JP 2005094009A
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
- G02B6/4204—Packages, e.g. shape, construction, internal or external details the coupling comprising intermediate optical elements, e.g. lenses, holograms
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- G—PHYSICS
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- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/4201—Packages, e.g. shape, construction, internal or external details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- Optics & Photonics (AREA)
- Light Receiving Elements (AREA)
- Optical Couplings Of Light Guides (AREA)
Abstract
【解決手段】 第1ウェハに形成される複数のサブマウント120のそれぞれにダイ110がウェハレベルで電気的に接続される。ダイ110の表の面に光電領域が形成され、裏の面に集光レンズが形成され、ダイ110の表の面がサブマウント120と隣接するように載置される。次いで、ダイ110を包囲するキャビティ140を形成するキャップ130が複数形成された第2ウェハが第1ウェハ上に載置され、シールされる。第2ウェハは、サブマウント120の表面に形成される外部端子124が露出するように切断され、キャップ130は1つひとつに分離される。その後、第1ウェハはダイシングされて個々のチップが切り出され、ダイ110に入射する光信号に対して透光性を有する位置決めポスト160が取り付けられ、光サブアセンブリパッケージ100が完成する。
【選択図】 図1
Description
なお、本発明は例として次の態様を含む。( )内の数字は添付図面の参照符号に対応する。
[1] サブマウント(120)と、
前記サブマウント(120)に電気的に接続されるセンサを備えるダイ(110)と、
前記サブマウント(120)に取り付けられ、前記ダイ(110)を包囲するキャビティ(140)を形成するキャップ(130)と、
光信号を前記センサの光電領域上に集光するレンズ(150、250)と
を備えることを特徴とするデバイス。
[2] 前記レンズ(150)が前記ダイ(110)の裏の面上に存在することを特徴とする、上記[1]に記載のデバイス。
[3] 前記ダイ(110)が前記サブマウント(120)に取り付けられ、前記ダイの表の面が前記サブマウント(120)に隣接することを特徴とする、上記[1]または[2]に記載のデバイス。
[4] 前記レンズ(250)が前記キャップ(230)内に集積されることを特徴とする、上記[1]に記載のデバイス。
[5] 前記センサまでの光学経路に沿って、前記キャップ(130)に取り付けられた位置決めポスト(160)をさらに備えることを特徴とする、上記[1]から[5]の何れかに記載のデバイス。
[6] ボアを有するスリーブ(330)であって、前記ボアが、前記ボアの第1端部に前記位置決めポスト(160)を、前記ボアの第2端部に光ファイバコネクタ(310)を収容可能なボアサイズに形成されたスリーブ(330)をさらに備えることを特徴とする、上記[5]に記載のデバイス。
[7] 前記サブマウント(400)が、前記センサ(110)の電気出力信号に対して作用する能動回路(420)を有することを特徴とする、上記[1]から[6]の何れかに記載のデバイス。
[8] 前記ダイ(110)を包囲する前記キャビティ(140)が気密封止されることを特徴とする、上記[1]から[7]の何れかに記載のデバイス。
[9] フォトセンサを有するパッケージを製造する方法であって、
複数のサブマウント領域を含む第1ウェハ(620)を製造する処理と、
各々のダイ(110)がフォトセンサを有する複数のダイ(110)を前記複数のサブマウント領域のそれぞれに取り付けて、電気的に接続する処理と、
複数のキャップを前記第1ウェハ(620)にボンドする処理であって、前記複数のダイが、前記第1ウェハ(620)と前記複数のキャップのそれぞれとの間の個々のキャビティ(140)内において包囲され、前記複数のダイ(110)のそれぞれでは、前記ダイ(110)上のフォトセンサが光信号を受信するように配置される処理と、
前記の各処理によって得られる構造を分割して、前記ダイ(110)を含む複数のパッケージ(100)に分離する処理と
を有することを特徴とする方法。
[10] 前記第1ウェハ(620)を製造する処理が、前記複数のサブマウント領域の各々に能動回路(420)を形成することを有することを特徴とする、上記[9]に記載の方法。
[11] 基板を加工する処理であって、光電領域を有するフォトセンサを前記基板の表の面に形成するように基板を加工する処理と、
レンズ(150)を前記基板の裏の面に形成して、光を前記光電領域上に集光するようにする処理と
をさらに有することを特徴とする、上記[9]または[10]に記載の方法。
[12] 複数のポスト(160)を前記パッケージ(100)に取り付ける処理であって、前記複数のポスト(160)のそれぞれが、前記パッケージ(100)内のダイ(110)までの光信号の経路に沿うように取り付けられる、前記取り付ける処理をさらに有することを特徴とする、上記[9]、[10]または[11]に記載の方法。
[13] 前記複数のキャップが、第2ウェハ(630)に形成された個々の領域を有し、
前記複数のキャップを前記第1ウェハ(620)にボンドする処理が、前記第1ウェハ(620)に前記第2ウェハ(630)をボンドする処理を含むことを特徴とする、上記[9]、[10]、[11]または[12]に記載の方法。
[14] 前記キャップが前記第1ウェハにボンドされた時に、前記光信号の経路に配置されるレンズを有するように前記キャップを製造することを特徴とする、上記[9]、[10]、[11]、[12]または[13]に記載の方法。
[15] デバイスを製造するための方法であって、
光電領域を前記基板の表の面に有するセンサ(110)を形成するように基板を処理することと、
光信号を前記光電領域上に集光するレンズ(150)を、前記基板の裏の面に形成することとを有することを特徴とする方法。
[16] 前記レンズが屈折光学素子であることを特徴とする、上記[15]に記載の方法。
110 ダイ
112 ボンドパッド
120 サブマウント
122 導電ピラー
124 外部端子
130 キャップ
140 キャビティ
150 レンズ
160 位置決めポスト
230 キャップ
232 スタンドオフリング
250 レンズ
300 光アセンブリ
310 光ファイバコネクタ(フェルール)
320 光ファイバ
330 スリーブ
340 可撓性回路
400 サブマウント
420 能動回路(プリアンプ回路)
430 ボンドパッド
500 キャップ
510 スタンドオフリング
520 バッキングプレート
540 キャビティ
620 第1ウェハ(サブマウントウェハ)
630 第2ウェハ(キャップウェハ)
Claims (1)
- サブマウントと、
前記サブマウントに電気的に接続されるセンサを備えるダイと、
前記サブマウントに取り付けられ、前記ダイを包囲するキャビティを形成するキャップと、
光信号を前記センサの光電領域上に集光するレンズと
を備えることを特徴とするデバイス。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/665660 | 2003-09-19 | ||
US10/665,660 US6900509B2 (en) | 2003-09-19 | 2003-09-19 | Optical receiver package |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2005094009A true JP2005094009A (ja) | 2005-04-07 |
JP2005094009A5 JP2005094009A5 (ja) | 2007-07-12 |
JP5086521B2 JP5086521B2 (ja) | 2012-11-28 |
Family
ID=34312918
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004268066A Expired - Fee Related JP5086521B2 (ja) | 2003-09-19 | 2004-09-15 | 光受信機パッケージ |
Country Status (4)
Country | Link |
---|---|
US (2) | US6900509B2 (ja) |
JP (1) | JP5086521B2 (ja) |
CN (1) | CN100479197C (ja) |
DE (2) | DE102004025735B4 (ja) |
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- 2004-05-26 DE DE102004025735A patent/DE102004025735B4/de not_active Expired - Fee Related
- 2004-05-26 DE DE102004064081A patent/DE102004064081B9/de not_active Expired - Fee Related
- 2004-07-08 CN CNB2004100624783A patent/CN100479197C/zh not_active Expired - Fee Related
- 2004-09-09 US US10/938,291 patent/US6955934B2/en not_active Expired - Lifetime
- 2004-09-15 JP JP2004268066A patent/JP5086521B2/ja not_active Expired - Fee Related
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JP2013235000A (ja) * | 2012-05-09 | 2013-11-21 | Boeing Co:The | 耐久性を高めたフォトニック結晶センサパッケージング |
US10061093B2 (en) | 2012-05-09 | 2018-08-28 | The Boeing Company | Ruggedized photonic crystal sensor packaging |
US10338328B2 (en) | 2012-05-09 | 2019-07-02 | The Boeing Company | Ruggedized photonic crystal sensor packaging |
JP2015177125A (ja) * | 2014-03-17 | 2015-10-05 | 新光電気工業株式会社 | キャップ及びその製造方法、半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP5086521B2 (ja) | 2012-11-28 |
US20050062119A1 (en) | 2005-03-24 |
CN100479197C (zh) | 2009-04-15 |
DE102004025735B4 (de) | 2008-10-23 |
CN1599059A (zh) | 2005-03-23 |
DE102004064081B4 (de) | 2008-12-18 |
DE102004025735A1 (de) | 2005-04-21 |
US20050062117A1 (en) | 2005-03-24 |
US6900509B2 (en) | 2005-05-31 |
US6955934B2 (en) | 2005-10-18 |
DE102004064081B9 (de) | 2009-06-04 |
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