JP2005019883A - Multilayer substrate and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer substrate, as well as its manufacturing method, that can be made thin, excellent in mass-production, has a pattern accuracy, a lamination accuracy, and an insulating layer thickness accuracy, and is highly reliable. <P>SOLUTION: Conductor patterns 2a to 2f are formed onto transfer substrates 1a to 1f having conductivity. The conductor patterns 2a-2f formation surfaces of the transfer substrates 1a-1f are opposed, and are stuck with resinous sheets 4a-4d between the opposing surfaces. One transfer substrate of the two lamination element sheets 6a and 6b or 6c and 6d sticking the resinous sheets 4a-4d is peeled off and a new resinous sheet 4e and 4f are put between the peeled surfaces, and stuck. Such a step is repeated a required number of times to obtain a multilayer substrate. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【００３６】
本実施の形態によれば、下記の種々の効果をあげることができる。
（１）薄型化、高密度化が可能である。
機械的強度の大きなステンレス板等の転写用基板１を用いている上、全工程において、少なくとも片方に転写用基板があるので、樹脂シート４ａ〜４ｇからなる層間絶縁層そのものには機械的強度が要求されず、薄型化、高密度化が可能である。
【００３７】
（２）下記の理由で量産性に優れている。
（ａ）最初に転写用基板に導体パターンを一括して形成するのでリードタイム（製造時間）が短い。
（ｂ）積層素体シートを２枚ずつ積層していくので、ビルドアップ工法に比較して積層回数が少ない。
（ｃ）導電性転写用基板に直接導体パターンを形成する転写工法を用いているので、プリプレグ上にまず下地導体層を形成してその上にレジストパターンの形成、電解めっきによる導体パターンの形成を行うセミアディティブ工法に比較して下地導体層形成工程、下地導体層のエッチング工程が不要である。
【００３８】
（３）下記の理由でパターン精度、積層精度が良好である。
（ａ）転写用基板に導体パターンを直接電解めっきにより形成するフルアディティブ工法を採用できるので、パターニング精度が良好である。
（ｂ）積層時に基板の片面に必ず機械的強度の優れる転写用基板があるので、プレス前後の積層素体シートの縮率が小さい。
（ｃ）図７に示すように、転写用基板１にピンアライメント用の孔１３および導体パターンのアライメント用の孔１４またはマークを設けておき、これらの孔１４やマークをレジストパターン３形成のための位置合わせに用いれば、層間のアライメントはこれらの孔１３、１４やマークの位置合わせを行うことで転写用基板１を基準にして行えるので、積層精度（導体パターン２の横方向のずれの精度）がよい。
【００３９】
（４）下記の理由で樹脂シート４ａ〜４ｇによる相間絶縁層の厚さの精度がよい。
（ａ）樹脂シートへの転写のための一番最初のプレス以外は、転写用基板１の表面が平滑であるので、プレス時の樹脂の流れのむらがなく、また、プレス圧力が下げられる。
（ｂ）一番最初のプレス時に転写用基板の厚さ精度（厚さのばらつき）を小さく（例えば±２μｍ）することができるので、その結果、樹脂シートのプレス後の厚みのばらつきを小さくすることができる。
【００４０】
（５）少なくとも内部積層部においては、無電解めっき工程が不要になるので、エッチング液や触媒の残渣による信頼性の低下の問題を解決できる。
【００４１】
実施例１
（導体パターンの形成）図７に示すように、７６ｍｍ角、０．１ｍｍ厚のステンレス板（ＳＵＳ３０４ＴＡ材）１の４隅の所定の位置に直径３ｍｍの転写用基板積層時のピンアライメント用の穴１３を設けると共に、中央部の両端の所定の位置に０．２ｍｍの導体パターンアライメント用孔１４を開けたものを転写用基板として用いた。この転写用基板上に２５μｍ厚のドライフィルムでライン幅およびライン間隔（Ｌ＆Ｓ）が２０μｍのレジストパターンを形成して、硫酸銅めっき液で導体パターンを形成した。その後、有機系剥離液でレジストを剥離した後、黒化処理で銅でなる導体パターンの表面のみを選択的に粗面化した。
【００４２】
（絶縁層の形成）ビニルベンジル樹脂に高誘電率フィラーを４０ｖｏｌ％混合したものをＰＥＴフィルム上に４０μｍの厚さに形成して樹脂シートとした。この樹脂シートの１ＧＨｚにおける誘電率は１５であった。これを図３、図４に示したように、転写用基板間に挟み、２００℃の加熱状態で真空プレスで一体化した。プレス後の樹脂シートからなる絶縁層の厚さは２０μｍであった。
【００４３】
（絶縁層の形成）図５、図６で示したように、一方に転写用基板を剥離してその剥離面間に前記材質でなる樹脂シートを介在させてプレスするという工程と、表裏面の転写用基板を剥離する工程により、導体パターン２ａ〜２ｆ、絶縁層４ａ〜４ｇからなる積層素体シート９を得た。
【００４４】
（スルーホール、ビアホールの形成）図６（Ａ）、（Ｂ）に示したように、前記積層素体シート９にドリルにより直径０．２ｍｍのスルーホール１０を開けた。その後、レーザによりトップ径が７０μｍ、ボトム径が５０μｍのビアホール１１を形成した。
【００４５】
（表裏面の導体パターンの形成）無電解めっきにより、下地導体層１２として銅を０．３μｍの厚さに形成した。その後、レジストとして２５μｍ厚のドライフィルムを使用してライン幅およびライン間隔が２０μｍのレジストパターンを形成した。そして硫酸銅めっき液を使用して導体パターン２ｇ、２ｈを形成した。その後、クイックエッチングにより下地導体層１２を除去した。
【００４６】
（結果）実施例１の場合、リードタイム：２２時間、サンプル数が１シートで、絶縁層４ａ〜４ｈの層数が８層の場合の導体厚：２０μｍ±２μｍ、導体幅：２０μｍ±２μｍ、絶縁層厚：２０±２μｍ、積層精度：±２０μｍであった。
【００４７】
比較例１（ビルドアップ工法）
（コア基板）コア基板に１００μｍ厚のガラスクロス入りビニルベンジル樹脂を用いた。このコア基板に無電解めっきにより下地導体層を０．３μｍを形成した後、レジストパターンの形成、導体パターンの形成、クイックエッチングを、前記実施例１における積層素体シートの表裏面の導体パターンの形成と同様に行った。
【００４８】
（絶縁層の形成）ビニルベンジル樹脂に高誘電率フィラーを４０ｖｏｌ％混合したものを１８μｍ銅箔の上に４０μｍの厚みに形成した樹脂付き銅箔を、樹脂面をコア基板側にして熱プレスにより固着した。プレス後の絶縁層の１ＧＨｚにおける誘電率εは９．２であった。
【００４９】
（導体パターンの形成）前記実施例１における積層素体シートの表裏面に対する導体パターンの形成と同様に、下地導体層の形成、レジストパターンの形成、導体パターンの形成、クイックエッチングを行った。
【００５０】
（結果）リードタイム：３８時間、サンプル数が１シートで、絶縁層の層数が８層の場合の導体厚：２０μｍ±４μｍ、導体幅：２０μｍ±４μｍ、絶縁層厚：２０±３μｍ、積層精度：±２０μｍであった。
【００５１】
比較例２（プリプレグによる同時プレス）
コア基板に１００μｍ厚のガラスクロス入りビニルベンジル樹脂を用いた。このコア基板は両面に銅箔を貼り付けたものである。導体パターン形成のためのパターニングは、サブトラクティブ工法により行った。このライン幅およびライン間隔は６０μｍである。
【００５２】
（プレス）このようにして形成した４枚のコア基板を、コア基板間にそれぞれプリプレグを介在させて積層し、熱プレスにより一体化した。
【００５３】
（スルーホール、導体パターンの形成）実施例１と同様に、スルーホール形成、無電解めっき、レジストパターンの形成、硫酸銅めっき液を用いた電解めっきにより、２０μｍの厚みに銅でなる導体パターンを形成した。
【００５４】
（結果）リードタイム：１７時間、サンプル数が１シートで、絶縁層の層数が８層の場合の導体厚：１８μｍ±２μｍ、導体幅：６０μｍ±６μｍ、絶縁層厚：４０±５μｍ、積層精度：±５０μｍであった。
【００５５】
実施例２
前記実施例１における絶縁層の代わりにガラスクロス入りで厚さ６０μｍのプリプレグを使用した。このプリプレグの材質は実施例１と同じである。この場合、誘電率は１０に低下した。
【００５６】
（結果）リードタイム：２２時間、サンプル数が１シートで、絶縁層の層数が８層の場合の導体厚：２０μｍ±２μｍ、導体幅：２０μｍ±２μｍ、絶縁層厚：４０±２μｍ、積層精度：±２０μｍであった。
【００５７】
これらの実施例１、２によれば、比較例１のビルドアップ工法に比較してリードタイムを約半分に短縮でき、複数枚のコア基板をプレスにより同時に一体化する場合に近い短いリードタイムに短縮できる。また、比較例２の銅箔をサブトラクティブ工法によりパターン化する場合に比較し、導体厚さおよび幅の精度を向上させることができる。また、絶縁層厚さの精度、積層精度を向上させることができる。
【００５８】
本発明は、多層基板はその上に半導体素子やチップ部品を搭載したものとして構成することができ、また、多層構造を有する個々の電子部品として構成する場合にも本発明を適用することができる。本発明は、多層基板内にコンデンサが形成される場合あるいはコンデンサを含む電子部品として構成される場合、絶縁層（誘電体層）の薄型化が可能となることにより、高容量のコンデンサを実現することが可能となり、同じ取得容量であれば、電極面積を小さくすることができ、基板の小型化を図ることができる。
【００５９】
【発明の効果】
本発明によれば、機械的強度の大きなステンレス板等の転写用基板を製造に用いているので、樹脂シートからなる層間絶縁層そのものには機械的強度が要求されず、薄型化が可能である。
【００６０】
また、転写用基板に導体パターンを一括して形成しておくことができ、また、アディティブ工法を採用して導体パターンの形成が行え、下地電極層の形成、除去が不要になるので、製造時間を短縮でき、量産性に優れている。
【００６１】
また、転写用基板に導体パターンを直接電解めっきにより形成することができ、サブトラクティブ工法のように銅箔パターンにエッチングを行なわないことで、パターニング精度を向上させることができる。また、機械的強度の優れる転写用基板の使用により、プレス前後の積層素体シートの縮率が小さいため、導体パターンのずれが少なく、さらに転写用基板に位置合わせのための孔やマークにより導体パターン位置合わせを行うこともできるので、積層精度がよい。
【００６２】
また、最初のプレスを除き、転写用基板の表面を平滑にでき、プレス時の樹脂の流れのむらがなく、また、プレス圧力が下げられる上、一番最初のプレス時に積層素体シートの厚さのばらつきを小さくすることができる。その結果、樹脂シートのプレス後の厚みのばらつきを小さくすることができ、相間絶縁層の厚さの精度を向上させることができる。
【００６３】
また、少なくとも内部積層部においては、無電解めっき工程が不要になるので、エッチング液や触媒の残渣がなく、信頼性を向上させることができる。
【図面の簡単な説明】
【図１】本発明による多層基板の製造方法の一実施の形態を示す導体パターンの形成工程を示す図である。
【図２】本発明の多層基板の製造方法の一実施の形態における導体パターン形成転写用基板の構成例を示す図である。
【図３】本実施の形態における転写工程の一部を示す図である。
【図４】本実施の形態における転写工程の残部を示す図である。
【図５】本実施の形態における積層工程を示す図である。
【図６】本実施の形態におけるスルーホール、ビアホールおよび積層体表裏面の導体パターン形成工程を示す図である。
【図７】本発明において用いる転写用基板の一例を示す平面図である。
【符号の説明】
１、１ａ〜１ｆ：転写用基板、２、２ａ〜２ｆ：導体パターン、３：レジストパターン、４ａ〜４ｇ：樹脂シート（絶縁層）、５：ＰＥＴフィルム、６ａ〜６ｄ、７ａ、７ｂ、８、９：積層素体シート、１０：スルーホール、１１：ビアホール、１２：下地電極層、１３：ピンアライメント用孔、１４：導体パターンアライメント用孔[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multilayer substrate (including a case where it is configured as an electronic component) configured using a resin material or a composite material obtained by mixing powder in a resin and a method for manufacturing the same.
[0002]
[Prior art]
Conventionally, the following two manufacturing methods have been adopted as a manufacturing method of a multilayer substrate constituted by using a resin material or a composite material in which a powder such as ceramic is mixed with a resin. The first method is an example of a through-hole substrate. This is done by preparing a plurality of core substrates with conductor patterns formed on both sides, laminating each of these core substrates via a semi-cured prepreg, and curing the prepreg by hot pressing to form a plurality of core substrates. In this method, a through hole is formed in the laminate, and the through holes are plated to connect the internal conductors (see, for example, Patent Document 1 and FIG. 3). In this case, a subtractive method, a semi-additive method, and a full additive method are employed as a method for forming a conductor pattern.
[0003]
The second method is a build-up method using a surface layer BVH (blind via hole) (see, for example, Patent Document 2). This method repeats the process of thermocompression bonding of an insulating layer made of prepreg and copper foil on both sides of a core substrate on which a conductor pattern is formed, and patterning the copper foil, and then connecting conductors of different layers by through holes. . Then, the outermost conductor and the inner conductor are connected by BVH.
[0004]
[Patent Document 1]
JP 2003-151856 A [Patent Document 2]
Japanese Patent Laid-Open No. 2002-319764.
[0005]
[Problems to be solved by the invention]
Since the manufacturing method of the multilayer substrate described in Patent Document 1 requires the mechanical strength of the core substrate in handling, the core substrate and the prepreg that is the adhesive layer need to contain a core material such as a glass cloth, For this reason, the thickness of each layer cannot be reduced. Usually, it is difficult to make the thickness of the core substrate thinner than 60 μm, and it is difficult to reduce the thickness.
[0006]
In order to improve mechanical strength, it is necessary to insert the core material. However, when a capacitor is formed, the dielectric constant decreases, and the heat between capacitor electrodes cannot be reduced. There is a problem that cannot be taken.
[0007]
In addition, pin alignment is the main technique for alignment between layers, and the stacking accuracy (shift of the conductor pattern) is poor, and there is a possibility that a shift of about 50 to 100 μm at maximum is usually generated.
[0008]
On the other hand, the build-up method described in Patent Document 2 has a problem that the number of steps increases and the mass productivity is inferior. Similarly to the method described in Patent Document 1, the core substrate is required to have mechanical strength, and it is difficult to reduce the thickness and increase the density.
[0009]
There is also a method of forming a resist pattern on electroless plating instead of copper foil, and forming a conductor pattern by electroplating, but it is necessary to perform quick (soft) etching of electroless plating, and electroless In particular, there is a problem in that the residue or the like of the base catalyst for plating (Pd or the like) tends to cause migration or corrosion particularly in the inner laminated portion, and the reliability is lowered.
[0010]
In view of the above problems, an object of the present invention is to provide a multilayer substrate that can be thinned, is excellent in mass productivity, has good pattern accuracy and lamination accuracy, and has high reliability, and a method for manufacturing the same. .
[0011]
[Means for Solving the Problems]
(1) In the method for producing a multilayer substrate of the present invention, a conductive pattern is formed on a transfer substrate having conductivity,
A laminated body sheet is configured by adhering a resin sheet between the conductor pattern forming surfaces of the two transfer substrates on which the conductor patterns are formed,
It is necessary to repeat the process of peeling the transfer substrate on one side of each of the two laminated body sheets and sandwiching and fixing a new resin sheet between the peeled surfaces to obtain a laminate that becomes a multilayer substrate. Features.
[0012]
(2) Moreover, the manufacturing method of the multilayer board | substrate of this invention is the said (1),
A stainless plate is used as the transfer substrate.
[0013]
(3) The multilayer substrate of the present invention is a multilayer substrate obtained by the method for producing a multilayer substrate according to (1) or (2) above, wherein the insulating layer composed of the resin sheet is made of a functional material powder. It is characterized by comprising a vinylbenzyl resin.
[0014]
(4) Moreover, the multilayer board | substrate of this invention is a multilayer board | substrate obtained by the manufacturing method of the multilayer board | substrate as described in said (1) or (2), Comprising: The insulating layer comprised by the said resin sheet has a core material. It consists of the material which does not contain.
[0015]
(5) Moreover, the multilayer board | substrate of this invention is a multilayer board | substrate as described in said (3) or (4), Comprising: The capacitor is incorporated, It is characterized by the above-mentioned.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
1 to 6 are views showing an embodiment of a method for producing a multilayer substrate according to the present invention. The example of FIG. 1 is a method of forming a conductor pattern 2 on a transfer substrate 1 by a full additive method. In FIG. 1A, reference numeral 1 denotes a transfer substrate, and the transfer substrate 1 is made of a conductive material, and preferably has strength, smoothness, corrosion resistance, and peelability of plated metal. . As such a transfer substrate 1, any metal such as stainless steel, titanium, tungsten, tantalum, iron, aluminum, nickel, etc., on which a passive film (porous oxide film) is easily formed can be used. is there. Of these, the use of a stainless steel plate is preferable in terms of strength, smoothness, corrosion resistance, and easy removal of the plated metal.
[0017]
As shown in FIG. 1B, a resist pattern 3 is formed on the transfer substrate 1 by printing or photolithography. Then, as shown in FIG. 1C, a conductor that becomes a conductor pattern 2 such as a coil, a wiring, a capacitor electrode, etc. is formed on the surface of the transfer substrate 1 where the resist is not formed by electroplating (full additive method). A film is formed.
[0018]
Here, copper, aluminum, nickel, gold, silver, platinum, tin, lead or the like is used as the metal forming the conductor film. Of these, copper is preferable because of its low resistivity, good migration resistance, and low cost. After the conductor pattern 2 is formed, the resist pattern 3 is removed as shown in FIG.
[0019]
When the conductor pattern 2 is formed on the transfer substrate 1 by such a process, the transfer substrate 1 preferably has a surface roughness Rmax in the range of 0.2 to 2 μm. When Rmax is less than 0.2 μm, the adhesion between the resist and the conductor pattern and the transfer substrate 1 becomes insufficient, and it is not preferable because it easily peels off. On the other hand, if Rmax exceeds 2 μm, the film thickness variation of the conductor pattern is affected, and when used for high frequency, the conductor loss increases, which is not preferable. When copper is used as the conductor pattern 2 and a stainless steel plate is used for the transfer substrate 1, it is preferable to form a passive film on the surface of the stainless steel plate by a passivation treatment in order to ensure peelability from copper.
[0020]
When producing a multilayer substrate, the required number of transfer substrates 1 on which the conductor pattern 2 as shown in FIG. 1 is formed are prepared. FIG. 2 shows an example of preparing six transfer substrates 1a to 1f on which conductor patterns 2a to 2f are respectively formed in order to produce the multilayer substrate of the present embodiment. In this example, the same conductor patterns 2a to 2f are shown for simplification of explanation, but each of the conductor patterns 2a to 2f corresponds to the configuration of wirings and elements (inductors, capacitors, etc.) built in the multilayer substrate to be manufactured. It is formed in the shape of 2f. For ease of understanding, in FIG. 2, transfer substrates 1a to 1f are drawn in accordance with the vertical direction of the layers in the final product.
[0021]
Using the transfer substrates 1a to 1f having the conductor patterns 2a to 2f shown in FIG. 2, a multilayer substrate is manufactured by the steps shown in FIGS. FIG. 3 shows a transfer process to the resin sheet 4a (or 4d) for the uppermost transfer substrate 1a and the lowermost transfer substrate 1f among the transfer substrates. As shown in FIG. 3 (A), 4a (4d) is formed on the PET film 5 with a predetermined thickness. When transferring to the resin sheet 4a (4d), the PET sheet 5 is Then, the resin sheet 4a (4d) is overlaid on the surface of the transfer substrate 1a, (1f) on which the conductor pattern 2a (2f) is formed, the PET sheet 5 is peeled off, and as shown in FIG. 4d) Another transfer substrate 1g (or 1h) is stacked and fixed thereon. In this fixing step, the resin is cured by pressure bonding in a heated state. This heating temperature is preferably 190 to 210 ° C. in the case of vinylbenzyl resin.
[0022]
FIG. 4 shows a process of transferring the transfer substrates 1b and 1c (or 1d and 1e) to the resin sheet 4b (or 4c), respectively. Also in this case, the resin sheet 4b (4c) from which the PET film 5 has been peeled is overlaid on the transfer substrate 1c (1e) on which the conductor pattern 2c (2e) is formed, and the conductor pattern 2b (2d) side is placed thereon. Then, the transfer substrate 1b (1d) is stacked and integrated by hot pressing in the same manner as described above. The resin sheets 4a to 4d serve as an insulating layer.
[0023]
FIG. 5A shows laminated body sheets 6a to 6d in which the transfer substrate and the resin sheet are integrated as described above.
[0024]
As shown in FIG. 5A, when the transfer substrates 1a and 1b on the surfaces to be joined of the laminated body sheets 6a and 6b obtained in the above process are peeled off, the conductor patterns 2a and 2b are formed on the surface. A sheet formed on the same surface as the surfaces of the sheets 4a and 4b, that is, the conductor patterns 2a and 2b embedded in the resin sheets 4a and 4b is obtained. As shown in FIG. 5 (B), the resin sheet 4e is newly sandwiched between the peeled surfaces from which the transfer substrates 1a and 1b have been peeled in this manner, as in the case of FIG. 3 and FIG. A laminated body sheet 7a is newly obtained.
[0025]
Similarly, for the laminated body sheets 6c and 6d, the transfer substrates 1e and 1f on the surfaces to be joined are peeled off, and a new resin sheet is formed between the resin sheets 4c and 4d where the conductor patterns 2e and 2f are exposed on the surface. The laminated body sheets 6c and 6d are thermocompression bonded with 4f interposed therebetween to obtain a new laminated body sheet 7b as shown in FIG. 5B.
[0026]
After that, the transfer substrates 1c and 1d on the surfaces to be joined of the multilayer body sheets 7a and 7b shown in FIG. 5B are peeled off, and as shown in FIG. A laminated body sheet 8 having an insulating layer formed by interposing the resin sheet 4g between the conductor patterns 2c and 2d by thermocompression bonding the laminated body sheets 7a and 7b with a resin sheet 4g newly sandwiched between 7b. obtain.
[0027]
When the resin sheet 4a-4g forms a capacitor electrode as a conductor pattern, the thickness of the conductor layer of the capacitor electrode is 10 times or less, preferably 5 times or less, more preferably 3 times the thickness of the resin sheet 4a-4g. No more than twice, most preferably no more than 2 times, and the effect of increasing the capacitance becomes more conspicuous as the thickness is reduced.
[0028]
Moreover, it is preferable to raise the adhesive strength with the resin sheets 4a-4g by roughening the surface of the conductor patterns 2a-2f. For the roughening of the conductor patterns 2a to 2f, for example, blackening treatment such as Probond 80 manufactured by Shipley First East Co., Ltd., CZ treatment (surface roughening using formic acid) manufactured by MEC Co., Ltd., multi bond processing manufactured by Nihon McDermid Co., Ltd. It is preferable to use (roughening with a sulfuric acid / hydrogen peroxide-based etching solution) or the like. Of these, roughening with a sulfuric acid / hydrogen peroxide-based etching solution is preferable because it can be made chlorine-free.
[0029]
Further, by using the transfer substrate 1 having a smooth surface, the surfaces of the conductor patterns 2a to 2f formed by being embedded in the resin sheets 4a to 4d by transfer and the resin sheets 4a to 4d become smooth. . Here, the term “smooth” means that the step on the surface of the conductor film constituting the conductor patterns 2a to 2f has a value of 1/2 or less, preferably 1/3 or less, more preferably 1/4 or less of the thickness of the conductor film. It is formed so that it becomes.
[0030]
As shown in FIG. 6 (A), for the laminated body sheet 8 as shown in FIG. 5 (C), the transfer substrates 1g and 1h on the front and back surfaces of the laminated body sheet 8 are peeled off and the laminated body sheet 9 is peeled off. Get. Subsequently, as shown in FIG. 6 (A), through holes 10 are opened in necessary portions of the multilayer body sheet 9, and further, as shown in FIG. 6 (B), the front and back surfaces and the front and back surfaces of the multilayer body sheet 9 are the most. A portion of the conductor pattern 2 a, 2 f in the layer close to is exposed by the via hole 11.
[0031]
Thereafter, as shown in FIG. 6C, a base conductor layer 12 for electrolytic plating is formed on the front and back surfaces of the multilayer body sheet 9, the through holes 10 and the via holes 11 by electroless plating. Subsequently, as shown in FIG. 6D, conductor patterns 2g and 2h are formed on the front and back surfaces of the multilayer body sheet 9 using a photolithography method. Thereafter, as shown in FIG. 6E, the underlying conductor layer 12 is removed by quick etching. Thereafter, each product is cut into products.
[0032]
The resin sheets 4a to 4g are preferably organic materials with Q> 100 at 1 GHz in consideration of high-frequency characteristics. In addition to vinylbenzyl resin (Q = 200 to 250), high-frequency BT resin (Q = 150 to 500) ) Etc. are also possible. By using such a resin having a high Q value, a multilayer substrate having a high Q value can be obtained. It is possible to use other thermosetting resins or thermoplastic resins as long as the peelability to the transfer substrate 1 can be secured.
[0033]
In addition, when mechanical strength is required, core materials, such as a glass cloth, an aramid nonwoven fabric, and a fluororesin porous sheet, can be used. However, since the surface of the insulating layer formed by the resin sheet also has unevenness due to the unevenness of the core material such as glass cloth, the thickness variation between the conductor patterns 2a to 2f increases, and the core material and the resin Therefore, if possible, it is preferable not to insert the core material.
[0034]
Depending on the purpose, the resin sheets 4a to 4g may be mixed with an appropriate powder, such as a high dielectric constant powder or a magnetic powder. Table 1 shows an example of a dielectric constant and a Q value of a resin sheet obtained by mixing a vinylbenzyl resin and a high dielectric constant filler (Ba-Ti-Nb ceramic having a dielectric constant of about 90). When a capacitor is formed in a multilayer substrate, a capacitor having a higher capacity can be obtained by mixing high dielectric constant powder.
[0035]
[Table 1]

[0036]
According to the present embodiment, the following various effects can be obtained.
(1) Thinning and high density are possible.
Since the transfer substrate 1 such as a stainless plate having a high mechanical strength is used and the transfer substrate is present in at least one of all the processes, the interlayer insulating layer itself composed of the resin sheets 4a to 4g has a mechanical strength. It is not required and can be reduced in thickness and density.
[0037]
(2) It is excellent in mass productivity for the following reasons.
(A) First, a conductor pattern is collectively formed on a transfer substrate, so that the lead time (manufacturing time) is short.
(B) Since the laminated body sheets are laminated two by two, the number of lamination is less than that in the build-up method.
(C) Since a transfer method in which a conductor pattern is directly formed on a conductive transfer substrate is used, a base conductor layer is first formed on a prepreg, and then a resist pattern is formed thereon, and a conductor pattern is formed by electrolytic plating. Compared to the semi-additive method to be performed, the base conductor layer forming step and the base conductor layer etching step are not required.
[0038]
(3) The pattern accuracy and stacking accuracy are good for the following reasons.
(A) Since a full additive method in which a conductor pattern is directly formed on the transfer substrate by electrolytic plating can be adopted, the patterning accuracy is good.
(B) Since there is always a transfer substrate having excellent mechanical strength on one side of the substrate during lamination, the reduction ratio of the laminated body sheet before and after pressing is small.
(C) As shown in FIG. 7, the transfer substrate 1 is provided with pin alignment holes 13 and conductor pattern alignment holes 14 or marks, and these holes 14 and marks are used for forming the resist pattern 3. Since the alignment between the layers can be performed with reference to the transfer substrate 1 by aligning the holes 13 and 14 and the marks, the stacking accuracy (accuracy of the lateral displacement of the conductor pattern 2) is used. ) Is good.
[0039]
(4) The accuracy of the thickness of the interphase insulating layer by the resin sheets 4a to 4g is good for the following reasons.
(A) Since the surface of the transfer substrate 1 is smooth except for the first press for transfer to the resin sheet, there is no uneven flow of the resin during pressing, and the press pressure is reduced.
(B) Since the thickness accuracy (thickness variation) of the transfer substrate can be reduced (for example, ± 2 μm) at the very first pressing, as a result, the thickness variation after pressing of the resin sheet is reduced. be able to.
[0040]
(5) Since the electroless plating step is not required at least in the inner laminated portion, it is possible to solve the problem of lowering reliability due to the etching solution and the residue of the catalyst.
[0041]
Example 1
(Conductor pattern formation) As shown in FIG. 7, holes for pin alignment when laminating a transfer substrate having a diameter of 3 mm at predetermined positions of four corners of a stainless steel plate (SUS304TA material) 1 of 76 mm square and 0.1 mm thickness 13 and having a 0.2 mm conductor pattern alignment hole 14 formed at a predetermined position at both ends of the central portion was used as a transfer substrate. A resist pattern having a line width and a line spacing (L & S) of 20 μm was formed on the transfer substrate with a dry film having a thickness of 25 μm, and a conductor pattern was formed with a copper sulfate plating solution. Thereafter, after removing the resist with an organic stripping solution, only the surface of the conductor pattern made of copper was selectively roughened by blackening treatment.
[0042]
(Formation of Insulating Layer) A resin sheet was prepared by mixing a vinyl benzyl resin with 40 vol% of a high dielectric constant filler on a PET film to a thickness of 40 μm. The dielectric constant of this resin sheet at 1 GHz was 15. As shown in FIGS. 3 and 4, this was sandwiched between transfer substrates and integrated by a vacuum press in a heated state at 200.degree. The thickness of the insulating layer made of the resin sheet after pressing was 20 μm.
[0043]
(Formation of Insulating Layer) As shown in FIGS. 5 and 6, the process of peeling the transfer substrate on one side and pressing the resin sheet made of the above material between the peeling surfaces, By the process of peeling the transfer substrate, a multilayer body sheet 9 composed of the conductor patterns 2a to 2f and the insulating layers 4a to 4g was obtained.
[0044]
(Formation of Through Hole and Via Hole) As shown in FIGS. 6 (A) and 6 (B), a through hole 10 having a diameter of 0.2 mm was opened in the multilayer body sheet 9 by a drill. Thereafter, via holes 11 having a top diameter of 70 μm and a bottom diameter of 50 μm were formed by laser.
[0045]
(Formation of Conductor Patterns on Front and Back Surfaces) Copper was formed to a thickness of 0.3 μm as the underlying conductor layer 12 by electroless plating. Thereafter, a resist pattern having a line width and a line interval of 20 μm was formed using a dry film having a thickness of 25 μm as a resist. And the conductor patterns 2g and 2h were formed using the copper sulfate plating solution. Thereafter, the underlying conductor layer 12 was removed by quick etching.
[0046]
(Result) In the case of Example 1, the lead time is 22 hours, the number of samples is one sheet, and the number of insulating layers 4a to 4h is eight. Conductor thickness: 20 μm ± 2 μm, Conductor width: 20 μm ± 2 μm, The insulating layer thickness was 20 ± 2 μm, and the lamination accuracy was ± 20 μm.
[0047]
Comparative example 1 (build-up method)
(Core Substrate) A vinylbenzyl resin containing glass cloth having a thickness of 100 μm was used for the core substrate. After forming a base conductor layer of 0.3 μm on the core substrate by electroless plating, resist pattern formation, conductor pattern formation, and quick etching are performed on the conductor patterns on the front and back surfaces of the multilayer body sheet in Example 1. Performed similarly to formation.
[0048]
(Formation of Insulating Layer) Resin-coated copper foil formed by mixing vinylbenzyl resin with 40 vol% of high dielectric constant filler on 18 μm copper foil to a thickness of 40 μm was subjected to hot pressing with the resin surface as the core substrate side. Stuck. The dielectric constant ε at 1 GHz of the insulating layer after pressing was 9.2.
[0049]
(Formation of Conductor Pattern) In the same manner as the formation of the conductor pattern on the front and back surfaces of the multilayer body sheet in Example 1, formation of the underlying conductor layer, formation of the resist pattern, formation of the conductor pattern, and quick etching were performed.
[0050]
(Result) Lead time: 38 hours, sample number is 1 sheet, and the number of insulating layers is 8 conductor thickness: 20 μm ± 4 μm, conductor width: 20 μm ± 4 μm, insulating layer thickness: 20 ± 3 μm, lamination Accuracy: ± 20 μm.
[0051]
Comparative Example 2 (simultaneous pressing with prepreg)
A vinyl benzyl resin containing glass cloth having a thickness of 100 μm was used for the core substrate. This core substrate has copper foil attached on both sides. Patterning for forming a conductor pattern was performed by a subtractive method. The line width and line interval are 60 μm.
[0052]
(Press) The four core substrates formed in this manner were laminated with a prepreg interposed between the core substrates, and integrated by hot pressing.
[0053]
(Formation of through-holes and conductor patterns) Similar to Example 1, through-hole formation, electroless plating, resist pattern formation, and electroplating using a copper sulfate plating solution, a conductor pattern made of copper with a thickness of 20 μm was formed. Formed.
[0054]
(Result) Lead time: 17 hours, sample number is one sheet, and the number of insulating layers is 8 conductor thickness: 18 μm ± 2 μm, conductor width: 60 μm ± 6 μm, insulating layer thickness: 40 ± 5 μm, lamination Accuracy: ± 50 μm.
[0055]
Example 2
Instead of the insulating layer in Example 1, a prepreg with a glass cloth and a thickness of 60 μm was used. The material of this prepreg is the same as that of Example 1. In this case, the dielectric constant decreased to 10.
[0056]
(Result) Lead time: 22 hours, sample number is one sheet, and the number of insulating layers is 8 conductor thickness: 20 μm ± 2 μm, conductor width: 20 μm ± 2 μm, insulating layer thickness: 40 ± 2 μm, lamination Accuracy: ± 20 μm.
[0057]
According to these Examples 1 and 2, the lead time can be shortened to about half compared to the build-up method of Comparative Example 1, and the lead time is close to the case where a plurality of core substrates are integrated simultaneously by pressing. Can be shortened. Moreover, compared with the case where the copper foil of the comparative example 2 is patterned by a subtractive construction method, the precision of a conductor thickness and a width | variety can be improved. In addition, the accuracy of the insulating layer thickness and the stacking accuracy can be improved.
[0058]
In the present invention, the multilayer substrate can be configured as a semiconductor element or chip component mounted thereon, and the present invention can also be applied to a case where the multilayer substrate is configured as an individual electronic component having a multilayer structure. . The present invention realizes a high-capacitance capacitor by enabling the insulating layer (dielectric layer) to be thin when a capacitor is formed in a multilayer substrate or as an electronic component including a capacitor. If the same acquisition capacity is obtained, the electrode area can be reduced, and the substrate can be reduced in size.
[0059]
【The invention's effect】
According to the present invention, since a transfer substrate such as a stainless plate having high mechanical strength is used for manufacturing, the interlayer insulating layer made of a resin sheet itself does not require mechanical strength and can be thinned. .
[0060]
In addition, the conductor pattern can be formed in a batch on the transfer substrate, and the conductive pattern can be formed by adopting the additive method, so that the formation and removal of the base electrode layer is not required. And is excellent in mass productivity.
[0061]
In addition, the conductor pattern can be directly formed on the transfer substrate by electrolytic plating, and the patterning accuracy can be improved by not etching the copper foil pattern unlike the subtractive method. Also, due to the use of a transfer substrate with excellent mechanical strength, the contraction rate of the laminated body sheet before and after pressing is small, so there is little displacement of the conductor pattern, and the conductor is formed by holes and marks for alignment with the transfer substrate. Since pattern alignment can also be performed, the stacking accuracy is good.
[0062]
Also, except for the first press, the surface of the transfer substrate can be smoothed, there is no uneven flow of resin during pressing, the pressing pressure can be reduced, and the thickness of the laminated body sheet during the first pressing The variation of can be reduced. As a result, variation in thickness of the resin sheet after pressing can be reduced, and the accuracy of the thickness of the interphase insulating layer can be improved.
[0063]
Further, at least in the inner laminated portion, an electroless plating step is not required, so that there is no etching solution or catalyst residue, and reliability can be improved.
[Brief description of the drawings]
FIG. 1 is a diagram showing a process of forming a conductor pattern showing an embodiment of a method for producing a multilayer board according to the present invention.
FIG. 2 is a diagram showing a configuration example of a conductive pattern formation transfer substrate in an embodiment of the method for producing a multilayer substrate of the present invention.
FIG. 3 is a diagram showing a part of a transfer process in the present embodiment.
FIG. 4 is a diagram showing the remaining part of the transfer process in the present embodiment.
FIG. 5 is a diagram showing a stacking process in the present embodiment.
FIG. 6 is a diagram showing a conductor pattern forming process for through holes, via holes, and front and back surfaces of a laminate in the present embodiment.
FIG. 7 is a plan view showing an example of a transfer substrate used in the present invention.
[Explanation of symbols]
1, 1a-1f: transfer substrate, 2, 2a-2f: conductor pattern, 3: resist pattern, 4a-4g: resin sheet (insulating layer), 5: PET film, 6a-6d, 7a, 7b, 8, 9: laminated body sheet, 10: through hole, 11: via hole, 12: base electrode layer, 13: hole for pin alignment, 14: hole for conductor pattern alignment

Claims (5)

A conductive pattern is formed on a transfer substrate having conductivity,
A laminated body sheet is formed by fixing a resin sheet between the conductor pattern forming surfaces of the two transfer substrates on which the conductor pattern is formed,
It is necessary to repeat the process of peeling the transfer substrate on one side of each of the two laminated body sheets and sandwiching and fixing a new resin sheet between the peeled surfaces to obtain a laminate that becomes a multilayer substrate. A method for producing a multilayer substrate, which is characterized. In the manufacturing method of the multilayer substrate according to claim 1,
A method of manufacturing a multilayer substrate, wherein a stainless steel plate is used as the transfer substrate. A multilayer substrate obtained by the method for producing a multilayer substrate according to claim 1 or 2, wherein the insulating layer made of the resin sheet is made of a vinylbenzyl resin containing a functional material powder. substrate. 3. The multilayer substrate obtained by the method for producing a multilayer substrate according to claim 1, wherein the insulating layer formed of the resin sheet is made of a material not including a core material. The multilayer board according to claim 3 or 4, wherein a capacitor is built in the multilayer board.

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