JP2004511039A5 - - Google Patents

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Publication number
JP2004511039A5
JP2004511039A5 JP2002533059A JP2002533059A JP2004511039A5 JP 2004511039 A5 JP2004511039 A5 JP 2004511039A5 JP 2002533059 A JP2002533059 A JP 2002533059A JP 2002533059 A JP2002533059 A JP 2002533059A JP 2004511039 A5 JP2004511039 A5 JP 2004511039A5
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JP
Japan
Prior art keywords
bit
data word
shift
portions
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002533059A
Other languages
English (en)
Japanese (ja)
Other versions
JP5133491B2 (ja
JP2004511039A (ja
Filing date
Publication date
Priority claimed from GB0024311A external-priority patent/GB2367650B/en
Application filed filed Critical
Publication of JP2004511039A publication Critical patent/JP2004511039A/ja
Publication of JP2004511039A5 publication Critical patent/JP2004511039A5/ja
Application granted granted Critical
Publication of JP5133491B2 publication Critical patent/JP5133491B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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JP2002533059A 2000-10-04 2001-08-21 単一命令多数データ処理 Expired - Lifetime JP5133491B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB0024311A GB2367650B (en) 2000-10-04 2000-10-04 Single instruction multiple data processing
GB0024311.3 2000-10-04
PCT/GB2001/003744 WO2002029553A1 (en) 2000-10-04 2001-08-21 Single instruction multiple data processing

Publications (3)

Publication Number Publication Date
JP2004511039A JP2004511039A (ja) 2004-04-08
JP2004511039A5 true JP2004511039A5 (enExample) 2012-11-22
JP5133491B2 JP5133491B2 (ja) 2013-01-30

Family

ID=9900674

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002533059A Expired - Lifetime JP5133491B2 (ja) 2000-10-04 2001-08-21 単一命令多数データ処理

Country Status (11)

Country Link
US (1) US6999985B2 (enExample)
EP (1) EP1323031B1 (enExample)
JP (1) JP5133491B2 (enExample)
KR (1) KR100880614B1 (enExample)
CN (1) CN1196998C (enExample)
GB (1) GB2367650B (enExample)
IL (2) IL151395A0 (enExample)
MY (1) MY129332A (enExample)
RU (1) RU2279706C2 (enExample)
TW (1) TW548587B (enExample)
WO (1) WO2002029553A1 (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003114323A (ja) * 2001-10-04 2003-04-18 Bridgestone Corp 近赤外線吸収フィルム
JP3857614B2 (ja) * 2002-06-03 2006-12-13 松下電器産業株式会社 プロセッサ
US20030231660A1 (en) * 2002-06-14 2003-12-18 Bapiraju Vinnakota Bit-manipulation instructions for packet processing
US8082419B2 (en) 2004-03-30 2011-12-20 Intel Corporation Residual addition for video software techniques
US7584233B2 (en) * 2005-06-28 2009-09-01 Qualcomm Incorporated System and method of counting leading zeros and counting leading ones in a digital signal processor
US7840954B2 (en) * 2005-11-29 2010-11-23 International Business Machines Corporation Compilation for a SIMD RISC processor
US8290095B2 (en) * 2006-03-23 2012-10-16 Qualcomm Incorporated Viterbi pack instruction
US8493979B2 (en) * 2008-12-30 2013-07-23 Intel Corporation Single instruction processing of network packets
US8495341B2 (en) * 2010-02-17 2013-07-23 International Business Machines Corporation Instruction length based cracking for instruction of variable length storage operands
GB2481384B (en) * 2010-06-21 2018-10-10 Advanced Risc Mach Ltd Key allocation when tracing data processing systems
WO2012134321A1 (en) * 2011-03-30 2012-10-04 Intel Corporation Simd integer addition including mathematical operation on masks
WO2012137428A1 (ja) * 2011-04-08 2012-10-11 パナソニック株式会社 データ処理装置、及びデータ処理方法
US20130113809A1 (en) 2011-11-07 2013-05-09 Nvidia Corporation Technique for inter-procedural memory address space optimization in gpu computing compiler
CN103092571B (zh) * 2013-01-10 2016-06-22 浙江大学 支持多种数据类型的单指令多数据算术单元
US20190196787A1 (en) * 2017-12-21 2019-06-27 Intel Corporation Apparatus and method for right shifting packed quadwords and extracting packed doublewords
KR102182299B1 (ko) * 2019-07-24 2020-11-24 에스케이텔레콤 주식회사 시프트 연산 장치 및 그의 동작 방법

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4785393A (en) * 1984-07-09 1988-11-15 Advanced Micro Devices, Inc. 32-Bit extended function arithmetic-logic unit on a single chip
EP0540150B1 (en) * 1991-10-29 1999-06-02 Advanced Micro Devices, Inc. Arithmetic logic unit
US5673321A (en) * 1995-06-29 1997-09-30 Hewlett-Packard Company Efficient selection and mixing of multiple sub-word items packed into two or more computer words
US6237016B1 (en) * 1995-09-05 2001-05-22 Intel Corporation Method and apparatus for multiplying and accumulating data samples and complex coefficients
US5835782A (en) * 1996-03-04 1998-11-10 Intel Corporation Packed/add and packed subtract operations
US5812140A (en) * 1996-09-05 1998-09-22 Adobe Systems Incorporated Efficient gray tile storage
US6061783A (en) * 1996-11-13 2000-05-09 Nortel Networks Corporation Method and apparatus for manipulation of bit fields directly in a memory source
US6081824A (en) * 1998-03-05 2000-06-27 Intel Corporation Method and apparatus for fast unsigned integral division
JPH11272546A (ja) * 1998-03-23 1999-10-08 Nec Corp 可変長レジスタ装置
US6338135B1 (en) * 1998-11-20 2002-01-08 Arm Limited Data processing system and method for performing an arithmetic operation on a plurality of signed data values

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