KR100880614B1 - 단일 명령어 다중 데이터 처리 - Google Patents
단일 명령어 다중 데이터 처리 Download PDFInfo
- Publication number
- KR100880614B1 KR100880614B1 KR1020037004621A KR20037004621A KR100880614B1 KR 100880614 B1 KR100880614 B1 KR 100880614B1 KR 1020037004621 A KR1020037004621 A KR 1020037004621A KR 20037004621 A KR20037004621 A KR 20037004621A KR 100880614 B1 KR100880614 B1 KR 100880614B1
- Authority
- KR
- South Korea
- Prior art keywords
- bit
- data word
- portions
- shift
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/3001—Arithmetic instructions
- G06F9/30014—Arithmetic instructions with variable precision
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30025—Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
- G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/3808—Details concerning the type of numbers or the way they are handled
- G06F2207/3828—Multigauge devices, i.e. capable of handling packed numbers without unpacking them
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/499—Denomination or exception handling, e.g. rounding or overflow
- G06F7/49931—Modulo N reduction of final result
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Software Systems (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Computational Mathematics (AREA)
- Mathematical Physics (AREA)
- Mathematical Optimization (AREA)
- Computing Systems (AREA)
- Executing Machine-Instructions (AREA)
- Advance Control (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0024311A GB2367650B (en) | 2000-10-04 | 2000-10-04 | Single instruction multiple data processing |
| GB0024311.3 | 2000-10-04 | ||
| PCT/GB2001/003744 WO2002029553A1 (en) | 2000-10-04 | 2001-08-21 | Single instruction multiple data processing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20030066631A KR20030066631A (ko) | 2003-08-09 |
| KR100880614B1 true KR100880614B1 (ko) | 2009-01-30 |
Family
ID=9900674
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020037004621A Expired - Lifetime KR100880614B1 (ko) | 2000-10-04 | 2001-08-21 | 단일 명령어 다중 데이터 처리 |
Country Status (11)
| Country | Link |
|---|---|
| US (1) | US6999985B2 (enExample) |
| EP (1) | EP1323031B1 (enExample) |
| JP (1) | JP5133491B2 (enExample) |
| KR (1) | KR100880614B1 (enExample) |
| CN (1) | CN1196998C (enExample) |
| GB (1) | GB2367650B (enExample) |
| IL (2) | IL151395A0 (enExample) |
| MY (1) | MY129332A (enExample) |
| RU (1) | RU2279706C2 (enExample) |
| TW (1) | TW548587B (enExample) |
| WO (1) | WO2002029553A1 (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102182299B1 (ko) * | 2019-07-24 | 2020-11-24 | 에스케이텔레콤 주식회사 | 시프트 연산 장치 및 그의 동작 방법 |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003114323A (ja) * | 2001-10-04 | 2003-04-18 | Bridgestone Corp | 近赤外線吸収フィルム |
| JP3857614B2 (ja) * | 2002-06-03 | 2006-12-13 | 松下電器産業株式会社 | プロセッサ |
| US20030231660A1 (en) * | 2002-06-14 | 2003-12-18 | Bapiraju Vinnakota | Bit-manipulation instructions for packet processing |
| US8082419B2 (en) | 2004-03-30 | 2011-12-20 | Intel Corporation | Residual addition for video software techniques |
| US7584233B2 (en) * | 2005-06-28 | 2009-09-01 | Qualcomm Incorporated | System and method of counting leading zeros and counting leading ones in a digital signal processor |
| US7840954B2 (en) * | 2005-11-29 | 2010-11-23 | International Business Machines Corporation | Compilation for a SIMD RISC processor |
| US8290095B2 (en) * | 2006-03-23 | 2012-10-16 | Qualcomm Incorporated | Viterbi pack instruction |
| US8493979B2 (en) * | 2008-12-30 | 2013-07-23 | Intel Corporation | Single instruction processing of network packets |
| US8495341B2 (en) * | 2010-02-17 | 2013-07-23 | International Business Machines Corporation | Instruction length based cracking for instruction of variable length storage operands |
| GB2481384B (en) * | 2010-06-21 | 2018-10-10 | Advanced Risc Mach Ltd | Key allocation when tracing data processing systems |
| WO2012134321A1 (en) * | 2011-03-30 | 2012-10-04 | Intel Corporation | Simd integer addition including mathematical operation on masks |
| WO2012137428A1 (ja) * | 2011-04-08 | 2012-10-11 | パナソニック株式会社 | データ処理装置、及びデータ処理方法 |
| US20130113809A1 (en) | 2011-11-07 | 2013-05-09 | Nvidia Corporation | Technique for inter-procedural memory address space optimization in gpu computing compiler |
| CN103092571B (zh) * | 2013-01-10 | 2016-06-22 | 浙江大学 | 支持多种数据类型的单指令多数据算术单元 |
| US20190196787A1 (en) * | 2017-12-21 | 2019-06-27 | Intel Corporation | Apparatus and method for right shifting packed quadwords and extracting packed doublewords |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4785393A (en) * | 1984-07-09 | 1988-11-15 | Advanced Micro Devices, Inc. | 32-Bit extended function arithmetic-logic unit on a single chip |
| EP0540150B1 (en) * | 1991-10-29 | 1999-06-02 | Advanced Micro Devices, Inc. | Arithmetic logic unit |
| US5673321A (en) * | 1995-06-29 | 1997-09-30 | Hewlett-Packard Company | Efficient selection and mixing of multiple sub-word items packed into two or more computer words |
| US6237016B1 (en) * | 1995-09-05 | 2001-05-22 | Intel Corporation | Method and apparatus for multiplying and accumulating data samples and complex coefficients |
| US5835782A (en) * | 1996-03-04 | 1998-11-10 | Intel Corporation | Packed/add and packed subtract operations |
| US5812140A (en) * | 1996-09-05 | 1998-09-22 | Adobe Systems Incorporated | Efficient gray tile storage |
| US6061783A (en) * | 1996-11-13 | 2000-05-09 | Nortel Networks Corporation | Method and apparatus for manipulation of bit fields directly in a memory source |
| US6081824A (en) * | 1998-03-05 | 2000-06-27 | Intel Corporation | Method and apparatus for fast unsigned integral division |
| JPH11272546A (ja) * | 1998-03-23 | 1999-10-08 | Nec Corp | 可変長レジスタ装置 |
| US6338135B1 (en) * | 1998-11-20 | 2002-01-08 | Arm Limited | Data processing system and method for performing an arithmetic operation on a plurality of signed data values |
-
2000
- 2000-10-04 GB GB0024311A patent/GB2367650B/en not_active Expired - Lifetime
-
2001
- 2001-08-21 RU RU2002124769/09A patent/RU2279706C2/ru not_active IP Right Cessation
- 2001-08-21 WO PCT/GB2001/003744 patent/WO2002029553A1/en not_active Ceased
- 2001-08-21 KR KR1020037004621A patent/KR100880614B1/ko not_active Expired - Lifetime
- 2001-08-21 IL IL15139501A patent/IL151395A0/xx unknown
- 2001-08-21 CN CNB01810648XA patent/CN1196998C/zh not_active Expired - Lifetime
- 2001-08-21 EP EP01960902.3A patent/EP1323031B1/en not_active Expired - Lifetime
- 2001-08-21 JP JP2002533059A patent/JP5133491B2/ja not_active Expired - Lifetime
- 2001-08-29 TW TW090121381A patent/TW548587B/zh not_active IP Right Cessation
- 2001-08-30 US US09/941,790 patent/US6999985B2/en not_active Expired - Lifetime
- 2001-09-21 MY MYPI20014440A patent/MY129332A/en unknown
-
2002
- 2002-08-21 IL IL151395A patent/IL151395A/en active IP Right Grant
Non-Patent Citations (1)
| Title |
|---|
| Data packing and unpacking scheme for high performance image processing" IBM Technical Disclosure Bulletin, IBM Corp. New York, US, vol.36, no.7, 1993.07.01, pp.309-313* |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102182299B1 (ko) * | 2019-07-24 | 2020-11-24 | 에스케이텔레콤 주식회사 | 시프트 연산 장치 및 그의 동작 방법 |
Also Published As
| Publication number | Publication date |
|---|---|
| IL151395A0 (en) | 2003-04-10 |
| JP5133491B2 (ja) | 2013-01-30 |
| EP1323031A1 (en) | 2003-07-02 |
| IL151395A (en) | 2009-09-01 |
| US20020040378A1 (en) | 2002-04-04 |
| KR20030066631A (ko) | 2003-08-09 |
| TW548587B (en) | 2003-08-21 |
| RU2002124769A (ru) | 2004-02-20 |
| GB2367650A (en) | 2002-04-10 |
| WO2002029553A1 (en) | 2002-04-11 |
| CN1432151A (zh) | 2003-07-23 |
| CN1196998C (zh) | 2005-04-13 |
| MY129332A (en) | 2007-03-30 |
| RU2279706C2 (ru) | 2006-07-10 |
| GB2367650B (en) | 2004-10-27 |
| GB0024311D0 (en) | 2000-11-15 |
| EP1323031B1 (en) | 2018-11-14 |
| JP2004511039A (ja) | 2004-04-08 |
| US6999985B2 (en) | 2006-02-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0105 | International application |
Patent event date: 20030331 Patent event code: PA01051R01D Comment text: International Patent Application |
|
| PG1501 | Laying open of application | ||
| A201 | Request for examination | ||
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 20060627 Comment text: Request for Examination of Application |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20070920 Patent event code: PE09021S01D |
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| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20080327 Patent event code: PE09021S01D |
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| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 20081030 |
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| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 20090120 Patent event code: PR07011E01D |
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| PR1002 | Payment of registration fee |
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