JP2004508607A5 - - Google Patents

Download PDF

Info

Publication number
JP2004508607A5
JP2004508607A5 JP2001560791A JP2001560791A JP2004508607A5 JP 2004508607 A5 JP2004508607 A5 JP 2004508607A5 JP 2001560791 A JP2001560791 A JP 2001560791A JP 2001560791 A JP2001560791 A JP 2001560791A JP 2004508607 A5 JP2004508607 A5 JP 2004508607A5
Authority
JP
Japan
Prior art keywords
instruction
result value
pipeline
register file
execution device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2001560791A
Other languages
English (en)
Japanese (ja)
Other versions
JP2004508607A (ja
Filing date
Publication date
Priority claimed from US09/505,986 external-priority patent/US6851044B1/en
Application filed filed Critical
Publication of JP2004508607A publication Critical patent/JP2004508607A/ja
Publication of JP2004508607A5 publication Critical patent/JP2004508607A5/ja
Withdrawn legal-status Critical Current

Links

JP2001560791A 2000-02-16 2001-01-24 例外ルーチンを有するプロセッサのレジスタライトトラフィックを減じる装置及び方法 Withdrawn JP2004508607A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/505,986 US6851044B1 (en) 2000-02-16 2000-02-16 System and method for eliminating write backs with buffer for exception processing
PCT/EP2001/000775 WO2001061469A2 (en) 2000-02-16 2001-01-24 Apparatus and method for reducing register write traffic in processors with exception routines

Publications (2)

Publication Number Publication Date
JP2004508607A JP2004508607A (ja) 2004-03-18
JP2004508607A5 true JP2004508607A5 (enExample) 2004-12-24

Family

ID=24012699

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001560791A Withdrawn JP2004508607A (ja) 2000-02-16 2001-01-24 例外ルーチンを有するプロセッサのレジスタライトトラフィックを減じる装置及び方法

Country Status (6)

Country Link
US (1) US6851044B1 (enExample)
EP (1) EP1208424B1 (enExample)
JP (1) JP2004508607A (enExample)
AT (1) ATE264520T1 (enExample)
DE (1) DE60102777T2 (enExample)
WO (1) WO2001061469A2 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060155885A1 (en) * 2002-07-19 2006-07-13 Joachim Roos Processor and a method in the processor, the processor comprising a programmable pipeline and at least one interface engine
WO2004010288A1 (en) * 2002-07-19 2004-01-29 Xelerated Ab Method and apparatus for pipelined processing of data packets
US7290153B2 (en) * 2004-11-08 2007-10-30 Via Technologies, Inc. System, method, and apparatus for reducing power consumption in a microprocessor
US8250231B2 (en) 2004-12-22 2012-08-21 Marvell International Ltd. Method for reducing buffer capacity in a pipeline processor
WO2007057831A1 (en) * 2005-11-15 2007-05-24 Nxp B.V. Data processing method and apparatus
CN104216681B (zh) * 2013-05-31 2018-02-13 华为技术有限公司 一种cpu指令处理方法和处理器

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4228497A (en) * 1977-11-17 1980-10-14 Burroughs Corporation Template micromemory structure for a pipelined microprogrammable data processing system
AU553416B2 (en) * 1984-02-24 1986-07-17 Fujitsu Limited Pipeline processing
US6370623B1 (en) 1988-12-28 2002-04-09 Philips Electronics North America Corporation Multiport register file to accommodate data of differing lengths
JPH0719222B2 (ja) * 1989-03-30 1995-03-06 日本電気株式会社 ストアバッフア
AU629007B2 (en) 1989-12-29 1992-09-24 Sun Microsystems, Inc. Apparatus for accelerating store operations in a risc computer
US5222240A (en) 1990-02-14 1993-06-22 Intel Corporation Method and apparatus for delaying writing back the results of instructions to a processor
GB2241801B (en) 1990-03-05 1994-03-16 Intel Corp Data bypass structure in a register file on a microprocessor chip to ensure data integrity
JPH04367936A (ja) * 1991-06-17 1992-12-21 Mitsubishi Electric Corp スーパースカラープロセッサ
US5471626A (en) * 1992-05-06 1995-11-28 International Business Machines Corporation Variable stage entry/exit instruction pipeline
US5898882A (en) * 1993-01-08 1999-04-27 International Business Machines Corporation Method and system for enhanced instruction dispatch in a superscalar processor system utilizing independently accessed intermediate storage
JPH08212083A (ja) 1995-02-07 1996-08-20 Oki Electric Ind Co Ltd 割り込み処理装置
JP3490191B2 (ja) 1995-06-30 2004-01-26 株式会社東芝 計算機
US20020161985A1 (en) * 1999-10-01 2002-10-31 Gearty Margaret Rose Microcomputer/floating point processor interface and method for synchronization of cpu and fpu pipelines

Similar Documents

Publication Publication Date Title
US10114651B2 (en) Gathering and scattering multiple data elements
KR101673990B1 (ko) 프로그램가능 예외 처리 지연
TWI499973B (zh) 利用暫存器擴充來管理與施用中央處理單元中之元資料的技術
US11663006B2 (en) Hardware apparatuses and methods to switch shadow stack pointers
US6665749B1 (en) Bus protocol for efficiently transferring vector data
US7590774B2 (en) Method and system for efficient context swapping
KR100309615B1 (ko) 고속프로그램가능로직컨트롤러(plc)
US8359443B2 (en) Secure memory access system and method
JP2014513340A (ja) データ要素のストライドパターンギャザーおよびデータ要素のストライドパターンスキャッタのためのシステム、装置、および方法
JP2007141246A (ja) ベクトルマスク設定技術
US3701977A (en) General purpose digital computer
US11683310B2 (en) Protecting supervisor mode information
CN113900710B (zh) 扩展存储器组件
KR20220116566A (ko) 확장 메모리 통신
JP4189402B2 (ja) キャッシュ回路
JP2004508607A5 (enExample)
TWI640864B (zh) 重疊輸入輸出記憶體管理單元映射及第二層記憶體讀取之二階命令緩衝器
US8719542B2 (en) Data transfer apparatus, data transfer method and processor
JP2007207249A (ja) ミス衝突処理状態でのキャッシュ・ヒットのための方法、システムおよびマイクロプロセッサ
US9092486B2 (en) Extensible I/O activity logs
JPH08255476A (ja) データ処理システムにおけるメモリ拡張スタック装置および方法
US6625720B1 (en) System for posting vector synchronization instructions to vector instruction queue to separate vector instructions from different application programs
WO2001061469A3 (en) Apparatus and method for reducing register write traffic in processors with exception routines
CN1357824A (zh) 数据存取控制装置、方法及其所使用的指令格式
JP2000066922A (ja) 全命令トレースデータの２次記憶装置への格納競合防止方法