ATE264520T1 - Vorrichtung und verfahren zur verminderung von datenschreibverkehr in prozessoren mit ausnahmeroutinen - Google Patents
Vorrichtung und verfahren zur verminderung von datenschreibverkehr in prozessoren mit ausnahmeroutinenInfo
- Publication number
- ATE264520T1 ATE264520T1 AT01953031T AT01953031T ATE264520T1 AT E264520 T1 ATE264520 T1 AT E264520T1 AT 01953031 T AT01953031 T AT 01953031T AT 01953031 T AT01953031 T AT 01953031T AT E264520 T1 ATE264520 T1 AT E264520T1
- Authority
- AT
- Austria
- Prior art keywords
- result
- instruction
- exception
- processors
- register file
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
- Computer And Data Communications (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/505,986 US6851044B1 (en) | 2000-02-16 | 2000-02-16 | System and method for eliminating write backs with buffer for exception processing |
PCT/EP2001/000775 WO2001061469A2 (en) | 2000-02-16 | 2001-01-24 | Apparatus and method for reducing register write traffic in processors with exception routines |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE264520T1 true ATE264520T1 (de) | 2004-04-15 |
Family
ID=24012699
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT01953031T ATE264520T1 (de) | 2000-02-16 | 2001-01-24 | Vorrichtung und verfahren zur verminderung von datenschreibverkehr in prozessoren mit ausnahmeroutinen |
Country Status (6)
Country | Link |
---|---|
US (1) | US6851044B1 (de) |
EP (1) | EP1208424B1 (de) |
JP (1) | JP2004508607A (de) |
AT (1) | ATE264520T1 (de) |
DE (1) | DE60102777T2 (de) |
WO (1) | WO2001061469A2 (de) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004010288A1 (en) * | 2002-07-19 | 2004-01-29 | Xelerated Ab | Method and apparatus for pipelined processing of data packets |
AU2003281596A1 (en) * | 2002-07-19 | 2004-02-09 | Xelerated Ab | A processor and a method in the processor, the processor comprising a programmable pipeline and at least one interface engine |
US7290153B2 (en) * | 2004-11-08 | 2007-10-30 | Via Technologies, Inc. | System, method, and apparatus for reducing power consumption in a microprocessor |
US8250231B2 (en) | 2004-12-22 | 2012-08-21 | Marvell International Ltd. | Method for reducing buffer capacity in a pipeline processor |
WO2007057831A1 (en) * | 2005-11-15 | 2007-05-24 | Nxp B.V. | Data processing method and apparatus |
CN104216681B (zh) * | 2013-05-31 | 2018-02-13 | 华为技术有限公司 | 一种cpu指令处理方法和处理器 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4228497A (en) * | 1977-11-17 | 1980-10-14 | Burroughs Corporation | Template micromemory structure for a pipelined microprogrammable data processing system |
AU553416B2 (en) * | 1984-02-24 | 1986-07-17 | Fujitsu Limited | Pipeline processing |
US6370623B1 (en) | 1988-12-28 | 2002-04-09 | Philips Electronics North America Corporation | Multiport register file to accommodate data of differing lengths |
JPH0719222B2 (ja) * | 1989-03-30 | 1995-03-06 | 日本電気株式会社 | ストアバッフア |
AU629007B2 (en) | 1989-12-29 | 1992-09-24 | Sun Microsystems, Inc. | Apparatus for accelerating store operations in a risc computer |
US5222240A (en) | 1990-02-14 | 1993-06-22 | Intel Corporation | Method and apparatus for delaying writing back the results of instructions to a processor |
GB2241801B (en) | 1990-03-05 | 1994-03-16 | Intel Corp | Data bypass structure in a register file on a microprocessor chip to ensure data integrity |
JPH04367936A (ja) * | 1991-06-17 | 1992-12-21 | Mitsubishi Electric Corp | スーパースカラープロセッサ |
US5471626A (en) * | 1992-05-06 | 1995-11-28 | International Business Machines Corporation | Variable stage entry/exit instruction pipeline |
US5898882A (en) * | 1993-01-08 | 1999-04-27 | International Business Machines Corporation | Method and system for enhanced instruction dispatch in a superscalar processor system utilizing independently accessed intermediate storage |
JPH08212083A (ja) | 1995-02-07 | 1996-08-20 | Oki Electric Ind Co Ltd | 割り込み処理装置 |
JP3490191B2 (ja) | 1995-06-30 | 2004-01-26 | 株式会社東芝 | 計算機 |
US20020161985A1 (en) * | 1999-10-01 | 2002-10-31 | Gearty Margaret Rose | Microcomputer/floating point processor interface and method for synchronization of cpu and fpu pipelines |
-
2000
- 2000-02-16 US US09/505,986 patent/US6851044B1/en not_active Expired - Lifetime
-
2001
- 2001-01-24 JP JP2001560791A patent/JP2004508607A/ja not_active Withdrawn
- 2001-01-24 WO PCT/EP2001/000775 patent/WO2001061469A2/en active IP Right Grant
- 2001-01-24 EP EP01953031A patent/EP1208424B1/de not_active Expired - Lifetime
- 2001-01-24 AT AT01953031T patent/ATE264520T1/de not_active IP Right Cessation
- 2001-01-24 DE DE2001602777 patent/DE60102777T2/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2004508607A (ja) | 2004-03-18 |
WO2001061469A2 (en) | 2001-08-23 |
DE60102777T2 (de) | 2009-10-08 |
EP1208424A2 (de) | 2002-05-29 |
US6851044B1 (en) | 2005-02-01 |
EP1208424B1 (de) | 2004-04-14 |
WO2001061469A3 (en) | 2002-02-21 |
DE60102777D1 (de) | 2004-05-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |