JP2004336192A - Semiconductor circuit and picture receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor circuit and a picture receiver which stably decides an input frequency. <P>SOLUTION: The semiconductor circuit 10 divides a frequency band into first and second frequency bands by a given reference frequency and decides which frequency band the frequency band covering an input clock signal belongs to. It comprises an input clock frequency decision circuit which decides that the input clock signal changes from the first frequency band to the second frequency band or changes vice versa when the input clock signal CKIN is faster than a second reference frequency or slower than a first reference frequency, respectively, and outputs an input clock frequency decision signal. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor circuit. In particular, the present invention relates to a semiconductor circuit and an image receiving apparatus for determining which frequency band a frequency band to which an input clock signal input to a PLL (Phase Locked Loop) belongs.
[0002]
[Background Art]
When transmitting an image signal by the DVI (Digital Visual Interface) method or the like, the transmission frequency of the image signal differs depending on the size of the image to be transmitted and the refresh rate. The transmission clock frequency at this time may take a frequency band from 25 MHz to 175 MHz, for example.
[0003]
In such a case, in a PLL (Phase Locked Loop) on the receiving side of the image signal, it is necessary to perform processing in accordance with a frequency from 25 MHz to 175 MHz. In many cases, a configuration that switches the setting according to the clock frequency to be received is provided.
[0004]
[Patent Document 1]
JP-A-2000-236260
[Patent Document 2]
JP-A-2000-324135
[Patent Document 3]
JP-A-2000-293327
[0005]
[Problems to be solved by the invention]
However, conventionally, since the input frequency was determined to be the high-speed mode or the low-speed mode at a single level, for example, when the input frequency was near the determination level, the input frequency fluctuated even if it was minute. If there is, there is a risk that the judgment output of the frequency judgment circuit will not be stable and malfunction will occur.
[0006]
The present invention has been made in view of the above technical problems, and an object of the present invention is to provide a semiconductor circuit and an image receiving device capable of stably determining an input frequency.
[0007]
[Means for Solving the Problems]
(1) The present invention divides a frequency band into a first frequency band and a second frequency band which is a frequency band faster than the first frequency band according to a given reference frequency. A semiconductor circuit for determining which frequency band belongs,
Determining that the input clock signal has changed from the first frequency band to the second frequency band when the input clock signal is faster than a second reference frequency that is faster than the given frequency;
Determining that the input clock signal has changed from the second frequency band to the first frequency band when the input clock signal is lower than a first reference frequency that is lower than a given frequency;
An input clock frequency determination circuit that outputs an input clock frequency determination signal is included.
[0008]
Here, it is determined whether or not the input clock signal has become faster than a second reference frequency, which is a frequency higher than the given frequency, or whether the input clock signal is later than the first reference frequency, which is a frequency lower than the given frequency. The determination as to whether or not the frequency has become true may be made, for example, using the frequency itself or using a value obtained by converting the frequency into a voltage or a current.
[0009]
Here, the input clock signal may be, for example, an input clock signal input to a PLL (Phase Locked Loop).
[0010]
According to the present invention, it is possible to provide a semiconductor circuit that can obtain a stable input frequency because a hysteresis characteristic can be obtained in determining whether an input clock signal belongs to a first frequency band or a second frequency band. Can be done.
[0011]
(2) The semiconductor circuit of the present invention
The input clock frequency determination circuit,
A first reference value is output if the input clock signal currently belongs to the first frequency band, and a second reference value is output if the input clock signal currently belongs to the second frequency band. A reference value output circuit that switches and outputs a reference value according to the frequency band to which the input clock signal currently belongs,
A circuit for comparing the reference value output from the reference value output circuit with a voltage value or a current value obtained based on the input clock signal or the input clock signal, and generating an input clock frequency determination signal based on the comparison result. Features.
[0012]
(3) The semiconductor circuit of the present invention comprises:
The input clock frequency determination circuit,
A reference voltage output circuit for outputting a reference voltage,
A frequency-voltage conversion circuit that generates and outputs an input clock conversion voltage based on the frequency of the input clock signal,
A circuit that compares the input clock converted voltage output from the frequency voltage conversion circuit with the reference voltage output from the reference voltage output circuit and generates an input clock frequency determination signal based on the comparison result;
The reference voltage output circuit,
A first reference voltage value is output if the input clock signal currently belongs to the first frequency band, and a second reference voltage value if the input clock signal currently belongs to the second frequency band. , The reference voltage is switched and output according to the frequency band to which the input clock signal currently belongs.
[0013]
(4) The semiconductor circuit of the present invention
A voltage-controlled oscillation circuit that receives the input clock frequency determination signal output from the frequency determination circuit and switches a conversion characteristic between an input voltage and an oscillation frequency.
[0014]
(5) The semiconductor circuit of the present invention comprises:
A PLL circuit that generates an output signal using the input clock frequency determination signal output from the frequency determination circuit.
[0015]
(6) The semiconductor circuit of the present invention comprises:
The PLL circuit comprises:
A voltage-controlled oscillation circuit that receives the input clock frequency determination signal output from the frequency determination circuit and switches a conversion characteristic between an input voltage and an oscillation frequency.
[0016]
(7) The semiconductor circuit of the present invention comprises:
The PLL circuit comprises:
A charge pump circuit that generates and outputs a potential based on a signal output from the phase detection circuit with characteristics according to the input clock frequency determination signal.
[0017]
(8) The semiconductor circuit of the present invention comprises:
The PLL circuit comprises:
It further includes a loop filter circuit that filters the potential output from the charge pump circuit according to the input clock frequency determination signal and outputs the filtered potential.
[0018]
(9) The semiconductor circuit of the present invention comprises:
The input clock signal is a reference clock signal for receiving an image signal.
[0019]
(10) The image signal receiving apparatus of the present invention
It is characterized by including the semiconductor circuit described in any of the above.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.
[0021]
FIG. 1 is an example of an input frequency determination circuit (semiconductor circuit) of the present embodiment. FIG. 2 is a diagram showing input / output characteristics of the input frequency determination circuit (semiconductor circuit) of the present embodiment.
[0022]
The input frequency determination circuit (semiconductor circuit) 10 according to the present embodiment changes a frequency band into a first frequency band and a second frequency band (first frequency band <second frequency band) based on a given reference frequency. This is a semiconductor circuit that determines which frequency band an input clock signal that is divided and input to a PLL (Phase Locked Loop) belongs to.
[0023]
The input frequency determination circuit (semiconductor circuit) 10 determines that the input clock signal CKIN has become faster than a given second reference frequency (the second reference frequency is set to a frequency higher than the first reference frequency). It is determined that the input clock signal CKIN has changed from the first frequency band to the second frequency band, and when the input clock signal CKIN becomes slower than the first reference frequency, the input clock signal CKIN becomes the second frequency band. When it is determined that the frequency band has changed to the first frequency band, an input clock frequency determination signal 62 is output.
[0024]
The reference value output circuit (reference voltage output circuit 40) outputs the first reference voltage value when the input clock signal currently belongs to the first frequency band, and outputs the first reference voltage value when the input clock signal currently belongs to the second frequency band. When the input clock signal belongs to the frequency band, the reference voltage is switched according to the frequency band to which the input clock signal currently belongs so as to output the second reference voltage value.
[0025]
The input clock frequency determination signal generation circuit 50 generates a reference value (voltage V2 in FIG. 1) output from the reference value output circuit (reference voltage output circuit 40) and an input clock signal or a voltage value or current obtained based on the input clock signal. The input clock frequency determination signal 62 is generated based on the comparison result with the value (the voltage V1 in FIG. 1).
[0026]
The reference voltage output circuit 40 outputs a reference voltage. The frequency-voltage conversion circuit 30 generates and outputs an input clock conversion voltage according to the frequency of the input clock signal.
[0027]
Also, the input clock frequency determination signal generation circuit 50 compares the input clock conversion voltage V1 output from the frequency voltage conversion circuit 30 with the reference voltage V2 output from the reference voltage output circuit 10, and based on the comparison result. The input clock frequency determination signal 62 may be generated.
[0028]
Based on the input clock frequency determination signal 62, the reference voltage output circuit 40 changes the output reference voltage to a first reference voltage value VREF1 (a voltage value set when the input clock belongs to a first frequency band) or It may be configured to switch to any of the second reference voltage values VREF2 (voltage values set when the input clock belongs to the second frequency band). Here, the first reference voltage VREF1 <the second reference voltage VREF2.
[0029]
Here, the reference voltage output circuit 40 can be configured to include a reference voltage generation circuit 42 and a switch circuit 44. The reference voltage generation circuit 42 generates a first reference voltage value VREF1 and a second reference voltage value VREF2 and outputs them to the switch circuit 44. The switch circuit 44 switches the output voltage to the first reference voltage value VREF1 or the second reference voltage value VREF2 based on the input clock frequency determination signal 62.
[0030]
The frequency divider 20 divides the input clock signal and outputs a frequency-divided clock 1 (N-CK1) and a frequency-divided clock 2 (N-CK2). Then, the frequency-voltage conversion circuit 30 may generate the input clock conversion voltage V1 based on the divided clock 1 (N-CK1) and the divided clock 2 (N-CK2).
[0031]
Further, the input clock frequency determination signal generation circuit 50 may be configured to include the comparator 52 and the D flip-flop 54. The comparator 52 compares the input clock conversion voltage V1 with the reference voltage V2 and outputs a comparison signal COMP. The D flip-flop 54 may be configured to output the input clock frequency determination signal 62 based on the comparison signal COMP and the frequency-divided clock 2 (N-CK2).
[0032]
With such a configuration, when the input clock signal CKIN is in the first frequency band (low-speed mode), the input frequency determination circuit (semiconductor circuit) 10 of the present embodiment When the input clock signal CKIN changes from a first frequency band (low-speed mode) to a second frequency band (high-speed mode) when the frequency becomes faster than a given second reference frequency (FDET-L in FIG. 2). Therefore, the level of the potential of the input fraction determination signal changes along a → b → c in FIG.
[0033]
When the input clock signal CKIN is in the second frequency band (high-speed mode), the input clock signal CKIN becomes slower than a given first reference frequency (FDET-H in FIG. 2). It is determined that the clock signal CKIN has changed from the second frequency band (high-speed mode) to the first frequency band (low-speed mode), and the potential of the input fraction determination signal is determined along c → d → a in FIG. The level changes.
[0034]
That is, when the input clock signal is currently at low speed, the potential level of the input fraction determination signal changes along a → b → c in FIG. 2 and when the input clock signal CKIN is currently at high speed. Provides a hysteresis characteristic in which the level of the potential of the input fraction determination signal changes along c → d → a in FIG.
[0035]
3 to 6 are timing charts showing operation timings of the input frequency determination circuit of FIG.
[0036]
FIG. 3 is a timing chart showing the operation timing of the input frequency determination circuit when the input clock signal CKIN having a frequency lower than the first reference frequency is input.
[0037]
As shown in FIG. 3, the input clock signal CKIN (110) changes in potential level at a frequency lower than the reference frequency.
[0038]
The charging of the capacitor C1 of the frequency-voltage conversion circuit of FIG. 1 starts from the fall of the frequency-divided clock 1 (N-CK1) at time t1, and the potential V1 rises like a ramp. Then, when the frequency-divided clock 1 (N-CK1) rises at time t3, charging of the capacitor C1 is stopped, and the rise of the potential V1 is stopped.
[0039]
Further, the rising of the frequency-divided clock 2 (N-CK2) at time t4 discharges the capacitor C1, and the potential V1 becomes L level.
[0040]
During this time, the comparator 52 in FIG. 1 compares the input clock conversion voltage V1 (140) with the first reference voltage VREF1, and when the input clock conversion voltage V1 (140) is higher than the first reference voltage VREF1, the comparison signal COMP (150). ) Is set to L level, and when the input clock conversion voltage V1 (140) is equal to or lower than the first reference voltage VREF1, the comparison signal COMP (150) is set to H level. Here, the first reference voltage VREF1 is a voltage value set corresponding to the first reference frequency.
[0041]
Since the input clock conversion voltage V1 (140) ≦ the first reference voltage VREF1 from time t1 to time t2, the comparison signal COMP (150) becomes H level, and the input clock conversion voltage from time t2 to time t4. Since V1 (140)> first reference voltage VREF1, the comparison signal COMP (150) becomes L level.
[0042]
1 outputs the input clock frequency determination signal FB (62) based on the comparison signal COMP (150) and the divided clock 2 (N-CK2) 130.
[0043]
In FIG. 3, the value held in the D flip-flop 54 at the timing when the divided clock 2 (N-CK2) 130 rises is L level (for example, at the timing t4 when the divided clock 2 (N-CK2) 130 rises), the comparison signal Since COMP is at the L level (see 152), the input clock frequency determination signal FB (62) is at the L level.
[0044]
FIG. 4 is a timing chart showing the operation timing of the input frequency determination circuit when the input clock signal CKIN changes from a frequency lower than the reference frequency to a frequency higher than the reference frequency.
[0045]
As shown in FIG. 4, the input clock signal CKIN (110) changes in potential level at a frequency higher than the reference frequency.
[0046]
The charging of the capacitor C1 of the frequency-voltage conversion circuit of FIG. 1 starts from the fall of the frequency-divided clock 1 (N-CK1) at time t1, and the potential V1 rises like a ramp. Then, the rising of the frequency-divided clock 1 (N-CK1) at time t2 stops the charging of the capacitor C1, and stops the rise of the potential V1.
[0047]
Further, the rising of the frequency-divided clock 2 (N-CK2) at time t3 discharges the capacitor C1, and the potential V1 becomes L level.
[0048]
During this time, the comparator 52 in FIG. 1 compares the input clock conversion voltage V1 (140) with the first reference voltage VREF1, and when the input clock conversion voltage V1 (140) is higher than the first reference voltage VREF1, the comparison signal COMP (150). ) Is set to L level, and when the input clock conversion voltage V1 (140) is equal to or lower than the first reference voltage VREF1, the comparison signal COMP (150) is set to H level. Here, the first reference voltage VREF1 is a voltage value set corresponding to the first reference frequency.
[0049]
From time t1 to time t3, the input clock conversion voltage V1 (140) ≦ the first reference voltage VREF1, so that the comparison signal COMP (150) becomes H level.
[0050]
1 outputs the input clock frequency determination signal FB (62) based on the comparison signal COMP (150) and the divided clock 2 (N-CK2) 130.
[0051]
In FIG. 4, the value held in the D flip-flop 54 at the timing when the divided clock 2 (N-CK2) 130 rises is at the H level (for example, at the timing t3 when the divided clock 2 (N-CK2) 130 rises), the comparison signal is output. Since COMP is at the H level (see 154), the input clock frequency determination signal FB (62) is at the H level.
[0052]
FIG. 5 is a timing chart showing the operation timing of the input frequency determination circuit when an input clock signal CKIN having a frequency higher than the reference frequency is input.
[0053]
As shown in FIG. 5, the input clock signal CKIN (110) changes in potential level at a frequency lower than the reference frequency.
[0054]
The charging of the capacitor C1 of the frequency-voltage conversion circuit of FIG. 1 starts from the fall of the frequency-divided clock 1 (N-CK1) at time t1, and the potential V1 rises like a ramp. Then, the rising of the frequency-divided clock 1 (N-CK1) at time t2 stops the charging of the capacitor C1, and stops the rise of the potential V1.
[0055]
Further, the rising of the frequency-divided clock 2 (N-CK2) at time t3 discharges the capacitor C1, and the potential V1 becomes L level.
[0056]
During this time, the comparator 52 of FIG. 1 compares the input clock conversion voltage V1 (140) with the second reference voltage VREF2, and when the input clock conversion voltage V1 (140) is higher than the second reference voltage VREF2, the comparison signal COMP (150). ) Is set to L level, and when the input clock conversion voltage V1 (140) is equal to or lower than the second reference voltage VREF2, the comparison signal COMP (150) is set to H level. Here, the second reference voltage VREF2 is a voltage value set corresponding to the second reference frequency.
[0057]
From time t1 to time t3, the input clock conversion voltage V1 (140) ≦ the second reference voltage VREF2, so that the comparison signal COMP (150) is at the H level.
[0058]
1 outputs the input clock frequency determination signal FB (62) based on the comparison signal COMP (150) and the divided clock 2 (N-CK2) 130.
[0059]
In FIG. 5, the value held in the D flip-flop 54 at the timing when the divided clock 2 (N-CK2) 130 rises is H level (for example, at the timing t3 when the divided clock 2 (N-CK2) 130 rises), the comparison signal is output. Since COMP is at the H level (see 154), the input clock frequency determination signal FB (62) is at the H level.
[0060]
FIG. 6 is a timing chart showing the operation timing of the input frequency determination circuit when the input clock signal CKIN changes from a frequency higher than the reference frequency to a frequency lower than the reference frequency.
[0061]
As shown in FIG. 6, the potential level of the input clock signal CKIN (110) changes at a frequency higher than the reference frequency.
[0062]
The charging of the capacitor C1 of the frequency-voltage conversion circuit of FIG. 1 starts from the fall of the frequency-divided clock 1 (N-CK1) at time t1, and the potential V1 rises like a ramp. Then, when the frequency-divided clock 1 (N-CK1) rises at time t3, charging of the capacitor C1 is stopped, and the rise of the potential V1 is stopped.
[0063]
Further, the rise of the frequency-divided clock 2 (N-CK2) at time t4 discharges the capacitor C1, and the potential V1 becomes L level.
[0064]
During this time, the comparator 52 of FIG. 1 compares the input clock conversion voltage V1 (140) with the second reference voltage VREF2, and when the input clock conversion voltage V1 (140) is higher than the second reference voltage VREF2, the comparison signal COMP (150). ) Is set to L level, and when the input clock conversion voltage V1 (140) is equal to or lower than the second reference voltage VREF2, the comparison signal COMP (150) is set to H level. Here, the second reference voltage VREF2 is a voltage value set corresponding to the second reference frequency.
[0065]
Since the input clock conversion voltage V1 (140) ≦ the second reference voltage VREF2 between the time t1 and the time t2, the comparison signal COMP (150) becomes H level, and the input clock conversion voltage between the time t2 and the time t4. Since V1 (140)> the second reference voltage VREF2, the comparison signal COMP (150) becomes L level.
[0066]
1 outputs the input clock frequency determination signal FB (62) based on the comparison signal COMP (150) and the divided clock 2 (N-CK2) 130.
[0067]
In FIG. 6, the value held in the D flip-flop 54 at the timing when the divided clock 2 (N-CK2) 130 rises is L level (for example, at the timing t4 when the divided clock 2 (N-CK2) 130 rises), the comparison signal is output. Since COMP is at the L level (see 156), the input clock frequency determination signal FB (62) is at the L level.
[0068]
Further, the semiconductor circuit of the present embodiment includes a voltage controlled oscillation circuit (VCO) that receives an input clock frequency determination signal output from the frequency determination circuit and switches a conversion characteristic (generation pattern) between an input voltage and an oscillation frequency. Is also good.
[0069]
FIGS. 7A and 7B are block diagrams showing an example of the voltage controlled oscillator (VCO) according to the present embodiment. FIGS. 8A and 8B show conversion characteristics from the input voltage to the oscillation frequency of the voltage controlled oscillator (VCO). FIG. 9 is a diagram for explaining (generation pattern).
[0070]
The voltage-controlled oscillation circuit (VCO) 260 receives the input clock frequency determination signal HS output from the frequency determination circuit, switches the conversion characteristic (generation pattern) between the input voltage and the oscillation frequency, and performs oscillation. I can do it.
[0071]
The voltage controlled oscillation circuit (VCO) 260 may be configured to include a voltage conversion circuit 262 and a VCO oscillation circuit 264 as shown in FIG.
[0072]
The voltage conversion circuit 262 converts the bias voltage VC into a bias voltage PB using a conversion pattern selected based on the input clock frequency signal HS.
[0073]
Here, 320 in FIG. 8A is a conversion curve showing a conversion characteristic from the bias voltage VC to the bias voltage PB in the low speed mode, and 310 is a conversion curve from the bias voltage VC to the bias voltage PB in the high speed mode. 7 is a conversion curve showing the conversion characteristics of the above.
[0074]
When the input frequency determination signal HS is at the H level, the voltage conversion circuit 262 of FIG. 7 converts the input bias voltage VC into the bias voltage PB according to the conversion curve 310 of FIG. When the input frequency determination signal HS is at the L level, the input bias voltage VC is converted into the bias voltage PB according to the conversion curve 320 of FIG.
[0075]
Reference numeral 330 in FIG. 8B denotes a conversion curve indicating a conversion characteristic when converting the bias voltage PB into the output clock f0. The VCO oscillation circuit 264 of FIG. 7 converts the input bias voltage PB into an output clock of frequency f0 according to the conversion curve 330 of 8 (B), and outputs the output clock.
[0076]
FIG. 9 is a block diagram illustrating an example of the semiconductor circuit according to the second embodiment.
[0077]
The semiconductor circuit 200 according to the second embodiment includes, for example, an input frequency determination circuit 220, a phase detection circuit 230, a charge pump circuit 240, a loop filter circuit 250, a voltage control oscillation circuit 260, and a frequency division circuit 270. The input frequency determination circuit 220, the phase detection circuit 230, the charge pump circuit 240, the loop filter circuit 250, the voltage control oscillation circuit 260, and the frequency dividing circuit 270 constitute a PLL (Phase Locked Loop) circuit.
[0078]
The input clock signal CKIN (210) of a given frequency is externally input to the semiconductor circuit 200 of the second embodiment. This input clock signal CKIN (210) is supplied to the input frequency determination circuit 220 and the phase detection circuit 230.
[0079]
The input frequency determination circuit 220 generates a control signal HS indicating whether the input clock signal CKIN (210) of a given frequency belongs to two frequency bands (H speed mode or L speed mode) divided by the reference frequency. This is the output circuit. When the frequency of the input clock signal CKIN (210) belongs to a band lower than the reference frequency, the input frequency determination circuit 220 outputs the L-level control signal HS. If the signal belongs to a higher band, the control signal HS at the H level is issued. Here, the input frequency determination circuit 220 can be constituted by, for example, the circuit described with reference to FIG.
[0080]
Further, the voltage controlled oscillation circuit 260 can be constituted by, for example, the circuit described with reference to FIG.
[0081]
FIG. 10 is a diagram for describing an example of the image signal receiving device according to the present embodiment.
[0082]
The image signal receiving device 410 of the present embodiment is, for example, a DVI (Digital Visual Interface) receiver built in the TFT panel 440 or the like. DVI (Digital Visual Interface) is a digital transmission interface standard for digital displays. As a data format, a TMDS (Transition Mimicified Differential Signaling) method is adopted.
[0083]
Image signal receiving apparatus 410 of the present embodiment includes a PLL circuit 420. The PLL circuit 420 has, for example, the configuration described in the semiconductor circuit 200 in FIG. 9 and includes the input frequency determination circuit described in FIG.
[0084]
The TFT panel 440 receives the image signal 432 (for example, RGB or YUV data) and the input clock signal CKIN 434 from, for example, the PC 430 or the like.
[0085]
Image signal receiving apparatus 410 of the present embodiment receives input clock signal CKIN 434, and the frequency of input clock signal CKIN 434 belongs to one of two frequency bands (high-speed mode and low-speed mode) divided by the reference frequency. Then, the conversion operation such as VCO is set based on the result of the judgment.
[0086]
The present invention is not limited to the present embodiment, and various modifications can be made within the scope of the present invention.
[Brief description of the drawings]
FIG. 1 is an example of an input frequency determination circuit (semiconductor circuit) of the present embodiment.
FIG. 2 is a diagram showing input / output characteristics of an input frequency determination circuit (semiconductor circuit) of the present embodiment.
FIG. 3 is a timing chart illustrating operation timings of the input frequency determination circuit according to the present embodiment.
FIG. 4 is a timing chart showing the operation timing of the input frequency determination circuit of the present embodiment.
FIG. 5 is a timing chart showing the operation timing of the input frequency determination circuit of the present embodiment.
FIG. 6 is a timing chart showing operation timings of the input frequency determination circuit of the present embodiment.
FIG. 7 is a block diagram illustrating an example of a voltage controlled oscillator (VCO) according to the present embodiment.
FIGS. 8A and 8B are diagrams for explaining a conversion characteristic (generation pattern) from an input voltage to an oscillation frequency of a voltage controlled oscillator (VCO).
FIG. 9 is a block diagram illustrating an example of a semiconductor circuit according to a second embodiment;
FIG. 10 is a diagram for describing an example of an image signal receiving device according to the present embodiment.
[Explanation of symbols]
Reference Signs List 10 input frequency judgment circuit, 20 frequency dividing circuit, 30 frequency voltage conversion circuit, 40 reference voltage output circuit, 42 reference voltage generation circuit, 44 switch circuit, 50 input clock frequency judgment signal generation circuit, 52 comparator, 54 D flip-flop circuit , 62 input clock frequency determination signal, 200 semiconductor circuit, 220 input frequency determination circuit, 230 phase detection circuit, 240 charge pump circuit, 250 loop filter circuit, 260 voltage controlled oscillation circuit, 270 frequency divider circuit, 410 image signal receiving device, 420 PLL circuit, 440 TFT panel

Claims (10)

The frequency band is divided into a first frequency band and a second frequency band which is a frequency band faster than the first frequency band according to a given reference frequency, and the frequency band to which the input clock signal to be inputted belongs is A semiconductor circuit for determining whether
Determining that the input clock signal has changed from the first frequency band to the second frequency band when the input clock signal is faster than a second reference frequency that is faster than the given frequency;
Determining that the input clock signal has changed from the second frequency band to the first frequency band when the input clock signal is lower than a first reference frequency that is lower than a given frequency;
A semiconductor circuit including an input clock frequency determination circuit that outputs an input clock frequency determination signal. In claim 1,
The input clock frequency determination circuit,
A first reference value is output if the input clock signal currently belongs to the first frequency band, and a second reference value is output if the input clock signal currently belongs to the second frequency band. A reference value output circuit that switches and outputs a reference value according to the frequency band to which the input clock signal currently belongs,
A circuit for comparing the reference value output from the reference value output circuit with a voltage value or a current value obtained based on the input clock signal or the input clock signal, and generating an input clock frequency determination signal based on the comparison result. Characteristic semiconductor circuit. In claim 1,
The input clock frequency determination circuit,
A reference voltage output circuit for outputting a reference voltage,
A frequency-voltage conversion circuit that generates and outputs an input clock conversion voltage based on the frequency of the input clock signal,
A circuit that compares the input clock converted voltage output from the frequency voltage conversion circuit with the reference voltage output from the reference voltage output circuit and generates an input clock frequency determination signal based on the comparison result;
The reference voltage output circuit,
A first reference voltage value is output if the input clock signal currently belongs to the first frequency band, and a second reference voltage value if the input clock signal currently belongs to the second frequency band. A semiconductor circuit characterized in that a reference voltage is switched and output according to a frequency band to which an input clock signal currently belongs so as to output the reference clock. In any one of claims 1 to 3,
A semiconductor circuit, comprising: a voltage-controlled oscillation circuit that receives the input clock frequency determination signal output from the frequency determination circuit and switches a conversion characteristic between an input voltage and an oscillation frequency. In any one of claims 1 to 4,
A semiconductor circuit, comprising: a PLL circuit that generates an output signal using the input clock frequency determination signal output from the frequency determination circuit. In claim 5,
The PLL circuit comprises:
A semiconductor circuit, comprising: a voltage-controlled oscillation circuit that receives the input clock frequency determination signal output from the frequency determination circuit and switches a conversion characteristic between an input voltage and an oscillation frequency. In any one of claims 5 to 7,
The PLL circuit comprises:
A semiconductor circuit comprising: a charge pump circuit that generates and outputs a potential based on a signal output from a phase detection circuit with characteristics according to the input clock frequency determination signal. In any one of claims 5 to 7,
The PLL circuit comprises:
A semiconductor circuit, comprising: a loop filter circuit that filters a potential output from a charge pump circuit according to the input clock frequency determination signal and outputs the filtered potential. In any one of claims 1 to 8,
2. The semiconductor circuit according to claim 1, wherein the input clock signal is a reference clock signal for receiving an image signal. An image signal receiving apparatus comprising the semiconductor circuit according to claim 1.

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