JP2000078433A - Pll circuit, ad conversion circuit using the same and video signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a highly accurate PLL capable of variably adjusting the phase relation between a dot clock signal and an analog video signal without providing an expensive IC by outputting the dot clock signal by varying frequency according to a DC value of a loop filter output to output a voltage difference signal by filtering it and converting it into a DC signal. SOLUTION: Frequency information of vertical and horizontal synchronizing signals of various video standards are stored in a microcomputer 120, the standard is judged and held by collating the frequency information of the video standard and the frequency information of the vertical and horizontal synchronizing signal to be inputted. And information on frequency division from the microcomputer 120 is stored in a frequency divider pulse generation circuit 110. On the other hand, the dot clock signal generated by a voltage control oscillator 119 is supplied to a clock input terminal of a counter like a counter of the frequency divider pulse generating circuit 110, the frequency is divided 1/n by the counter and an H pulse signal formed by dividing the frequency by 1/n is outputted from the frequency divider pulse generating circuit 110.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (Phased Locked Loop) for generating a dot clock signal for sampling a video signal from a personal computer or the like.
The present invention relates to a circuit, an AD conversion circuit that converts a video signal into a digital signal using the circuit, and a video signal processing device using the same. For example, an input video signal is temporarily converted into a digital signal, and signal processing such as pixel conversion such as enlargement or reduction of video information is performed, and the signal is changed to an optimum size on a display panel such as a liquid crystal display and used for signal processing for display. Is preferred.

[0002]

2. Description of the Related Art Generally, in a personal computer, an R / G / B video signal is processed by a digital signal inside the personal computer, and the digital signal is finally converted into an analog signal by a DA converter. Is done. When such a personal computer is connected to an externally connected device such as a liquid crystal display, it is connected by an analog signal. On the liquid crystal display side, it is necessary to convert this analog video signal into a digital video signal by an AD converter. is there.

When performing AD conversion, frequency characteristics and S
In order to obtain a digital video signal while maintaining high-definition analog video signal information without deteriorating the N ratio, first, a clock signal having the same frequency as a pixel, which is the minimum unit constituting the video signal, Usually this is called a dot clock signal, but the analog video signal is sampled using this dot clock signal, and when sampling, the phase of the dot clock signal is adjusted optimally to the phase of the analog video signal. Must. The reason for this is that, as described in, for example, Japanese Patent Application Laid-Open No. 7-295533, image quality is significantly degraded particularly when performing dither processing in which the data level changes for each pixel or when displaying a high-definition image. It is stated that it will appear. Also, since this dot clock signal is generally not output from a personal computer in general, in order to optimally adjust the phase relationship between the dot clock signal and the video signal on the display side, the following is usually performed. The method described in the above is adopted.

[0004] That is, a dot clock signal in which a horizontal synchronizing signal output from a personal computer is locked to this horizontal synchronizing signal using a multiplier such as a PLL is generated,
Further, the dot clock signal is delayed by the delay circuit to adjust the phase relationship optimally. The phase relationship between the analog video signal and the horizontal synchronizing signal is slightly shifted due to variations in individual components in the personal computer, even in the case of personal computers of the same model and the same model. Not managed. For this reason, in a display panel such as a liquid crystal display that realizes high image quality as described above, the dot clock signal is delayed by, for example, a minute time unit of 1 nanosecond within one cycle of the dot clock signal. It is provided with a delay circuit IC, etc., which can be used to visually confirm the image quality on the display device panel screen via an operation button, a remote control, or the like, and to provide a high-quality image without deteriorating the image quality. The delay amount is variably adjusted to match the phases of the dot clock signal and the analog video signal.

[0005]

In the above-mentioned prior art, in order to convert a high-definition analog video signal into a digital signal while maintaining the information of the high-definition analog video signal without deteriorating the frequency characteristics and the S / N ratio, it is necessary to use a dot. There is a problem that a very expensive delay circuit IC for shifting the phase of the clock signal with respect to the analog video signal by a minute time unit must be provided.

It is an object of the present invention to provide a high-precision PLL capable of variably adjusting the phase relationship between a dot clock signal and an analog video signal without providing this expensive IC, and
It is an object of the present invention to provide an AD conversion circuit for converting an image into a high-quality digital video signal having L, a video signal processing device having the AD conversion device, and a display device having the video signal processing device.

[0007]

According to a first aspect of the present invention, there is provided a PLL circuit for outputting a dot clock signal for sampling an input analog video signal. The frequency fs of the clock signal satisfies the relationship of fs = fH × n (where n is a positive integer) when the frequency of the horizontal synchronization signal of the input video signal is fH, and the dot clock signal is expressed by (1/1 / n) Frequency dividing pulse generating means for generating an H pulse signal which is a frequency divided pulse signal, and the value of n in the frequency dividing value (1 / n) of the frequency dividing pulse generating means is varied with periodicity. Frequency dividing value varying means, and phase comparing means for detecting a phase difference between the H pulse signal output from the frequency dividing pulse generating means and the horizontal synchronizing signal, converting the phase difference information into a voltage difference signal or the like, and outputting the same. When, A loop filter for smoothing the voltage difference signal output from the phase comparison means and converting and outputting the DC signal, and a voltage controlled oscillator for varying the frequency according to the DC value of the output of the loop filter and outputting the dot clock signal. It is characterized by having.

A second configuration of the PLL circuit according to the present invention is a PLL circuit for outputting a dot clock signal for sampling an input analog video signal, wherein the frequency fs of the dot clock signal is When the frequency of the horizontal synchronization signal is fH, fs = fH ×
n frequency pulse generating means for generating and outputting an H pulse signal which is a pulse signal obtained by frequency-dividing the dot clock signal by (1 / n) which satisfies a relationship of n (where n is a positive integer value); H-pulse delay means for receiving an input signal and outputting an H-pulse signal delayed from a logic circuit such as a flip-flop based on the dot clock signal; H-pulse signal output from the frequency-divided pulse generation means or output from the H-pulse delay means Selection switching means for receiving a delayed H pulse signal as input, selecting and outputting only one signal from the input, and selection for performing selection control with periodicity in the selection control method in the selection switching means Switching control means for detecting a phase difference between the H pulse signal from the output of the selection switching means and the horizontal synchronizing signal, converting the phase difference information into a voltage difference signal or the like, and outputting the voltage difference signal or the like Comparing means, a loop filter for smoothing the voltage difference signal output from the phase comparing means and converting and outputting the signal to a DC signal, and a voltage for varying the frequency according to the DC value of the output of the loop filter and outputting the dot clock signal And a control oscillator.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments for carrying out the present invention will be described below in detail with reference to the drawings. FIG.
FIG. 2 is a block diagram showing an embodiment according to the present invention. FIG.
, 101 is a personal computer, 102 is an R / G / B video input terminal, 103 is a vertical synchronization signal input terminal, 104 is a horizontal synchronization signal input terminal, 105 is an AD converter, 106 is a video signal processing circuit, and 107 is DA. The conversion device 108 is a PLL circuit. 109 is a frequency discriminating circuit, 110 is a divided pulse generating circuit, 111 is an H-pulse phase variation circuit, 112 is one delay circuit, 113 is two delay circuits, 114 is three delay circuits, 115 is a selection switching circuit, and 11
6 is a selection switching control circuit, 117 is a phase comparison circuit, 118
Is a loop filter, and 119 is a voltage controlled oscillator VCO (Vo
Stage Controlled Oscillator:), 120 is a microcomputer, 121 is a switching circuit, 122 is an oscillator, 123 is a remote controller, 124 is a light receiving element, and 125 is a pixel display device.

The operation of the embodiment will be described below. An analog video signal corresponding to each color of R / G / B, which is a computer video signal, is output from the personal computer 101, and is input to the AD converter 105 via the R / G / B video input terminal 102. AD
In the conversion device 105, each of the analog video signals corresponding to each color is converted and output into a digital signal. here,
A dot clock signal used as a sampling clock signal required for digital conversion by the AD converter 105 is supplied to a sampling clock signal input terminal of the AD converter 105 through the operation described below. The vertical synchronization signal and the horizontal synchronization signal synchronized with the video signal output from the personal computer 101 are both input to the frequency determination circuit 109 via the vertical synchronization signal input terminal 103 and the horizontal synchronization signal input terminal 104, respectively.
The vertical synchronizing signal is supplied to the frequency dividing pulse generating circuit 110.
Is also entered. On the other hand, the horizontal synchronization signal is also input to the first input terminal of the phase comparison circuit 117. The frequency discriminating circuit 109 detects the frequency of the vertical synchronizing signal and the frequency of the horizontal synchronizing signal based on the input vertical synchronizing signal and the horizontal synchronizing signal.
Is input to

In the microcomputer 120, a video standard, for example, V
The frequency information of the vertical synchronization signal and the horizontal synchronization signal such as GA, SVGA, XGA, and UXGA is stored.
The vertical and horizontal frequency information input to 20 is collated to determine and specify the video standard. The frequency division value (n: positive value) information from the output of the microcomputer 120 is input to the frequency division pulse generation circuit 110. On the other hand, the dot clock signal generated by the voltage-controlled oscillator 119 is supplied to a clock input terminal of a counter such as a counter of the frequency-divided pulse generating circuit 110.
The n-frequency-divided pulse signal is output from the frequency-divided pulse generation circuit 110, and the (1 / n) -frequency-divided H pulse signal is output. This frequency division value is set so that the relationship between the frequency of the horizontal synchronization signal and the frequency of the required dot clock signal is established.
A frequency division value (n) corresponding to the number of pixels in the horizontal synchronization signal, for example, in the case of an SVGA standard signal, the frequency of the horizontal synchronization signal is 37.9 kHz and the frequency of the dot clock signal is 4
Since the frequency is 0 MHz, the frequency-divided pulse generating circuit 110 divides the value 40 MHz of the frequency of the dot clock signal by the value 37.9 kHz of the frequency of the horizontal synchronizing signal. Thus, an H pulse signal is output.

The H pulse signal is supplied to a selection switching circuit 115
At the first input terminal (a). The H pulse signal is supplied to the delay 1 circuit 113 and the delay 2 circuit 11
4. Each is input. The delay 1 circuit 113 is a flip-flop circuit, and the delay 1 circuit 113 latches the H pulse signal using the falling edge of the dot clock signal, and only 周期 cycle (= (１ ／) T) of the clock signal The delayed H pulse signal is output, and the selection switching circuit 115
To the second input terminal (b). Similarly, the delay 2 circuit 114 is also a flip-flop circuit, latches the H pulse signal using the rising edge of the dot clock signal, and outputs an H pulse signal delayed by one cycle (= T) of the dot clock signal. Are input to the third input terminal (c) of the selection switching circuit 115. Selection switching control circuit 1
16 is obtained from three input signals of the selection switching circuit 115 in FIG.
As shown in FIGS. 2 to 9 which are diagrams for supplementary explanation of
8 kinds of switching control are performed from SE = 0 to 7, and the selection switching circuit 1
15 outputs an H pulse signal.

First, when PHASE = 0 shown in FIG. 2, the selection switching control circuit 116 always selects and outputs the first input terminal (a) of the selection switching circuit 115. First, the PLL circuit 10 at the time when the horizontal synchronizing signal 201 starts to be input.
8 will be described below. Since the first input terminal (a) of the selection switching circuit 115 is always selected and output,
The H-pulse signal output from the frequency-divided pulse generation circuit 110 is output as it is from the selection switching circuit 115, and the waveform 2001 to the waveform 2001 depend on the magnitude relationship between the frequency of the output of the voltage controlled oscillator 119 and the frequency of the input synchronization signal. 20
A continuous H pulse signal as shown in the waveform 04 or the waveforms 2005 to 2008 is generated. This waveform 2
001, waveform 2002, waveform 2003, waveform 2004
Shows only the rising portion of the H pulse signal waveform. One cycle of the H pulse signal (= from the rising edge of the waveform 2001 to the rising edge of the next waveform 2002)
TH). Subsequently, the relationship between the waveforms 2002 and 2003, and the waveforms 2003 and 2004
Is the same. Waveforms 2005 to 200
8 is the same.

At this point, a self-running clock signal is oscillating from the voltage controlled oscillator 119, and the waveform 200
1, the rising edge of the input synchronization signal 201 and the rising edge of the H pulse signal do not coincide with each other and gradually shift as shown in waveforms 2002, 2003, and 2004. This indicates that the frequencies are different. This H pulse signal is input to the second input terminal of the phase comparison circuit 117, and the phase of the H pulse signal is compared with the horizontal synchronization signal input to the first input terminal. That is, the phase comparison circuit 117 monitors only a predetermined period before and after the rising edge of the input horizontal synchronization signal, and within this monitoring period, compares the phase difference information corresponding to the phase shift between the horizontal synchronization signal and the H pulse signal with the phase difference. Output as a pulse voltage signal. As shown in the waveform diagram, it becomes a phase difference pulse voltage signal indicated by a waveform 2011 corresponding to the difference between the input synchronization signal waveform 201 and the waveform 2001. Similarly, the phase difference pulse voltage signal between the input synchronization signal waveform 201 and the waveform 2002 is the waveform 2012, the input synchronization signal waveform 2
01 and the waveform 2003 have a phase difference pulse voltage signal of waveform 2
013, the phase difference pulse voltage signal between the input synchronization signal waveform 201 and the waveform 2004 is as shown in a waveform 2014.

When the rising edge of the H pulse signal is temporally delayed from the rising edge of the horizontal synchronizing signal as in this waveform, that is, the frequency of the H pulse signal is lower than the frequency of the horizontal synchronizing signal. In case, waveform 2
As shown by 011, waveform 2011, waveform 2011, and waveform 2014, the width of the shaded portion increases, and the waveform of the shaded portion is on the upper side. Conversely, when the rising edge of the H pulse signal is temporally ahead of the rising edge of the horizontal synchronization signal, the waveforms 2005 to 200
8, the phase comparison circuit 117 outputs the phase difference information corresponding to the deviation between the horizontal synchronizing signal and the H pulse signal in the same monitoring period as the waveforms 2015 and 20.
11, the waveform 2011 and the waveform 2014 gradually increase the width indicated by the hatched portion, and the waveform of the hatched portion is on the lower side.

The phase difference pulse voltage signal output from the phase comparison circuit 117 is smoothed by a loop filter 118, and a DC signal is output as the phase difference pulse voltage signal. Therefore, the waveform 201 is input to the input of the loop filter 118.
When a phase difference pulse voltage signal whose width gradually increases with the upper pulse as shown in 1 to 2014 is input, the DC voltage value of the output of the loop filter 118 gradually increases. Conversely, the waveform 2015 is applied to the input of the loop filter 118.
When a phase difference pulse voltage signal whose width gradually increases with the lower pulse as shown in waveform 2018 is input, the DC voltage value of the output of the loop filter 118 gradually decreases.
The DC value of the output of the loop filter 118 gradually increases for a signal in which the frequency of the H pulse signal is lower than the frequency of the input synchronization signal, that is, for a signal in which the upper pulse width voltage value increases as in the waveforms 2011 to 2014. Is output. Conversely, when the frequency of the H-pulse signal is higher than the frequency of the input synchronization signal, as in the waveforms 2005 to 2008, a DC voltage signal is output in which the DC value of the loop filter 118 output gradually decreases.

The operation described above is performed by the horizontal synchronizing signal 20.
This is a description of the operation at the start of input of No. 1. The DC signal output from the loop filter 118 is input to the voltage controlled oscillator 119. The voltage controlled oscillator 119 oscillates and outputs a clock signal having a higher frequency as the input voltage value increases, and oscillates and outputs a lower clock signal as the input voltage value decreases. A clock signal whose oscillation frequency varies in proportion is output.

Therefore, as described above, when the frequency of the H pulse signal is lower than the frequency of the horizontal synchronization signal,
Since the DC signal is input to the voltage-controlled oscillator 119 so that the DC value gradually increases, the voltage-controlled oscillator 119 is controlled so that the frequency is increased, and the voltage-controlled oscillator 119 is controlled.
The output gradually oscillates and outputs a high frequency clock signal. Conversely, when the frequency of the H pulse signal is higher than the frequency of the horizontal synchronization signal, the DC signal is input to the voltage controlled oscillator 119 so that the DC value gradually decreases. Is controlled to be low, and the output of the voltage controlled oscillator 119 gradually oscillates and outputs a low frequency clock signal. The clock signal thus controlled and output from the voltage controlled oscillator 119 is input to the clock input terminal of the counting circuit composed of a counter or the like in the frequency-divided pulse generating circuit 110 described above. Since a loop is formed, the operation is performed so that the phase difference between the input horizontal synchronizing signal and the H pulse signal eventually disappears, and the frequency of the H pulse signal becomes completely equal to the frequency of the horizontal synchronizing signal. The H pulse signal is completely locked to the horizontal synchronizing signal waveform 201.

As described above, at the start of the operation of the PLL circuit 108, the waveform 2001, the waveform 2002, and the waveform 200
3. Waveform 2004 or waveform 2005,
The self-running H-pulse signals of the waveform 2006, the waveform 2007, and the waveform 2008 completely correspond to the rising edge of the input horizontal synchronization signal waveform 201 as shown by the waveforms 2021, 2022, 2023, and 2024, respectively. The states coincide with each other, and steady and converge constantly to the position shown by the waveform 211. At the same time, the voltage controlled oscillator 119
As the output clock signal, a signal waveform 212 completely and stably locked to the horizontal synchronization signal 201 from the input terminal 104 is output.

The operation of the PLL circuit 108 when PHASE = 0 described above is the same as the operation of a very general PLL circuit. In addition, PHASE =
The operation of the PLL circuit 108 in 1 to 7 is an essential part of the present invention and will be described in detail.

First, the operation of the PLL circuit 108 when PHASE = 1 as shown in FIG. 3 will be described. The following description relates to the operation from the state in which the input of the horizontal synchronization signal has been started and a sufficient time has elapsed and the PLL circuit 108 has been stabilized as described above. The general operation of the PLL until this stable state is reached is PHASE = 1 to
7 is also the same as when PHASE = 0, so the description is omitted. In this stable state, it is assumed that the switching time from PHASE = 0 to PHASE = 1 has sufficiently passed. This PHASE = 1 when P
The difference from HASE = 0 is that when PHASE = 1, the selection switching control circuit 116 is connected to the first input terminal of the selection switching circuit 115.
(a) and the second input terminal (b) are selected and output an H pulse signal as described below. In the first line, a signal delayed and output by a (1/2) dot clock cycle by the delay 1 circuit 113 is the second switching signal of the selection switching circuit 115.
A signal having a phase as shown by a waveform 3001 input to the input terminal (b) is selectively output. From the second to fourth lines, the first input terminal (a) of the selection switching circuit 115 to which the output signal of the frequency-divided pulse generation circuit 110 is input
Waveforms 2022, 2023, and 2024 are selectively output. 4 lines of the selectively output H pulse signal are
An H-pulse signal repeated in this cycle is output from the selection switching circuit 115. This H pulse signal is input to the second input terminal of the phase comparison circuit 117.

As a result, a phase shift occurs between the waveform 3001 in FIG. 3 and the input synchronization signal waveform 201, and a phase difference pulse voltage signal having a waveform 3011 is output from the output of the phase comparison circuit 117. Also, the signal waveform 202
2. Since the waveforms 2023 and 2024 have timings that coincide with the input synchronization signal, the phase difference pulse voltage signals output from the phase comparison circuit 117 have waveforms 3012 and 2012, respectively.
As shown in the waveforms 3013 and 3014, the signal has no phase shift “0”. From the waveform 3011 to the waveform 301
The phase difference pulse voltage signal repeated in the cycle of 4 is sufficiently smoothed by the loop filter 118, and this phase difference pulse voltage signal is converted and output to a DC signal. The DC value of the converted and output DC signal is a value in which the voltage value is slightly increased by the amount of the pulse signal on the upper side of the waveform 3011 only once every four cycles compared to when PHASE = 0. For this reason,
From the output of the loop filter 118, this increase (= Δ
A DC signal whose DC value has increased by V) is output, and this output is input to the voltage controlled oscillator 119.

As a result, a clock signal having a slightly higher frequency is output from the output of the voltage-controlled oscillator 119 as compared with the case of PHASE = 0, so that the PHAS
The phase of the clock signal output from the pressure-controlled oscillator 119 is slightly advanced as compared with the case where E = 0. Here, this advanced time is represented by δ. For ease of explanation, it is assumed that the value is δ = (８) T. This T is the time of one cycle of the dot clock signal.

Next, the operation of the PLL circuit 108 when PHASE = 2 as shown in FIG. 4 will be described. In FIG. 4, the waveforms having the same numbers as those in FIG. 3 are the same waveforms. This PHAS
The difference between E = 2 and PHASE = 1 is that the third line
As shown in the waveform 4003, (1/1 /
2) A signal output delayed by the dot clock cycle is selectively output from the selection switching circuit 115. Therefore, not only the waveform 3001 but also the waveform 4003 is shifted in phase from the input synchronization signal waveform 201, so that not only the waveform 3011 but also the waveform 4011 is obtained from the output of the phase comparison circuit 117.
13 phase difference pulse voltage signals are also output. For this reason,
Compared to when PHASE = 1, the loop filter 118
The output voltage value is a value further increased by ΔV. Therefore, a DC signal that is increased by ΔV from PHASE = 1 is input to the voltage controlled oscillator 119, so that the voltage controlled oscillator 11
From the 9 outputs, a clock signal having a higher frequency than when PHASE = 1 is output.
The phase of the clock signal is further advanced by δ than when E = 1.

Therefore, the clock signal advances by (2/8) T from the rising edge of the input synchronizing signal 201 as compared with when PHASE = 0.

Further, as shown in FIG. 5, PHASE = 3
The operation of the PLL circuit 108 at this time will be described. In FIG. 5, the waveforms with the same numbers as those in FIG. 4 are the same waveforms. This PH
The difference between ASE = 3 and PHASE = 2 is that the signal output from the first line with a delay of (1/2) dot clock cycle by the delay 1 circuit 113 as shown in the waveform 5004 is the selection switching circuit 115. This is a point that is more selectively output. Therefore, not only the waveform 3001 and the waveform 4003 but also the waveform 500
4, a phase shift occurs between the input synchronization signal waveform 201 and the waveform 301 from the output of the phase comparison circuit 117.
A phase difference pulse voltage signal is output for not only 1 and the waveform 4013 but also the waveform 5014. For this reason, PHASE = 2
Compared with the time, the voltage value of the output of the loop filter 118 becomes a value further increased by ΔV. Therefore, PHASE = 2
The DC signal increased by ΔV from the voltage-controlled oscillator 119
Therefore, from the output of the voltage-controlled oscillator 119,
Since a clock signal having a higher frequency than that at the time of PHASE = 2 is output, the phase of the clock signal is further advanced by δ as compared with the case of PHASE = 2 on the time axis.

Therefore, the clock signal advances by (3/8) T from the rising edge of the input synchronizing signal 201 as compared with when PHASE = 0.

Next, the operation of the PLL circuit 108 when PHASE = 4 as shown in FIG. 6 will be described. In FIG. 6, the waveforms with the same numbers as those in FIG. 5 are the same waveforms. This PHAS
The difference between E = 4 and PHASE = 3 is that the second line
As shown in a waveform 6002, (1/1 /
2) A signal output delayed by the dot clock cycle is selectively output from the selection switching circuit 115. Therefore, the waveform 3001, the waveform 6002, the waveform 4003, and the waveform 500
4, a phase shift occurs between the input synchronization signal waveform 201 and the phase comparison circuit 11 in one cycle.
Waveforms 3011, 4013, and 5014 from 7 outputs
Not only the waveform 6012 but also the phase difference pulse voltage signal is output. For this reason, the voltage value of the output of the loop filter 118 becomes a value further increased by ΔV compared to when PHASE = 3. Therefore, a DC signal increased by ΔV from PHASE = 3 is input to the voltage controlled oscillator 119,
From the output of the voltage controlled oscillator 119, a clock signal having a higher frequency than when PHASE = 3 is output.
Compared to the case of ASE = 3, the phase of the clock signal is further δ
Will only proceed. Therefore, the clock signal advances by (4/8) T from the rising edge of the input synchronization signal 201 as compared with when PHASE = 0.

Similarly, PHASE = 5-7 will be described.
As shown in FIG. 7, the PLL circuit 108 when PHASE = 5
Will be described. In FIG. 7, the waveforms with the same numbers as those in FIG. 6 are the same waveforms. When PHASE = 5, PHASE = 4
The difference from the time point is that the signal output from the first line with a delay of one dot clock cycle by the delay two circuit 114 is selectively output from the selection switching circuit 115 as shown by a waveform 7001. Therefore, the waveform 7001 becomes the waveform 6012,
A phase difference pulse voltage signal having twice the width of the waveforms 4013 and 5014 is output. For this reason, PHASE =
As compared with 4 o'clock, the voltage value of the output of the loop filter 118 becomes a value further increased by ΔV. Therefore, PHASE =
The DC signal which is increased by ΔV from 4 is the voltage controlled oscillator 11
9, a clock signal having a higher frequency than that at the time of PHASE = 4 is output from the output of the voltage-controlled oscillator 119, so that the phase of the clock signal is further increased by δ than at the time of PHASE = 4. Will go on.

Therefore, the clock signal advances by (5/8) T from the rising edge of the input synchronizing signal 201 as compared with when PHASE = 0.

Next, the operation of the PLL circuit 108 when PHASE = 6 as shown in FIG. 8 will be described. In FIG. 8, the waveforms with the same numbers as those in FIG. 7 are the same waveforms. This PHAS
The difference between E = 6 and PHASE = 5 is that the third line
As shown by the waveform 8003, the signal output delayed by one dot clock cycle by the delay two circuit 114 is
15 is selectively output. Therefore, the waveform 701
Waveform 8013, waveform 6012, waveform 50
A phase difference pulse voltage signal having a width twice as large as that of 14 is output. For this reason, the voltage value of the output of the loop filter 118 becomes a value further increased by ΔV compared to when PHASE = 5. Therefore, since a DC signal increased by ΔV from PHASE = 5 is input to the voltage controlled oscillator 119, a clock signal having a higher frequency than that at the time of PHASE = 5 is output from the output of the voltage controlled oscillator 119.
The phase of the clock signal is further advanced by δ than when E = 5. Therefore, the clock signal advances by (6/8) T from the rising edge of the input synchronization signal 201 as compared to when PHASE = 0.

Next, the operation of the PLL circuit 108 when PHASE = 7 as shown in FIG. 9 will be described. In FIG. 9, the waveforms with the same numbers as those in FIG. 8 are the same waveforms. This PHAS
The difference between E = 9 and PHASE = 8: 00 is that the fourth line
As shown by the waveform 8003, the signal output delayed by one dot clock cycle by the delay two circuit 114 is
15 is selectively output. Therefore, the waveform 701
1 and the waveform 8013 as well as the waveform 9014, the waveform 60
A phase difference pulse voltage signal having a width twice as large as that of 02 is output. For this reason, the voltage value of the output of the loop filter 118 becomes a value further increased by ΔV as compared with when PHASE = 6. Therefore, since a DC signal increased by ΔV from PHASE = 6 is input to the voltage controlled oscillator 119, a clock signal having a higher frequency than that at the time of PHASE = 6 is output from the output of the voltage controlled oscillator 119.
The phase of the clock signal is further advanced by δ than when E = 6. Therefore, the clock signal advances by (7/8) T from the rising edge of the input synchronization signal 201 as compared with when PHASE = 0. As described above, by varying PHASE = 0 to 7, the output of the voltage-controlled oscillator 119 can be shifted from the output of the voltage-controlled oscillator 119 by a very short time as shown in FIG. A clock signal is output. In the graph of FIG. 10, the horizontal axis indicates PHASE = 0 to 7, and the horizontal axis indicates the advance time of the dot clock signal. This dot clock signal is supplied to a clock input terminal of the AD converter 105.

The dot clock signal is input to one input terminal of the switching circuit 121. Switching circuit 121
The clock signal oscillated by the oscillator 122 is input to the other input terminal of the input terminal. The switching circuit 121 switches and outputs one of the two input clock signals. The clock signal output from the switching circuit 121 is input to a read clock signal terminal of the video signal processing circuit 106.
It is also supplied to the clock signal terminal of the DA converter 107. The AD converter 105 converts the analog video signal into digital video signal data based on the dot clock signal. The digital video signal data is input to the video signal processing circuit 106. Video signal processing circuit 1
In step 06, pixel conversion such as enlargement or reduction of an image is performed, and the microcomputer 12
0 controls the switching of the input of the switching circuit 121, the video signal processing signal data is output from the video signal processing circuit 106 by the read clock signal output from the switching circuit 121, and D
An analog video signal is input from the A converter 107 and output from the DA converter 107. The analog video signal is input to the pixel display device 125 to display an image. PHASE = 0 to 7 in the selection switching control circuit 116 described above.
Can be selected by the user with the remote controller 123 via the microcomputer 120. In other words, when the user
A selection operation of PHASE = 0 to 7 is performed via 23.

The remote controller 123 emits a different infrared signal according to the selection information of PHASE = 0 to 7,
4 receives the infrared signal, and the light receiving element 124 converts the infrared signal into a voltage signal and outputs the voltage signal. Based on this voltage signal, the microcomputer 120 identifies the phase and outputs an identification signal. The selection switching control circuit 116 controls the switching of the switching circuit 115 based on the identification signal. The user looks at the image projected on the pixel display device 125, and uses the remote controller 123 to select the PHASE from 0 to 7 when the image quality without image blurring and no noise generation is optimal.
You can select the ASE number.

As described above, according to the present embodiment, the frequency-divided pulse generating circuit 110 divides the frequency based on the dot clock signal output from the voltage-controlled oscillator 119, and generates an H pulse signal having the same frequency as the horizontal synchronizing signal. Can be output. Delay 1 circuit 113, delay 2 circuit 114, and selection switching circuit 11
5 and a selection switching control circuit 116, the H-pulse phase variation circuit 111 receives the H-pulse signal as input, and sets PHASE =
It is possible to output an H-pulse signal having a combination of a plurality of types of delayed outputs such as 0 to 7 and having a periodicity to change the phase. Phase comparison circuit 117
Can detect the phase difference between the H pulse signal and the horizontal synchronizing signal, convert the phase difference information into a voltage difference signal, and output the voltage difference signal. The loop filter 118 can smooth the voltage difference signal, which is the phase difference information, and convert and output the signal to a DC signal.

Accordingly, by changing PHASE = 0 to 7, the voltage controlled oscillator 119 can change the phase of the dot clock signal at intervals of eight divided periods of one cycle of the dot clock signal. Therefore, the AD converter 105
In this case, even if an expensive delay element IC is not provided, the pixel data of the analog video signal can be sampled and converted into digital signal data by using a dot clock signal capable of adjusting the phase of the pixel data. There is an effect that high-definition analog video signal information can be maintained and converted to a digital video signal as it is without deteriorating or deteriorating the SN ratio.

In this embodiment, in order to facilitate the description, the combination of the H pulse signal and the delayed H pulse signal is changed with a periodicity with four lines as one cycle, and the PHASE of the combination is changed. Is 8 of 0-7
The delay amounts of the delay 1 circuit 113 and the delay 2 circuit 114 for giving the same phase and delaying the H pulse signal have been described as (1/2) T and T, respectively. The number of lines per cycle, the combination of the H pulse signal and the delayed H pulse signal, and the amount of delay are not limited to those described in this embodiment. That is, from the H pulse signal output from the frequency-divided pulse generation circuit 110 and a plurality of H pulse signals of different delay amounts resulting from the delay of the H pulse signal, a plurality of P signals are obtained by combining these signals.
A circuit configuration for generating an H pulse signal with HASE,
In addition, all algorithms are also included in the present invention. Further, the delay amount of the delay circuit for delaying the H pulse signal is made smaller than the value in the present embodiment, and a combination of a plurality of H pulse signals of different delay amounts obtained by delaying the H pulse signal as described above. If you increase the number, PHA
It should be noted that the step of adjusting the phase of the dot clock signal with respect to a change in the value of SE can be reduced, which has the effect of increasing the accuracy.

FIG. 11 is a block diagram showing another embodiment according to the present invention. 11, the same reference numerals as those in FIG. 1 indicate the same functions. In FIG. 11, 11001 is a (1/2) frequency dividing circuit, 11002 is a counter, 1100
3 is a decode 1 circuit, 11004 is a decode 2 circuit, 1
1005 is a decode 3 circuit. Hereinafter, although the configuration of the PLL circuit 108 in FIG. 11 is different from that in FIG. 1, it will be described below that the same operation as the PLL circuit 108 in FIG. Voltage controlled oscillator 119
1 oscillates and outputs a clock signal having a frequency twice the frequency of the dot clock signal, unlike the embodiment of FIG. The clock signal having the double frequency is input to the (1/2) frequency dividing circuit 11001 and the counter 11002. First,
The (1/2) frequency dividing circuit 11001 outputs a (1/2) frequency-divided clock signal. This clock signal corresponds to a dot clock signal. The dot clock signal is supplied to a sampling clock input terminal of the AD converter 105. The dot clock signal is also input to the video signal processing circuit 106 and the switching circuit 121. Each time a clock signal of twice the frequency of the dot clock signal is input, the counter 11002 outputs a count value whose value increases by one from 0. This counter 110
02 is output from the decode 1 circuit 1100
3 and decode 2 circuit 11004 and decode 3 circuit 110
05 and three decoding circuits. First, the decode 1 circuit 11003 decodes a count value m (m is a positive number) for generating the same frequency as the horizontal synchronization signal, and outputs an H pulse signal.

The value of m is, for example, a required frequency division value of 10 for an SVGA standard signal as described in FIG.
In this case, since a clock signal of twice the frequency is input to the counter 11002, m = 10
56 × 2-1 = 2111 is a necessary decode value. The H decoded by the decode 1 circuit 11003
The pulse signal is input to the first input terminal (a) of the selection switching circuit 115.

Here, the H-pulse signal output from the decode 1 circuit 11003 corresponds to the frequency-divided pulse generator 1 shown in FIG.
This corresponds to an H pulse signal of 10 outputs. Further, it is the same H pulse signal as the waveform 211 when PHASE = 0 described in FIG. Next, in the decode 2 circuit 11004, a value (m + 1) larger by one clock than the previous decode value m
Is decoded to output an H pulse signal. This signal is a signal that is delayed from the H pulse signal output from the decode 1 circuit 11003 by the time corresponding to (１) cycle of the dot clock signal.

Here, this H-pulse signal is applied to the delay 1 circuit 1
Thirteen outputs correspond to the H pulse signal. In addition, the decode 3 circuit 11005 outputs an H pulse signal created by decoding a value (m + 2) which is larger by one clock than the decode value (m + 1). This signal is a signal delayed by one dot clock signal period from the H pulse signal output from the decode 1 circuit 11003, and this H pulse signal corresponds to the H pulse signal output from the delay 2 circuit 114.

The H pulse signal output from the decode 2 circuit 11004 is input to the second input terminal (b) of the selection switching circuit 115. The H pulse signal output from the decode 3 circuit 11005 is supplied to the third input terminal (c) of the selection switching circuit 115.
Is input to Then, the output signal of the selection switching circuit 115 is input to the reset terminal of the counter 11002.
The counter 11002 detects the rising edge of the H pulse signal output from the selection switching circuit 115, resets the counter 11002, returns the count value of the counter 11002 to 0, starts incrementing by one, and outputs the count value. Then, the selection switching control circuit 11
Reference numeral 6 denotes a switching selection order of the input terminals of the selection switching circuit 115 as shown in the table of FIG. 12. When PHASE = 0, the input terminal (a) is selected from the first line to the fourth line, and this is selected for one cycle. When this cycle is repeated, the waveform 202 shown in FIG.
1, the same H pulse signal as the waveforms 2022, 2023, and 2024 is output. When PHASE = 1, the first line input terminal (b) is selected, and the input terminal (a) is selected from the second line to the fourth line. This is repeated as one cycle, and the waveform 3001 shown in FIG. Waveform 2022, Waveform 2
023, the same H pulse signal as the waveform 2024 is output. Similarly, for PHASE = 2 to 7, by switching the input terminal of the selection switching circuit 115 as shown in FIG. 12, the waveform 3 of the H pulse signal shown in FIGS.
001, waveform 2022, waveform 4003, waveform 2024
(When PHASE = 2), waveform 3001, waveform 2022, waveform 4003, and waveform 5004 (when PHASE = 3), waveform 300
1. Waveform 6002, Waveform 4003, Waveform 5004 (PHAS
E = 4), waveform 7001, waveform 6002, waveform 400
3. Waveform 5004 (when PHASE = 5), Waveform 7001, Waveform 6002, Waveform 8003, Waveform 5004 (PHASE = 6
), Waveform 7001, waveform 6002, waveform 8003, and waveform 9004 (at PHASE = 7). As a result, the H pulse signal becomes (（) of the dot clock signal.
Since it is possible to generate an H-pulse signal with a time interval of a cycle and with a certain periodicity, it is possible to generate an H-pulse signal exactly the same as the embodiment of FIG.

This H-pulse signal is input to the phase comparison circuit 117 and operates in exactly the same manner as in FIG. 1. Therefore, also in this embodiment in FIG. 11, by changing PHASE = 0 to 7, the voltage-controlled oscillator 119 The phase of the clock signal can be varied in time intervals obtained by dividing one period of the dot clock signal into eight. Therefore, the AD converter 105 can sample and convert the pixel data of the analog video signal into digital signal data by using the dot clock signal that can adjust the phase without using the expensive delay element IC. Therefore, there is an effect that high-definition analog video signal information can be maintained and converted into a digital video signal as it is without deteriorating the frequency characteristics and the SN ratio. Further, in the present embodiment, the decode value of the decode 2 circuit 11004 is (m + 1) and the decode value of the decode 3 circuit 11005 is H pulse, such as (m + 2), with respect to the decode value m of the decode 1 circuit 11003 as a reference. Although the cycle of the signal is made longer, the decode value of the decode 2 circuit 11004 may be shortened to (m-1), and the decode value of the decode 3 circuit 11005 may be shortened to (m-2). Also, the decode value of the decode 2 circuit 11004 may be (m-1), and the decode value of the decode 3 circuit 11005 may be (m + 1).

FIG. 13 is a block diagram showing still another embodiment according to the present invention. 13, the same reference numerals as those in FIG. 11 indicate the same functions. In FIG.
01 is a coincidence circuit, and 13002 is a frequency division value setting circuit.
FIG. 13 differs from FIG. 11 described above in that the configuration of the H-pulse phase variation circuit 111 is different. In the present H-pulse phase variation circuit 111, the microcomputer 120 outputs a plurality of frequency-divided digital data for periodically varying, and these digital data are input to the frequency-divided value setting circuit 13002. The frequency setting circuit 13002 is composed of a shift register, and these frequency-divided digital data are stored. For example, as an example of frequency-divided digital data, as shown in the table of FIG. 14, for example, when PHASE = 3, the frequency-divided digital data values are (m + 1), m, (m +
1) and (m + 1) are stored in the shift register of the frequency setting circuit 13002 in the order of the numbers 1 to 4 described in this table, and are updated as described below in this order so that the digital data value matches the matching circuit. 13001 is input to one input terminal. Then, a count value which is output from the counter 11002 and increases by one from 0 is input to one input terminal of the other matching circuit 13001. Match circuit 130
The 01 output signal is input to the reset terminal of the counter 11002. The output signal of the matching circuit 13001 is also input to the frequency division value setting circuit 13002.

In the coincidence circuit 13001, the count value output from the counter 11002 is applied to the coincidence circuit 1
When it becomes the same value as the set value (m + 1) of the 3001 output,
The matching circuit 13001 outputs a digital value “1” indicating a match. That is, a pulse signal having a period of (m + 1) dot clock is output. This matching circuit 13001
When the values of the two input signals are different, the value is "0". The digital value “1” of this output makes the counter 11
002 performs a reset operation, returns the count value to 0, and outputs a count value that increases by one. At the same time, the division value setting circuit 13002 updates the value stored in the shift register based on the digital value "1" of the output, and the second value m is output from the division value setting circuit 13002 and the coincidence circuit 13
001. By repeating this update operation, 2
A pulse signal of (m + 1) dot clock is output in the third period, and a pulse signal of (m + 1) dot clock is output in the third period. When the four lines have been completed, the process returns to the beginning and repeats with the first divided digital data, the second divided digital data,..., And the counter 1100 in the coincidence circuit 13001.
The coincidence with the two output signals is detected and repeated. In this manner, as shown in FIG.
22, exactly like waveform 4003, waveform 5004,
H-pulse signal having periodicity in 4 lines
001 and the H pulse signal is input to the phase comparison circuit 117, so that the operation is exactly the same as that of FIG.

In the example described here, the case where the periodicity of four lines is provided has been described. However, if it is desired to generate an H pulse signal having one cycle on L lines, L divided digital data is generated. Division value setting circuit 13002
Should be set to. If the operation described in PHASE = 3 is similarly performed also in PHASE = 0 to 2, and PHASE = 4 to 7, the voltage controlled oscillator 119 divides the dot clock signal phase into eight steps by dividing one cycle of the dot clock signal into eight. Can be changed. Therefore, the AD converter 105 can sample and convert the pixel data of the analog video signal into digital signal data by using the dot clock signal that can adjust the phase without using the expensive delay element IC. Since the analog video signal information can be converted into a digital video signal while maintaining high-definition analog video signal information without deteriorating the frequency characteristics and the SN ratio, the same effects as in the above-described embodiment can be obtained.

[0047]

According to the present invention, the phase relationship between the dot clock signal and the analog video signal can be variably adjusted by an inexpensive digital circuit which can be formed into an LSI without providing an expensive delay element IC. By using the signal as a sampling signal, there is an effect that the signal can be converted into a digital signal that maintains high-definition analog video signal information without deterioration in frequency characteristics or SN ratio.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a pixel display device including a PLL circuit according to one embodiment of the present invention.

FIG. 2 is a waveform chart for explaining the operation of the embodiment shown in FIG. 1;

FIG. 3 is a waveform chart for explaining the operation of the embodiment shown in FIG. 1;

FIG. 4 is a waveform chart for explaining the operation of the embodiment shown in FIG. 1;

FIG. 5 is a waveform chart for explaining the operation of the embodiment shown in FIG. 1;

FIG. 6 is a waveform chart for explaining the operation of the embodiment shown in FIG. 1;

FIG. 7 is a waveform chart for explaining the operation of the embodiment shown in FIG. 1;

FIG. 8 is a waveform chart for explaining the operation of the embodiment shown in FIG. 1;

FIG. 9 is a waveform chart for explaining the operation of the embodiment shown in FIG. 1;

FIG. 10 is a graph showing a lead time of a dot clock signal for each phase.

FIG. 11 is a block diagram illustrating an example of a pixel display device including a PLL circuit according to another embodiment of the present invention.

FIG. 12 is a diagram showing contents of switching control of a selection switching circuit 115 in another embodiment shown in FIG. 11;

FIG. 13 is a block diagram showing an example of a pixel display device including a PLL circuit according to still another embodiment of the present invention.

FIG. 14 is a diagram showing contents of setting data of a frequency dividing value setting circuit 13002 in still another embodiment shown in FIG. 13;

[Explanation of symbols]

 Reference Signs List 101 personal computer 102 R / G / B video input terminal 103 vertical synchronization signal input terminal 104 horizontal synchronization signal input terminal 105 AD converter 106 video signal processing circuit 107 DA converter 108 PLL circuit 109 Frequency discriminating circuit 110 Divided pulse generating circuit 111 H pulse phase variation circuit 112 Delay 1 circuit 113 Delay 2 circuit 114 Delay 3 circuit 115 Selection switching circuit 116 Selection switching control circuit 117 Phase comparison circuit 118 Loop filter 119 Voltage-controlled oscillator 120 Voltage-controlled oscillator 121 Switching circuit 122 Oscillator 123 Remote control 124 Light-receiving element 125 Pixel display device

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takaaki Matino 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Visual Information Media Division of Hitachi, Ltd. (72) Inventor Takeshi Sakai 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Address Co., Ltd.Hitachi Ltd.Video Information Media Division (72) Inventor Masato Sugiyama 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Pref.Hitachi Ltd. Multimedia System Development Headquarters (72) Inventor Kazuo Ishikura Tokyo Kodaira-shi, Tokyo Hitachi, Ltd. System LSI Development Center, 5-2-1 Mizumotocho Co., Ltd. (72) Inventor Koichi Sudo 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Pref.

Claims (6)

[Claims] 1. A PLL circuit for outputting a dot clock signal for sampling an input analog video signal, wherein a frequency fs of the dot clock signal is fs = f where a frequency of a horizontal synchronization signal of the input video signal is fH. fH
.Times.n (where n is a positive integer value), and a frequency dividing pulse generating means for generating an H pulse signal which is a pulse signal obtained by dividing the dot clock signal by (1 / n); Frequency dividing value varying means for varying the value of n in the frequency dividing value (1 / n) of the pulse generating means with periodicity, an H pulse signal output from the frequency dividing pulse generating means, and the horizontal synchronizing signal Phase comparison means for detecting the phase difference between the phase difference information and converting the phase difference information into a voltage difference signal or the like and outputting the same, a loop filter for smoothing the voltage difference signal output from the phase comparison means and converting and outputting the DC signal, A voltage-controlled oscillator that varies the frequency according to the DC value of the output of the loop filter and outputs the dot clock signal.
L circuit. 2. A PLL circuit for outputting a dot clock signal for sampling an input analog video signal, wherein the frequency fs of the dot clock signal is fs = f where the frequency of a horizontal synchronization signal of the input video signal is fH. fH
× n (where n is a positive integer), a frequency-divided pulse generating means for generating and outputting an H pulse signal which is a pulse signal obtained by dividing the dot clock signal by (1 / n);
H-pulse delay means for receiving the H-pulse signal and outputting an H-pulse signal delayed from a logic circuit such as a flip-flop based on the dot clock signal; and an H-pulse signal output from the frequency-divided pulse generating means or the H-pulse. Selection switching means for inputting an H pulse signal delayed from the output of the delay means, selecting and outputting only one signal from the input, and selecting control by giving a periodicity to the selection control method in the selection switching means And a phase comparison means for detecting the phase difference between the H pulse signal from the output of the selection switching means and the horizontal synchronizing signal, converting the phase difference information into a voltage difference signal or the like, and outputting the signal. A loop filter for smoothing the voltage difference signal output from the phase comparing means and converting and outputting the signal to a DC signal; and varying a frequency according to the DC value of the output of the loop filter. PLL circuit, comprising a voltage controlled oscillator for outputting the dot clock signal. 3. An input analog video signal is converted into a digital signal using a dot clock signal output from the PLL circuit according to claim 1 or 2.
D conversion circuit. 4. A video signal processing device comprising an AD conversion circuit for converting an input analog video signal into a digital signal using a dot clock signal output from the PLL circuit according to claim 1. . 5. A liquid crystal pixel display device comprising the video signal processing device according to claim 4. 6. A television signal receiving apparatus comprising the video signal processing apparatus according to claim 4.