JP2004260603A - Digital/analog converter, display panel drive circuit using the same, and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the power consumption of a digital/analog converter where an analogue voltage selected by a digital/analog converter of an R-2R type composed of a data latch circuit 22 and a resistor ladder circuit 23 is outputted via an operational amplifier 24. <P>SOLUTION: A comparison circuit 26 detects the match/mismatch of data for all bits in digital data. A CMOS tristate output circuit 25 bypasses the data latch circuit 22, the resistor ladder circuit 23, and the operational amplifier 24. If the data of all the bits agree, the operation of the operational amplifier 24 side is interrupted, and the CMOS tristate output circuit 25 is made to operate. Thus, without a special signal, the output circuit is switched in detail for lowering power consumption. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention provides a digital / analog converter, a display panel driving circuit which incorporates the digital / analog converter, is realized as an LSI for driving an active matrix type liquid crystal, and the like, and further includes the display panel driving circuit. And a display device configured.
[0002]
[Prior art]
A digital / analog converter built in the driving LSI of the active matrix liquid crystal creates an analog voltage corresponding to a plurality of bits of digital data from a video signal source and outputs the analog voltage to a source driver. FIG. 4 is a block diagram showing an electrical configuration of a typical digital / analog converter 1 according to the related art. The digital / analog converter 1 includes a data latch circuit 2, a resistor ladder circuit 3, an operational amplifier 4, an NMOSFET 5 for short-circuiting an output, an AND gate 6, and an inverter 7. I have.
[0003]
The data latch circuit 2 and the resistance ladder circuit 3 are configured, for example, as shown in FIG. The data latch circuit 2 and the resistance ladder circuit 3 constitute a so-called R-2R type digital / analog converter. The data latch circuit 2 includes a plurality of n (n is the number of input bits, 8 in FIGS. 4 and 5) D flip-flops F0 to Fn arranged in parallel with each other. A clock signal is commonly input from a video signal source (not shown) to the clock input terminal CK, a control signal PDCTL is also commonly input from a video signal source (not shown) to the control terminal RB, and a data input terminal D is Each of the plurality of bits of digital data is input, and a power supply voltage VDD or a GND potential is output from an output terminal Q.
[0004]
On the other hand, the resistance ladder circuit 3 is configured by connecting resistors having resistance values of R and 2 × R in a ladder shape. That is, one end of a series circuit formed by connecting two resistors having a resistance value of R in series is connected to the output terminals Q of the D flip-flops F0 to Fn, respectively. Are connected to each other, and the lowermost (corresponding to the least significant bit) series circuit is connected to the GND potential by a series circuit formed by connecting two resistors having a resistance value of R in series. The other end of the uppermost (corresponding to the most significant bit) serial circuit is the output terminal.
[0005]
While the control signal PDCTL is active at a high level, the D flip-flops F0 to Fn connect one end of the series circuit to the power supply voltage VDD as described above in accordance with the input digital signal. , Or to the GND potential, whereby the combined impedance of the resistance ladder circuit 3 changes, and an analog voltage corresponding to the input digital signal can be output. During the low level in which the control signal PDCTL is inactive, all the D flip-flops F0 to Fn connect one end of the series circuit to the GND potential, whereby the resistance ladder circuit 3 changes the GND potential. Output.
[0006]
For example, when only the most significant bit (MSB) of the input digital signal is "1" and the remaining bits are "0", an equivalent circuit of a resistor network as shown in FIG. 6 is obtained, and the output voltage is VDD / 2. It becomes. When only the two most significant bits are "1" and the remaining bits are "0", an equivalent circuit as shown in FIG. 7 is obtained, and the output voltage is VDD / 4. Thus, the input digital value can be converted into an analog voltage proportional to the digital value and output.
[0007]
FIG. 8 shows a configuration of a digital / analog converter in another digital / analog converter. This digital / analog converter is called a voltage potentiometer type and is the most primitive digital / analog converter. And 2 ⁿ And the same number of analog switches S1 to S2 forming a pair. ⁿ And an n-bit digital input decode circuit 10 and an operational amplifier 4a. 2 above ⁿ The reference resistors R are connected in series between a reference voltage Vref and a GND potential, and the connection point between these reference resistors R and the GND potential are determined by the analog switches S1 to S2. ⁿ Of the analog switches S1 to S2 ⁿ Is commonly connected to the non-inverting input terminal of the operational amplifier 4a.
[0008]
A digital input from a video signal source (not shown) is divided into n-bit binary data by ⁿ Are generated. In response to the decoded signal, only the analog switch at the tap position corresponding to the input code is turned on, and an analog voltage is output to the operational amplifier 4a. The operational amplifier 4a performs the voltage follower operation using the reference voltage Vref as a power supply voltage.
[0009]
The analog voltage obtained as described above can compensate for a non-linear relationship between a pixel voltage of a liquid crystal pixel and its light transmission when driving an active matrix liquid crystal. This is generally called gamma correction, and can be realized by configuring a digital / analog converter having more bits than digital input bits. Specifically, for example, a table for converting 6-bit data read from the display RAM into 6 bits → 8 bits before input of the digital / analog converter is prepared, and the number of gradations that can be expressed by this is prepared. The output data that increases from 64 gray scales to 256 finer gray scales and can obtain a γ curve corresponding to the characteristics of the liquid crystal to be used for the input data given by the 64 gray scales is converted to the 256 gray scales. It can be realized by selecting and applying from among the tones.
[0010]
Returning to FIG. 4 again, separately from the output path of the multi-gradation analog voltage corresponding to the input digital data of a plurality of bits by the resistance ladder circuit 3 and the operational amplifier 4, the output of the binary output by the AND gate 6 is provided. A route is provided. One input of the AND gate 6 receives data of the most significant bit (MSB) of the data latch circuit, and the other input receives an output of the inverter 7. The control signal PDCTL is input to the inverter 7, and therefore, when the control signal PDCTL is at the active high level, the inverted output of the inverter 7 is at the low level, and the output of the AND gate 6 is masked. . On the other hand, when the control signal PDCTL is inactive low level, the inverted output by the inverter 7 becomes high level, and the binary output by the AND gate 6 is allowed.
[0011]
On the other hand, when the control signal PDCTL is at the active high level, the resistance ladder circuit 3 operates as described above, and the inverted output of the inverter 7 becomes the low level, and the operational amplifier 4 enters the operating state. Then, the NMOSFET 5 for short-circuiting the output is turned off, and multi-gradation output by the operational amplifier 4 is allowed. On the other hand, when the control signal PDCTL is at the inactive low level, the resistance ladder circuit 3 stops operating as described above, and the inverted output of the inverter 7 goes to the high level, and the operational amplifier 4 At the same time as the standby state, the NMOSFET 5 for short-circuiting the output is turned on, and the multi-gradation output by the operational amplifier 4 is pulled down.
[0012]
The operational amplifier 4 and the AND gate 6 have individual output terminals 9 and 10, respectively. Correspondingly, as shown in FIG. 9, the liquid crystal panel 11 has a first terminal at one end of the source line SL. An analog driver 12 which is a source driver is mounted, and a digital driver 13 which is a second source driver is mounted on the other end side. The output terminals 9 and 10 are connected to the respective drivers 12 and 13 with a gradation display voltage. Will be output.
[0013]
The following prior arts exist as other prior arts related to the present invention. However, the description of this prior art will be made in the embodiments of the present invention for convenience of description.
[0014]
[Patent Document 1]
JP 2002-26732 A (publication date: January 25, 2002)
[0015]
[Problems to be solved by the invention]
The digital / analog converter 1 configured as described above is used by switching between the multi-gradation output on the operational amplifier 4 side and the binary output on the AND gate 6 side by the control signal PDCTL. The switching is performed between an image area where a halftone image can be displayed and an icon area where a predetermined character is displayed, as shown in FIG. 10, for example. , The image area is active high level, and the icon area is inactive low level.
[0016]
On the other hand, in the digital / analog converter 1, since the ability to drive various loads of the active matrix liquid crystal panel 11 is not sufficient, the operational amplifiers 4 and 4a are added as output buffers as described above to convert the output to a low output impedance. Thus, an interface with the liquid crystal display panel 11 is performed. However, in the operational amplifiers 4 and 4a, a bias current is always consumed even in a steady state. Further, these operational amplifiers 4 and 4a include a type that outputs a full swing to a given power supply voltage range such as a rail-to-rail type, but the power consumption is large especially at the time of the full swing output. Become.
[0017]
Therefore, if the switching is performed by the control signal PDCTL as described above, the operational amplifiers 4 and 4a are used when displaying the image of the maximum gradation or the minimum gradation in the image area, and the efficiency is low. There is. In addition, the control signal PDCTL must be input from a video signal source to a controller equipped with the digital / analog converter 1, and there is a problem that the number of terminals increases.
[0018]
An object of the present invention is to provide a digital / analog converter capable of switching output circuits finely without using a special signal and achieving low power consumption, and a display panel drive circuit and a display device using the same. .
[0019]
[Means for Solving the Problems]
The digital / analog converter of the present invention selects an analog voltage corresponding to the digital data by selectively switching a resistor interposed between power supply lines in accordance with a plurality of bits of digital data. A digital / analog converter configured to output the analog voltage via an operational amplifier, detects a match / mismatch of data of all bits of the digital data, and when the match is detected, the operation of the resistor circuit and the operational amplifier is performed. A comparison circuit to be paused, and in response to an output of the comparison circuit, when data coincidence of all bits of the digital data is detected, a high-level or low-level power supply voltage corresponding to the data is supplied to the resistance circuit and And a CMOS tri-state output circuit that outputs the signal by bypassing the operational amplifier.
[0020]
According to the above configuration, the digital / analog converter that generates an analog voltage used as a gradation display voltage of the liquid crystal display device in accordance with a plurality of bits of digital data. A CMOS tri-state output circuit that outputs a power supply voltage in a full swing so as to bypass these resistors and the operational amplifier. When the data of all the bits match, that is, the data of the maximum value or the minimum value, the comparison circuit suspends the operation of the resistor circuit and the operational amplifier, and supplies the high-level or low-level power supply voltage to the CMOS tristate output circuit. Full swing voltage is output.
[0021]
Therefore, when all the bit data match, the bias current of the operational amplifier is cut off by using the standby function of the operational amplifier, and the current flowing through the resistance circuit is also cut off, thereby reducing the power consumption in these circuits. The full-swinged maximum or minimum analog voltage can be output with higher efficiency than when it is output via an operational amplifier. Thus, the output circuit can be switched finely without using a special signal, and the power consumption of the digital / analog converter can be reduced.
[0022]
Further, the digital / analog converter according to the present invention is characterized in that the output of the operational amplifier and the output of the CMOS tristate circuit are connected in a wired-OR relationship.
[0023]
According to the above configuration, while one of the circuits is operating, the other circuit is inactive at the output from the comparison circuit as described above, so that the outputs of the two circuits are connected in common. Also, no short circuit between the outputs occurs. Thus, the output terminals can be shared, and the number of output terminals can be reduced.
[0024]
Still further, the display panel drive circuit of the present invention includes a timing controller which writes / reads the plurality of bits of digital data from a video signal source to / from a display RAM and outputs a synchronization signal to a display panel. Data read from the display RAM in response thereto is supplied to the display panel through the digital / analog converter.
[0025]
According to the above configuration, it is possible to reduce the power consumption of the display panel drive circuit implemented as a controller that applies a grayscale voltage to the source driver of the liquid crystal panel.
[0026]
Further, in the display panel drive circuit of the present invention, the digital data from the video signal source is constituted by including data of an icon image in a halftone image, and outputting the grayscale voltage of the halftone image by the operational amplifier. An output is used, and an output of the CMOS tristate circuit is used for outputting a binary voltage of the icon image.
[0027]
According to the above configuration, it is possible to realize a driving circuit suitable for driving a display panel including an image area and an icon area without using a special signal.
[0028]
Furthermore, a display device of the present invention uses the above-described display panel drive circuit.
[0029]
According to the above configuration, a display device with low power consumption can be realized.
[0030]
BEST MODE FOR CARRYING OUT THE INVENTION
One embodiment of the present invention will be described below with reference to FIGS.
[0031]
FIG. 1 is a block diagram showing an electrical configuration of a digital / analog converter 21 according to an embodiment of the present invention. The digital / analog converter 21 generally includes a data latch circuit 22, a resistance ladder circuit 23, an operational amplifier 24, a CMOS tristate output circuit 25, and a comparison circuit 26.
[0032]
The data latch circuit 22 and the resistance ladder circuit 23 are configured by an R-2R type digital / analog converter shown in FIG. 5, similarly to the digital / analog converter 1 shown in FIG. It goes without saying that a voltage potentiometer type digital / analog converter as shown in FIG. E may be used in place of the data latch circuit 22 and the resistance ladder circuit 23.
[0033]
It should be noted that, in the present invention, a CMOS tri-state output circuit 25 is provided so as to bypass the data latch circuit 22, the resistance ladder circuit 23 and the operational amplifier 24, and these are provided from outside such as the control signal PDCTL. Is switched by the comparison circuit 26 in accordance with the input digital signal without using the special signal. Further, the output terminal 27 is shared by the output terminal of the operational amplifier 24 and the output terminal of the CMOS tristate output circuit 25.
[0034]
The comparison circuit 26 detects whether all bits of the digital input match or not, and outputs a switching signal PD according to the result. The switching signal PD is directly input to the data latch circuit 22 and the operational amplifier 24, and is inverted and input to the CMOS tristate output circuit 25. Therefore, when the digital inputs are not completely coincident, the data latch circuit 22 and the operational amplifier 24 are in the operating state to allow the output on the multi-gray scale side, and the operation of the CMOS tristate output circuit 25 is stopped to perform the binary operation. Side output is blocked. On the other hand, when the digital inputs are all coincident, the operation of the data latch circuit 22 is stopped as described above, and the bias current of the operational amplifier is cut off by using the standby function of the operational amplifier 24, so that multi-gradation is performed. The output on the side is stopped, and the CMOS tristate output circuit 25 is activated, so that the output on the binary side is allowed.
[0035]
FIG. 2 is a timing chart for explaining the operation of the digital / analog converter 21 configured as described above. The comparison circuit 26 and the data latch circuit 22 take in the digital input data at the rising edge of the clock, and the comparison circuit 26 operates during the high level period of the clock to determine the level of the switching signal PD, and Until the clock goes high. Therefore, when the clock goes high, the output of the operational amplifier 24 or the CMOS tri-state output circuit 25 starts to rise and rises sufficiently before the next clock rise, thereby causing the sampling circuit in the liquid crystal panel to sample data. be able to. Therefore, the relationship between the data as shown in FIG. 2 and the actual sampling clock is adjusted by a delay circuit or the like according to the specifications of the liquid crystal panel.
[0036]
When the digital value is 8 bits as described above, if the digital value is halftone data as indicated by a reference numeral ** (hex), the comparison circuit 26 outputs the switching signal PD. As a result, the CMOS tristate output circuit 25 enters a high impedance state, the standby state of the operational amplifier 24 is released, and an analog voltage corresponding to the digital value input from the resistance ladder circuit 23 is output. , And output from the output terminal 27.
[0037]
On the other hand, when the digital input value is indicated by the reference numeral FF (hex) or 00 (hex), the maximum value or the minimum value, that is, the input digital bits are all "1", or "1". In the case of "0" and all match, the comparison circuit 26 outputs "0" to the switching signal PD, thereby turning on the CMOS tristate output circuit 25, outputting the power supply voltage VDD or the GND potential and the operational amplifier 24. Are in a standby state and are in a high impedance state, and the power supply voltage VDD or the GND potential is output from the output terminal 27.
[0038]
With the above configuration, when all the bit data match, the bias current of the operational amplifier 24 is cut off using the standby function of the operational amplifier 24, and the current flowing through the resistance ladder circuit 23 is also cut off. The power consumption of the circuit can be reduced, and the analog voltage that has fully swinged to the power supply voltage VDD or the GND potential can be output with higher efficiency than when the analog voltage is output via the operational amplifier 24. Thus, the output circuit can be switched finely without using a special signal, and the power consumption of the digital / analog converter can be reduced.
[0039]
Further, the operational amplifier 24 and the CMOS tristate circuit 25 output the output of the operational amplifier 24 because one of the circuits is inactive while the other circuit is inactive by the switching signal PD from the comparison circuit 26. And the output of the CMOS tristate circuit 25 are connected in a wired-OR relationship and the output terminal 27 is shared, so that the number of output terminals can be reduced.
[0040]
FIG. 3 is a block diagram showing a configuration example of a liquid crystal display device 32 using a liquid crystal drive controller IC 31 equipped with the above-described digital / analog converter 21. The controller IC 31 is connected to a bus line of the CPU 33 and is controlled by the CPU 33 to be used for, for example, a mobile phone. To the controller IC 31 from the CPU 33, which is a video signal source, a plurality of bits of digital data serving as a video signal, a clock, and the like are input.
[0041]
The controller IC 31 is provided with the digital / analog converter 21 for each of R, G, and B colors, and a display RAM 34 in which the plurality of bits of digital data from the CPU 33 are written. And a timing controller 36 for outputting a synchronizing signal to the liquid crystal panel 35.
[0042]
An output from the digital / analog converter 21 is input to a video input line 37 of the liquid crystal panel 35, and a shift register 38 in the liquid crystal panel 35 turns on a sampling gate 39 to change a source bus line capacitance 40. Charge up. The gate driver 41 sequentially turns on the gate of the TFT element 42 in the liquid crystal panel 35, and causes the liquid crystal element 43 to hold the charge charged up in the source bus line capacitance 40. As a result, the liquid crystal element 43 is turned on in accordance with the difference from the voltage applied to the common electrode 44 on the opposite side of the liquid crystal element 43.
[0043]
The timing controller 36 receives the digital data from the CPU 33 as described above, converts the digital data to an analog voltage through the digital / analog converter 21, and then sequentially transfers the analog voltage to the liquid crystal display panel 35. In the case where a still image is displayed as in the case where the display is performed, the controller IC 31 has a display RAM 34 for holding the display data input from the CPU 33, and the liquid crystal display may be performed without access from the CPU 33. It is possible. This is effective for reducing the operation occupancy of the CPU 33 with respect to the liquid crystal display and reducing the power consumption of the mobile phone. Thus, the power consumption of the mobile phone can be further reduced, in addition to the reduction in the power consumption of the controller IC 31 by the use of the digital / analog converter 21.
[0044]
The image displayed in the display area 45 of the liquid crystal display panel 35 is an image as shown in FIG. Recent mobile phones are capable of displaying images with a camera and also displaying photographic images, and such camera images and photographic images may be displayed on the entire screen of the display area 45. Instead, it is displayed in the image area at the center of the screen as shown in FIG. 10, and icons such as the battery charge state of the mobile phone and menu icons are displayed in the upper and lower icon areas. In many cases, this icon area indicates ON or OFF, that is, a display based on white. If the digital / analog converter 21 of the present invention is used, a special signal from the outside such as the control signal PDCTL is used. Such an icon display can be realized without switching between the operational amplifier 24 and the CMOS tri-state output circuit 25.
[0045]
Further, in realizing such an icon display, as apparent from a comparison between FIG. 3 and FIG. 9, the conventional liquid crystal panel 11 requires two drivers 12 and 13 for analog and digital. On the other hand, in the liquid crystal panel 35 of the present invention, only one source driver 46 needs to be mounted, and the frame can be narrowed and the number of terminals can be reduced.
[0046]
Here, Japanese Patent Application Laid-Open No. 2002-26732 is cited as a prior art relating to a reduction in power consumption of a digital / analog converter. However, this prior art divides a digital / analog converter into two stages, an upper bit and a lower bit, and converts the voltage specified by the upper bit digital / analog converter into a lower bit digital / analog converter. And outputs a fine analog voltage from the lower bit side digital / analog converter as an input to the capacitive load driven by the output voltage from the upper bit side digital / analog converter. The capacity of the buffer is reduced by charging in advance with the output from the digital / analog converter on the upper bit side, and then switching to the digital / analog converter on the lower bit side and charging to the target potential. In addition, low power consumption can be achieved.
[0047]
However, in this prior art, the charging period of the capacitive load is divided into two to reduce the power consumption, and the technique is completely different from that of the present invention. It is always driven.
[0048]
【The invention's effect】
As described above, the digital / analog converter of the present invention converts the analog voltage used as the gradation display voltage of the liquid crystal display device into a voltage follower by switching a resistor according to a plurality of bits of digital data and operating an operational amplifier. A CMOS tri-state output circuit that outputs a full swing of the power supply voltage is provided so as to bypass these resistors and an operational amplifier, and that all bits of the digital data match, that is, When the data is the value or the minimum value, the comparison circuit suspends the operation of the resistor circuit and the operational amplifier, and outputs the CMOS tri-state output circuit to a voltage that has been fully swinged to a high-level or low-level power supply voltage.
[0049]
Therefore, at the time of coincidence of all the bit data, the bias current of the operational amplifier is cut off by using the standby function of the operational amplifier, and the current flowing through the resistor circuit is also cut off, thereby reducing power consumption in these circuits. In addition, the maximum or minimum analog voltage that has undergone the full swing can be output with higher efficiency than when it is output via an operational amplifier. Thus, the output circuit can be switched finely without using a special signal, and the power consumption of the digital / analog converter can be reduced.
[0050]
Further, as described above, the digital / analog converter of the present invention connects the output of the operational amplifier and the output of the CMOS tristate circuit in a wired-OR relationship.
[0051]
Therefore, the output terminals can be shared, and the number of the output terminals can be reduced.
[0052]
Further, as described above, the display panel drive circuit according to the present invention is a display panel drive circuit implemented as a controller or the like that applies a grayscale voltage to a source driver of a liquid crystal panel. A timing controller for writing / reading data to / from the display RAM and outputting a synchronization signal to the display panel; and outputting data read from the display RAM in response to the synchronization signal to the display panel through the digital / analog converter. To supply.
[0053]
Therefore, power consumption of the display panel driving circuit can be reduced.
[0054]
Further, as described above, the display panel drive circuit of the present invention is configured such that the digital data from the video signal source is configured by including the data of the icon image in the halftone image and the output of the grayscale voltage of the halftone image. The output of the operational amplifier is used, and the output of the CMOS tristate circuit is used for the output of the binary voltage of the icon image.
[0055]
Therefore, a driving circuit suitable for driving a display panel including an image area and an icon area can be realized without using a special signal.
[0056]
Furthermore, the display device of the present invention uses the above-described display panel drive circuit as described above.
[0057]
Therefore, a display device with low power consumption can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an electrical configuration of a digital / analog converter according to an embodiment of the present invention.
FIG. 2 is a timing chart for explaining the operation of the digital / analog converter shown in FIG.
FIG. 3 is a block diagram showing one configuration example of a liquid crystal display device using a liquid crystal drive controller IC equipped with the digital / analog converter shown in FIG.
FIG. 4 is a block diagram illustrating the electrical configuration of a typical prior art digital / analog converter.
FIG. 5 is a block diagram illustrating a configuration of an R-2R type digital / analog converter.
FIG. 6 is an equivalent circuit diagram of a resistor network when only the most significant bit of an input digital signal is “1” and the remaining bits are “0” in the R-2R type digital / analog converter.
FIG. 7 is an equivalent circuit diagram of a resistor network in the R-2R type digital / analog converter when only the most significant bit of the input digital signal is “1” and the remaining bits are “0”; It is.
FIG. 8 is a block diagram showing a configuration of a voltage potentiometer type digital / analog converter.
FIG. 9 is a block diagram of a liquid crystal panel driven by a controller having the digital / analog converter shown in FIG. 4;
FIG. 10 is a diagram illustrating an example of a display image on a liquid crystal panel in a mobile phone.
[Explanation of symbols]
21 Digital / analog converter
22 Data latch circuit
23 Resistance ladder circuit (resistance circuit)
24 Operational Amplifier
25 CMOS tristate output circuit
26 Comparison circuit
27 Output terminal
32 Controller IC (display panel drive circuit)
32 liquid crystal display
33 CPU
34 Display RAM
35 LCD panel
36 Timing Controller
37 video input lines
38 shift register
39 Sampling gate
40 Source bus line capacity
41 Gate Driver
42 TFT device
43 Liquid crystal element
44 Common electrode
45 display area
F0-Fn D flip-flop
R resistor

Claims (5)

By selectively switching a resistor interposed between power supply lines in accordance with digital data of a plurality of bits, an analog voltage corresponding to the digital data is selected, and the selected analog voltage is output via an operational amplifier. Digital-to-analog converter
A comparison circuit that detects a match / mismatch of data of all bits of the digital data and, when the match is detected, suspends the operation of the resistor circuit and the operational amplifier;
In response to the output of the comparison circuit, when a match of data of all bits of the digital data is detected, a high-level or low-level power supply voltage corresponding to the data is output by bypassing the resistor circuit and the operational amplifier. And a CMOS tri-state output circuit. 2. The digital / analog converter according to claim 1, wherein the output of the operational amplifier and the output of the CMOS tristate circuit are connected in a wired-OR relationship. A timing controller that writes / reads the plurality of bits of digital data from a video signal source to / from a display RAM and outputs a synchronization signal to a display panel;
3. A display panel driving circuit for supplying data read from a display RAM in response to the synchronization signal to the display panel through the digital / analog converter according to claim 1 or 2. The digital data from the video signal source is configured by including an icon image data in a halftone image, an output of the operational amplifier is used to output a gradation voltage of the halftone image, and a binary value of the icon image is used. 4. The display panel driving circuit according to claim 3, wherein an output of said CMOS tri-state circuit is used for outputting a voltage. A display device using the display panel drive circuit according to claim 3.

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