JP2005295240A - Digital-analog converter circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital-analog converter circuit including a buffer amplifier suitable for different liquid crystal panels. <P>SOLUTION: The digital-analog converter circuit (100) is provided with a digital-analog converter (10) for converting a digital signal to an analog signal, the buffer amplifier (20) for buffering the analog signal converted by the digital-analog converter (10), and a buffer amplifier current control circuit (30) for controlling the current of the analog signal buffered by the buffering amplifier. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a digital-analog converter circuit, and more particularly to a digital-analog converter circuit that generates an analog signal based on a digital signal.

  In recent years, the demand for liquid crystal display devices is increasing, and the liquid crystal display devices are also used in, for example, mobile phones.

  A liquid crystal display device generally includes a digital-analog converter circuit that generates an analog signal based on a digital signal representing display data, and a liquid crystal panel that performs display using the analog signal. Even images such as photographs can be displayed in multiple gradations.

  The digital-analog converter circuit includes a digital-analog converter that converts a digital signal into an analog signal, and a buffer amplifier that buffers the analog signal converted by the digital-analog converter. The digital-analog converter is composed of a resistance element or the like.

When the capacitance value C, the resistance value R, the period F for charging / discharging the liquid crystal panel, and the voltage V are specified, the power of the liquid crystal panel is expressed as follows: Power P = 1/2 (C × F × V ² ) The current value and power value necessary for driving the liquid crystal panel can also be predicted by simulation or the like.

  Also, the characteristics of the liquid crystal panel are modeled as a resistance value R and a capacitance value C, and the current required for the digital-analog converter circuit to drive the liquid crystal panel is calculated using the resistance value R and the capacitance value C. can do. However, the resistance value R and the capacitance value C are values inherent to the liquid crystal panel and vary from one liquid crystal panel to another. Specifically, the resistance value R and the capacitance value C vary depending on conditions such as the resolution of the liquid crystal panel or the number of inches of the glass substrate constituting the liquid crystal panel.

  In a conventional liquid crystal display device, a buffer amplifier is manufactured to match the characteristics of one type of liquid crystal panel, so the buffer amplifier is suitable for driving a specific liquid crystal panel, but suitable for driving other liquid crystal panels. Not. When a buffer amplifier and a liquid crystal panel that are not suitable for each other are used in combination, the liquid crystal panel cannot properly sample an analog signal indicating display data, and the display panel displays an inappropriate display, or The digital-to-analog converter circuit consumes unnecessary power.

  In order to prevent these problems, it is necessary to manufacture a digital-analog converter circuit including a buffer amplifier for each liquid crystal panel. As a result, the development period of the liquid crystal display device becomes longer and the development cost increases.

  The digital-analog converter circuit of the present invention includes a digital-analog converter that converts a digital signal into an analog signal, a buffer amplifier that buffers the analog signal converted by the digital-analog converter, and a buffer that is buffered by the buffer amplifier. And a buffer amplifier current control circuit for controlling the current of the analog signal.

  The digital-analog converter includes an R-2R type digital-analog converter formed by a plurality of first resistors and a plurality of second resistors, each of the plurality of first resistors being And each of the plurality of second resistors may have a resistance value 2R that is twice the resistance value R of the first resistor.

  A latch circuit may be further provided that outputs the digital signal to the digital-analog converter by latching the digital signal according to the clock signal.

  The latch circuit is supplied with a power-down signal indicating whether the digital-analog converter circuit is to be operated or stopped, and the power-down signal causes the digital-analog converter circuit to be stopped. The latch circuit may output the digital signal to the digital-to-analog converter such that the voltage of the analog signal converted by the digital-to-analog converter is substantially equal to a ground voltage. .

  When the power down signal indicates that the digital-analog converter circuit is to be stopped, the signal corresponding to the most significant bit data of the data indicated by the digital signal before the latch circuit latches May be further provided.

  Since the digital-analog converter circuit according to the present invention can control the current output from the buffer amplifier in accordance with the liquid crystal panel having the inherent resistance value R and capacitance value C, the liquid crystal panel always outputs the signal optimally. While sampling, the capacity of the buffer amplifier can be set with optimum power.

  Also, different liquid crystal panels can be driven by one digital-analog converter circuit, thereby shortening the development period of the liquid crystal display device and reducing the development cost.

  In addition, according to the present invention, the digital-analog converter circuit can be stopped and the power consumption of the digital-analog converter can be reduced or substantially zero.

  Further, according to the present invention, when displaying a screen that does not need to be displayed in multiple gradations, for example, when displaying a standby screen of a mobile phone, the digital-analog converter is stopped and the CMOS buffer circuit is used. Thus, the liquid crystal panel can be driven with binary values, thereby reducing power consumed in display.

  Further, when the digital-analog converter circuit is in a standby state with the display on the liquid crystal panel being off, if the data represented by the digital signal input to the digital-analog converter is set to “0”, the synthesis in the digital-analog converter The resistor is not connected to the power supply, so that the power consumed by the digital-to-analog converter can be zero or substantially zero.

  The digital-analog converter is stopped, a digital signal representing the most significant bit data is input to the CMOS buffer circuit, and a binary signal is output to the liquid crystal panel. Eight colors can be displayed with bits. This is used, for example, when displaying a standby screen.

  In addition, the liquid crystal panel has a transflective liquid crystal that can be operated in both a reflective mode in which the backlight is turned off and display is possible only with outside light, and a transmissive mode in which the backlight is turned on and a brighter image is displayed. There is a panel.

  When a liquid crystal display device including such a transflective liquid crystal panel is used in a mobile phone, the transflective liquid crystal panel operates in a transmissive mode when a multi-tone image is displayed or a user operates a key. When the user does not use the cellular phone key, the transflective liquid crystal panel operates in the reflective mode in order to reduce the power consumption of the cellular phone battery.

  In this case, when the standby screen is displayed in the reflection mode, RGB is not displayed in multiple gradations as in the case of displaying an image such as a photograph, but each of RGB is displayed in binary, that is, the screen is displayed in eight colors. May be. In this case, what is displayed on the screen is, for example, the clock, the remaining battery level of the mobile phone, or the radio wave reception sensitivity state of the mobile phone.

  In such a case, partial display may be performed in order to suppress power consumption as much as possible. Partial display is a partial display of the screen. Further, when the mobile phone is not used for a certain period of time, for example, when the key of the mobile phone is not used for a certain period of time, the display screen of the mobile phone may be turned off. However, these states need to be switched to multi-gradation display when the key of the cellular phone is operated, and these states are supplied to the liquid crystal display device in consideration of the switching speed. The operation is stopped so that the supplied power is supplied. These states are also called standby states.

  FIG. 1 is a schematic diagram showing a digital-analog converter circuit 100 according to an embodiment of the present invention.

  The digital-analog converter circuit 100 includes a digital-analog converter 10 that converts a digital signal into an analog signal, and a buffer amplifier 20 that buffers the analog signal converted by the digital-analog converter 10 and outputs the buffered analog signal. A buffer amplifier current control circuit 30 that controls the current of the analog signal buffered by the buffer amplifier 20, and a latch circuit 44. The digital-analog converter circuit 100 further includes a level shifter 40. The digital-analog converter circuit 100 further includes a CMOS buffer 50 to which a part of a digital signal is input and a level shifter 60 to which a binary signal is input.

  The buffer amplifier current control circuit 30 includes a level shifter 32 to which a bias current control signal is input, and a bias circuit 34 that outputs a bias current corresponding to the bias current control signal input to the level shifter 32 to the buffer amplifier 20. .

  Here, the digital-analog converter 10 is an R-2R type digital-analog converter. In this case, the digital-analog converter circuit 100 is also referred to as an R-2R type digital-analog converter circuit. However, the digital-analog converter of the present invention is not limited to the R-2R type digital-analog converter, and the digital-analog converter of the present invention may be any converter that converts a digital signal into an analog signal.

  In the following description, a mode in which the digital-analog converter circuit 100 generates an analog signal based on an 8-bit digital signal will be described.

  An 8-bit digital signal D0 to D7, a clock signal Clock for synchronizing the output of the latch circuit 44, and a power-down signal PD are input to the latch circuit 44 via the level shifter 40.

  The latch circuit 44 outputs digital signals Q0 to Q7 corresponding to the digital signals D0 to D7 to the digital-analog converter 10 according to the clock signal Clock. Specifically, the latch circuit 44 latches the 8-bit digital signals D0 to D7 at the falling edge of the clock signal Clock, and aligns the digital signals Q0 to Q7 corresponding to the digital signals D0 to D7 with the same timing. Output to the digital-analog converter 10. In FIG. 1, the entire digital signals D0 to D7 are indicated as D [7: 0].

  The latch circuit 44 is supplied with a power-down signal PD that puts the digital-analog converter circuit 100 into an operating state or stops it. When the digital-analog converter circuit 100 is stopped, that is, when the power-down signal PD is high, the latch circuit 44 is reset. Details of this will be described later with reference to FIG.

The digital-analog converter 10 converts the digital signals Q0 to Q7 into the analog signal DA. Convert to OUT. The digital-analog converter 10 includes an analog signal DA having a voltage corresponding to the 8-bit digital signals Q0 to Q7. OUT is output to the buffer amplifier 20.

The buffer amplifier 20 receives the analog signal DA OUT is buffered, and an analog signal AOUT having a desired voltage is output to the liquid crystal panel 200 (see FIGS. 5 and 7). The buffer amplifier 20 receives the analog signal DA By buffering OUT, impedance conversion for interfacing with the liquid crystal panel 200 is performed.

The level shifter 32 has a 4-bit bias current control signal IB. CNT0 to CNT3 and a power down signal PD are input.

The bias circuit 34 generates a bias current control signal IB A bias current corresponding to CNT0 to CNT3 is output to the buffer amplifier 20.

  The settling time of the analog signal AOUT output from the buffer amplifier 20 is changed according to the magnitude of the bias current output from the bias circuit 34. The settling time will be described later with reference to FIG.

  Further, the power down signal PD is input to the level shifter 32. When the digital-analog converter circuit 100 is brought into a stop state, that is, when the power-down signal PD is high, the bias current output by the bias circuit 34 is reset, and supply of the bias current is stopped.

  The most significant bit data of the digital signal D [7: 0] is input to the CMOS buffer 50. That is, the digital signal D 7 is input to the CMOS buffer 50.

  A binary signal is input to the level shifter 60. The level of the binary signal is shifted by the level shifter 60 and input to the CMOS buffer 50.

  The CMOS buffer 50 also has a tri-state function, and the CMOS buffer 50 outputs a signal DOUT to the liquid crystal panel 200 (see FIGS. 5 and 7).

  The analog signal AOUT and the signal DOUT are connected inside the digital-analog converter circuit 100, and one of the analog signal AOUT and the signal DOUT is output to the liquid crystal panel 200 (see FIGS. 5 and 7). That is, when the analog signal AOUT is output, the signal DOUT has a high impedance, and when the signal DOUT is output, the analog signal AOUT has a high impedance.

  Alternatively, the analog signal AOUT and the signal DOUT may be output separately and connected outside the digital-analog converter circuit 100.

  When the Binary signal is “high”, the signal DOUT has a high impedance.

  When the digital-analog converter circuit 100 is brought into a stop state, that is, when the power-down signal PD becomes high and the analog signal AOUT output from the buffer amplifier 20 becomes high impedance, the binary signal is changed from “high” to “ “Low”.

  As a result, the data “1” or “0” of the most significant bit of the digital signal input from the CMOS buffer 50 to the digital-analog converter circuit 100 at that time is output as the signal DOUT of the CMOS buffer 50. As described above, when the data is displayed in binary, that is, 1 bit, power consumption can be significantly reduced. This is used, for example, when the liquid crystal panel 200 (see FIGS. 5 and 7) displays a standby screen.

  Hereinafter, the digital-analog converter 10 and the latch circuit 44 will be described.

  FIG. 2 is a schematic diagram showing details of the digital-analog converter 10 and the latch circuit 44. FIG. 2 also shows an external circuit 70.

  The latch circuit 44 includes eight D flip-flops 42, and any of the digital signals D <b> 0 to D <b> 7 is input to each of the eight D flip-flops 42.

  External circuit 70 includes an AND circuit 71, an AND circuit 72, and an inverter circuit 73.

  Inverter circuit 73 inverts power down signal PD.

  The AND circuit 71 generates a clock signal Clock for the latch circuit 44 by the logical product of the power down signal PD inverted by the inverter circuit 73 and the clock signal CK.

  The AND circuit 72 generates a clear reset bit signal Clearb for the latch circuit 44 by a logical product of the power down signal PD inverted by the inverter circuit 73 and the clear reset bit signal CLRB.

  The clock signal Clock and the clear reset bit signal Clearb generated by the external circuit 70 are input to each of the eight D flip-flops 42.

  Next, the eight D flip-flops 42 will be described. Here, for the purpose of preventing redundant description, the D flip-flop 42 to which the digital signal D7 is input will be described, but other D flip-flops 42 to which the digital signals D0 to D6 are input operate in the same manner. .

  The D flip-flop 42 outputs a digital signal Q7 corresponding to the digital signal D7 to the digital-analog converter 10 in response to the clock signal Clock. For example, when the digital signal D 7 indicates high when the clock signal Clock falls, the D flip-flop 42 outputs the high digital signal Q 7 to the digital-analog converter 10. Here, the voltage of the high digital signal Q7 is the power supply voltage AVDD. The voltage AVDD of the digital signal Q7 is held until the next falling edge of the clock signal Clock. When the digital signal D7 indicates low when the clock signal Clock falls, the D flip-flop 42 outputs the low digital signal Q7 to the digital-analog converter 10. Here, the voltage of the low digital signal Q7 is a ground voltage, that is, a zero voltage.

  When the clear reset bit signal Clear indicates low, the D flip-flop 42 resets the high or low state held at that time and becomes low. Here, since the other D flip-flops 42 to which the digital signals D0 to D6 are inputted operate in the same manner, when the clear reset bit signal Clear becomes high, all the eight D flip-flops 42 become low.

  The digital-analog converter 10 is formed by combining a plurality of first resistors 12 and a plurality of second resistors 14. The plurality of first resistors 12 each have a resistance value R, and the plurality of second resistors 14 each have a resistance value 2R that is twice the resistance value R of the first resistor 12. .

  In the digital-analog converter 10, all of the digital signals Q0 to Q7 output from the eight D flip-flops 42 are input to different second resistors 14, respectively.

  Hereinafter, Q0 to Q7 output from the eight D flip-flops 42 of the latch circuit 44 and the combined resistance of the digital-analog converter 10 will be described.

  FIG. 3 is a schematic diagram for explaining the combined resistance of the digital-analog converter 10 when the digital signals Q0 to Q7 represent data (10000000).

  Here, data 1 corresponds to high and data 0 corresponds to low. That is, the voltage of the digital signal Q7 is the voltage AVDD, and the voltages of the digital signals Q0 to Q6 are the ground voltage.

As shown in FIG. 3, in the case of data (10000000), an analog signal DA output from the digital-analog converter 10 The voltage at OUT is 1/2 * AVDD.

  FIG. 4 is a schematic diagram for explaining the combined resistance of the digital-analog converter 10 when the digital signals Q0 to Q7 represent data (00000000).

As shown in FIG. 4, in the case of data (00000000), the analog signal DA output from the digital-analog converter 10 is displayed. The voltage at OUT is the ground voltage.

  As described above, when the clear reset bit signal Clearb shown in FIG. 2 is low, that is, when the power-down signal PD is high and the clear reset bit signal CLRB is low, eight D All the flip-flops 42 are reset, and the digital signals Q0 to Q7 become data (00000000).

  As described above, when all of the digital signals Q0 to Q7 input to the digital-analog converter 10 are data "0", the combined resistor in the digital-analog converter 10 has no path from the power source. The power consumed by the analog converter 10 is zero or substantially zero.

Therefore, when the digital-analog converter circuit 100 is stopped, that is, when the power-down signal PD is “high”, the clock input of the 8-bit D flip-flop becomes invalid and is input to the reset terminal. The reset bit signal RB becomes “low”, and the digital signals Q0 to Q7 input to the digital-analog converter 10 all indicate data “0”. In this case, as described above, the analog signal DA output from the digital-analog converter 10 is used. OUT becomes “zero”, so that the power consumed is also “zero” or substantially zero.

Further, as described above, the digital-to-analog converter 10 outputs the analog signal DA output by the input data. The voltage of OUT is determined, and the digital signal is converted into an analog signal in the digital-analog converter 10 in this way.

  FIG. 5 is a schematic view showing a liquid crystal panel 200 of the present invention.

  FIG. 5A is a schematic diagram of the liquid crystal panel 200, and FIG. 5B is a schematic diagram in which a part of the liquid crystal panel 200 is enlarged. Here, the liquid crystal panel 200 is a monolithic liquid crystal panel typified by a low-temperature polysilicon liquid crystal panel.

  As shown in FIG. 5A, the liquid crystal panel 200 includes an analog driver 210, a gate driver 220, a display unit 230, and a common electrode 240.

  The liquid crystal panel 200 is formed by bonding two substrates to a liquid crystal. An analog driver 210 and a gate driver 220 are provided on one substrate, and a common electrode 240 is provided on the other substrate. . The display unit 230 is formed by two substrates.

  The analog driver 210 controls a plurality of source lines extending to the display unit 230.

  The gate driver 220 controls a plurality of gate lines extending to the display unit 230.

  The display unit 230 includes a plurality of pixels 232. FIG. 5A shows only one pixel 232 for the purpose of preventing the drawing from being overly complicated. The plurality of pixels 232 include a red pixel 234R, a green pixel 234G, and a blue pixel 234B, respectively. Here, the red pixel 234R, the green pixel 234G, and the blue pixel 234B are collectively referred to as a unit pixel 234.

  Each of the plurality of unit pixels 234 includes a thin film transistor 236 and a liquid crystal element 238. Each of the thin film transistors 236 includes a gate electrically connected to the gate line, a source electrically connected to the source line, and a drain electrically connected to the liquid crystal element 238. Note that here, a liquid crystal sandwiched between two substrates is electrically equivalently shown as a liquid crystal element 238.

  The common electrode 240 is electrically connected to the liquid crystal element 238.

  The analog driver 210 receives a red analog signal Red, a green analog signal Green, a blue analog signal Blue, and a data clock signal Dck. The data clock signal Dck is synchronized with the clock signal Clock shown in FIG.

  The analog driver 210 includes a plurality of analog switches 214 and a plurality of analog switches 214 that can be switched to supply any one of the red analog signal Red, the green analog signal Green, and the blue analog signal Blue to the source of the unit pixel 234. And a shift register 212 to be controlled.

  The analog switch 214 is a general term for the red analog switch 214R, the green analog switch 214G, and the blue analog switch 214B.

  The red analog switch 214R can be switched so that the red analog signal Red is supplied to the source of the thin film transistor 236 of the red pixel 234R, and the green analog switch 214G can be switched to the source of the thin film transistor 236 of the green pixel 234G. The blue analog switch 214B can be switched so that the blue analog signal Blue is supplied to the source of the thin film transistor 236 of the blue pixel 234B.

  The shift register 212 includes a red analog switch 214R, a green analog switch 214G, and a blue analog switch 214B so that the red analog switch 214R, the green analog switch 214G, and the blue analog switch 214B corresponding to one pixel 232 are switched at the same timing. It is preferable to control.

  Of the plurality of pixels 234 of the display unit 230, a pixel to be supplied with a signal is specified by the shift register 212 and the gate driver 220.

  Here, reference is made to FIG. FIG. 5B illustrates the red pixel 234R and the corresponding red analog switch 214R for the purpose of preventing the drawing from being overly complicated. However, it should be noted that the green pixel 234G and corresponding green analog switch 214G, and the blue pixel 234B and corresponding blue analog switch 214B are similar.

  The red analog signal Red is transmitted via the wiring 211. When the red pixel 234R is specified by the shift register 212 and the gate driver 220, the red analog signal Red is supplied to the specified red pixel 234R.

  Here, the wiring 211 is a wiring for transmitting a display data signal indicating display data such as a red analog signal Red, and is also referred to as a video wiring.

  The wiring 211 is a wiring that connects the digital-analog converter circuit 100 and the liquid crystal panel 200, and the wiring 211 can be regarded as having a resistor 240 and a capacitor 250.

  The wiring 211 is modeled by a resistance value R and a capacitance value C.

  FIG. 6 is a graph showing the time change of the voltage of the analog signal output from the digital-analog converter circuit 100. Here, the resistance value R = 220Ω and the capacitance value C = 200 pF of the wiring 211 are applied, and a rectangular wave having a voltage of 3.5 V is applied for a time of 500 ns.

  As shown in FIG. 6, the analog signal output from the digital-analog converter circuit 100 is charged in the wiring capacitor 250 with a time constant CR. The charged voltage is applied to the unit pixel 234 in which the analog switch 214 is turned on by the shift register 212 of the liquid crystal panel 200 and the gate of the thin film transistor 236 is turned on.

  As shown in the graph of FIG. 6, it takes a predetermined time for the voltage of the wiring 211 to reach the applied voltage, and the time until the voltage of the wiring 211 reaches zero after the voltage application is completed. Takes a certain amount of time.

  In this specification, all the times are called settling times, and in particular, the time until the voltage of the wiring reaches the applied voltage rises, the settling time, from the end of the voltage application until the wiring voltage reaches zero. Time is called falling settling time.

  Here, the buffer amplifier current control circuit 30 and the buffer amplifier 20 shown in FIG. 1 will be described.

FIG. 7 shows a 4-bit bias current control signal IB. 4 is a graph showing a relationship between INT [3: 0] and a bias current output to the buffer amplifier 20 by the buffer amplifier current control circuit 30.

As shown in FIG. 7, the bias current control signal IB As INT changes, the bias current changes. Bias current control signal IB As the number indicated by INT increases, the bias current also increases and the bias current control signal IB The number indicated by INT is proportional to the bias current.

FIG. 8 shows a 4-bit bias current control signal IB. It is a graph which shows the relationship between INT [3: 0] and settling time.

Bias current control signal IB As the number indicated by INT increases, both the rising and falling settling times decrease.

  Therefore, as can be understood from FIGS. 7 and 8, the bias current increases, and the rising settling time and the falling settling time decrease.

  As described above, according to the present invention, the settling time of the analog signal output from the buffer amplifier 20 can be changed by changing the bias current output from the buffer amplifier current control circuit 30 to the buffer amplifier 20. Therefore, the optimum settling time can be adjusted in consideration of variations between the resistance value R and the capacitance value C inherent to the liquid crystal panel.

  Therefore, in the bias amplifier current control circuit 30, the bias current depends on the required load power and the settling time for settling inside the liquid crystal panel depending on the load size of the liquid crystal panel 200 represented by the capacitance value C and the resistance value R. Is decided. Moreover, the settling time is adjusted within the operating frequency.

  As described above, the buffer amplifier current control circuit 30 controls the bias current according to the load characteristics of the liquid crystal panel 200, so that the buffer amplifier 20 can supply an optimal current to the liquid crystal panel 200.

  7 and 8 both show the relationship between the bias current and the settling time when the buffer amplifier 20 is designed using the TSMC process when R = 220Ω and C = 200 pF. This is a simulation result.

  FIG. 9 is a schematic diagram showing a liquid crystal display device 300 including a digital-analog converter circuit according to the present invention.

  The liquid crystal display device 300 includes a liquid crystal controller 400 (hereinafter also referred to as LCDC) that is a large-scale integrated circuit (LSI), and a liquid crystal panel 200 connected to the liquid crystal controller 400.

  The host 550 transmits a display data signal and a command signal for controlling the liquid crystal controller 400 to the liquid crystal controller 400.

  The liquid crystal controller 400 includes a host interface 405, a register 410, an oscillation circuit (OSC: oscillator) 415, a timing generator 420, a VRAM controller 425, a display random access memory (RAM), and a display RAM. ) 430, a gamma correction circuit 435, and a digital-analog converter circuit unit 450.

  The digital-analog converter circuit unit 450 includes a red digital-analog converter circuit 100R, a green digital-analog converter circuit 100G, and a blue digital-analog converter circuit 100B.

  The red digital-analog converter circuit 100R, the green digital-analog converter circuit 100G, and the blue digital-analog converter circuit 100B correspond to the digital-analog converter circuit 100 described with reference to FIG. Further, the red digital-analog converter circuit 100R, the green digital-analog converter circuit 100G, and the blue digital-analog converter circuit 100B are collectively referred to simply as a digital-analog converter circuit 100.

  The display data signal and the command signal output from the host 500 are input to the host interface 405. The host interface 405 stores the display data indicated by the display data signal in the display RAM 430, and the command data indicated by the command signal. Is stored in the register 410.

  The register 410 uses the stored command data to issue commands to a timing generator 420 that generates a timing signal for the liquid crystal panel 200 and a VRAM controller 425 that generates a timing for writing display data to the display RAM 430.

  The timing generator 420 generates a source control signal and a gate control signal as timing signals for controlling the liquid crystal panel 200.

  A signal input from the host 500 is synchronized with the timing of the oscillation circuit 415.

Display data stored in the display RAM 430 is input to the γ correction circuit 435.
The γ correction circuit 435 includes a red γ correction table 435R, a green γ correction table 435G, and a blue γ correction table 435B.

  Each of the red γ correction table 435R, the green γ correction table 435G, and the blue γ correction table 435B compensates for the non-linear relationship between the voltage of the pixel 232 of the liquid crystal panel 200 and its light transmission so as to match the liquid crystal characteristics. It was provided to do.

  Usually, the red γ correction table 435R, the green γ correction table 435G, and the blue γ correction table 435B are of a reference table method and can be rewritten.

  Of the display data corrected by the γ correction circuit 435, display data relating to red is input to the red digital-analog converter circuit 100R, and display data relating to green is input to the green digital-analog converter circuit 100G, and display data relating to blue. Is input to the blue digital-analog converter circuit 100B. Here, the display data is shown as a digital signal.

  The digital signal is converted into an analog signal by the red digital-analog converter circuit 100R, the green digital-analog converter circuit 100G, and the blue digital-analog converter circuit 100B.

  The analog signal is sent to the liquid crystal panel 200 in synchronization with the source control signal and the gate control signal generated by the timing generator 420.

  The DC / DC converter 550 generates a power supply voltage for the digital-analog converter 100 built in the liquid crystal controller 400 and a power supply voltage for the liquid crystal panel 200. The rise timing and fall timing of the signal output from the DC / DC converter 550 are controlled by the timing generator 420 of the liquid crystal controller 400.

  As described with reference to FIG. 5, the analog source driver 210 includes a shift register 212 and a plurality of analog switches 214.

  FIG. 10 shows signal waveforms in the liquid crystal display device 300 according to the embodiment of the present invention. Here, the resolution of the liquid crystal panel 200 of the liquid crystal display device 300 is 176 × 240.

  OSC is used as a clock signal for the timing generator 420 at the frequency of the oscillation circuit 415 in the liquid crystal controller 400.

  R [7: 0], G [7: 0], and B [7: 0] are 8-bit digital signals of red, green, and blue, respectively.

  The signal SCK and the signal SCKB are input as clocks of the shift register 212 of the analog source driver 210.

  The signal SSP corresponds to a horizontal synchronization signal. When the signal SSP is input, the shift register 212 sequentially sets the SR176 signal to the SR176 signal high according to the signals SCK and SCKB. Here, the SR1 signal is a signal for the pixels in the first column, and the SR176 signal is a signal for the pixels in the 176th column.

  Signals SR1 to SR176 switch on / off of the analog switch 214. The analog switch 214 is sequentially turned on in the dot direction, and voltages indicated by ROUT, GOUT, and BOUT are applied to the liquid crystal element 238.

  While the display data is being transferred, the power-down signal PD is “low” indicating that the digital-analog converter circuit 100 is in an operating state, and power consumption is reduced after transmitting the necessary display data. Therefore, it becomes “high” and the digital-analog converter circuit 100 is stopped.

  The signal GSPB corresponds to a vertical synchronization signal and is input to the gate driver 220 in the liquid crystal panel 200. The gate driver 220 is normally configured by a shift register, and sequentially turns on the gates of the thin film transistors 236 in the scanning direction by inputting the clock signals GCK1 and GCK2.

  In the above description, the digital-analog converter circuit outputs an analog signal obtained by converting a digital signal to the liquid crystal panel. However, the present invention is not limited to this. The present invention may output an analog signal obtained by converting a digital signal to an arbitrary device.

  In the above description, the digital-analog converter circuit generates an analog signal based on an 8-bit digital signal. However, the present invention is not limited to this. The present invention can be applied to a digital-analog converter circuit that generates an analog signal based on a digital signal having an arbitrary number of bits.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  As described above, according to the present invention, the buffer amplifier current control circuit adjusts the bias current output to the buffer amplifier in accordance with the characteristics of the liquid crystal panel modeled by the resistance value R and the capacitance value C. The current of the analog signal output from the buffer amplifier can be adjusted.

FIG. 1 is a schematic diagram of a digital-to-analog converter circuit according to an embodiment of the present invention. FIG. 2 is a schematic diagram showing details of the digital-analog converter and the latch circuit. FIG. 3 is a schematic diagram for explaining the combined resistance of the digital-analog converter when the digital signals Q0 to Q7 represent data (10000000). FIG. 4 is a schematic diagram for explaining the combined resistance of the digital-analog converter when the digital signals Q0 to Q7 represent data (00000000). FIG. 5 is a schematic view showing a liquid crystal panel of the present invention. FIG. 6 is a graph showing the time change of the voltage of the analog signal output from the digital-analog converter circuit. FIG. 7 shows a 4-bit bias current control signal IB. It is a graph which shows the relationship between INT [3: 0] and the bias current output to a buffer amplifier by a buffer amplifier current control circuit. FIG. 8 shows a 4-bit bias current control signal IB. It is a graph which shows the relationship between INT [3: 0] and settling time. FIG. 9 is a schematic view showing a liquid crystal display device including a digital-analog converter circuit according to the present invention. FIG. 10 shows signal waveforms in the liquid crystal display device according to the embodiment of the present invention.

Explanation of symbols

10. Digital-to-analog converter 12. Resistor 14. Resistor 20. Buffer amplifier 30. Buffer amplifier current control circuit 32. Level shifter 34. Bias circuit 40. Level shifter 42. D flip-flop 44. Latch circuit 50. CMOS buffer 60. Level shifter 70. External circuit 71. AND circuit 72. AND circuit 73. Inverter circuit 100. Digital-analog converter circuit 200. Liquid crystal panel 210. Analog driver 211 wiring 212. Shift register 214. Analog switch 220. Gate driver 230. Display unit 232. Pixel 234. Unit pixel 236. Thin film transistor 238. Liquid crystal element 240. Common electrode 300. Liquid crystal display device 400. Liquid crystal controller 405. Host interface 410. Register 415. Oscillator circuit 420. Timing generator 425. VRAM controller 430 Display RAM
435. γ correction circuit 450. Digital-analog converter circuit

Claims (5)

A digital-to-analog converter for converting a digital signal into an analog signal;
A buffer amplifier for buffering an analog signal converted by the digital-analog converter;
A digital-analog converter circuit comprising: a buffer amplifier current control circuit that controls a current of an analog signal buffered by the buffer amplifier. The digital-analog converter includes an R-2R type digital-analog converter formed by a plurality of first resistors and a plurality of second resistors,
Each of the plurality of first resistors has a resistance value R;
2. The digital-analog converter circuit according to claim 1, wherein each of the plurality of second resistors has a resistance value 2R that is twice the resistance value R of the first resistor.   The digital-analog converter circuit according to claim 1, further comprising a latch circuit that outputs the digital signal to the digital-analog converter by latching the digital signal according to a clock signal. The latch circuit receives a power-down signal indicating whether the digital-analog converter circuit is in an operation state or a stop state,
When the power-down signal indicates that the digital-analog converter circuit is to be stopped, the latch circuit causes the voltage of the analog signal converted by the digital-analog converter to be substantially equal to the ground voltage. 4. The digital-analog converter circuit according to claim 3, wherein the digital signal is output to the digital-analog converter.   When the power-down signal indicates that the digital-analog converter circuit is to be stopped, the signal corresponding to the most significant bit of the data indicated by the digital signal before the latch is latched by the latch circuit The digital-to-analog converter circuit according to claim 3, further comprising a CMOS buffer circuit that outputs.

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