CN106130549B - Digital-to-analog converter with adjustable voltage conversion rate - Google Patents
Digital-to-analog converter with adjustable voltage conversion rate Download PDFInfo
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- CN106130549B CN106130549B CN201610455048.0A CN201610455048A CN106130549B CN 106130549 B CN106130549 B CN 106130549B CN 201610455048 A CN201610455048 A CN 201610455048A CN 106130549 B CN106130549 B CN 106130549B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
- H03M1/126—Multi-rate systems, i.e. adaptive to different fixed sampling rates
Abstract
The invention provides a digital-to-analog converter with adjustable voltage conversion rate in a power management chip, which comprises a rate adjusting circuit, a digital comparison circuit and a resistor network. The rate adjusting circuit adjusts the establishing time of the digital-to-analog converter through a conversion rate selecting end according to the requirement of conversion rate; the digital comparison circuit judges whether the data of the input signal end are equal to the converted data, if so, logic conversion is completed, and a switch of a binary level control resistor network is generated; the resistor network converts input data into corresponding analog voltage values. The digital-to-analog converter can adjust the conversion rate of output voltage through the rate adjusting circuit according to the requirement of conversion speed, ensures accurate and stable conversion of output analog voltage values, does not use an active operational amplifier inside the digital-to-analog converter, and is beneficial to saving static power consumption of a circuit.
Description
Technical Field
The invention belongs to the technical field of digital-analog hybrid integrated circuits, and particularly relates to a digital-analog converter in a power management chip, which is a digital-analog converter with adjustable voltage conversion rate.
Background
With the continuous development of semiconductor technology in China, as an interface between a digital circuit and an analog circuit, a digital-to-analog converter is widely applied to a power management chip design, and can recognize a digital signal and output a corresponding analog voltage value.
The digital-to-analog converter with adjustable voltage conversion rate is introduced into the power management chip to control the conversion rate of the output voltage of the chip in real time, and the rate value is controlled according to the rate regulating circuit, so that the soft start time of the chip is regulated according to the working state of the circuit, and the chip can work normally. Compared with the existing digital-to-analog converter technology with adjustable voltage conversion rate, the chip can reach the voltage value of millivolt per change in the regulation rate, and the conversion rate reaches microsecond magnitude, so that the digital-to-analog converter has the characteristics of higher conversion accuracy and wider practical range.
Disclosure of Invention
In order to solve the above problems, the present invention provides a digital-to-analog converter with adjustable voltage conversion rate, which can adjust the conversion rate of output voltage during switching by a rate adjusting circuit according to the working state of a chip, thereby controlling the soft start time of the chip, ensuring that the analog voltage value at the output end is accurately and stably converted, and adopting the implementation form of a resistor network in the digital-to-analog converter without using an active operational amplifier, which is beneficial to saving the static power consumption of a circuit.
The invention aims to provide a digital-to-analog converter with adjustable voltage conversion rate, which is applied to a power management chip. The design key point of the invention is as follows:
the digital-to-analog converter comprises a rate adjusting circuit, a digital comparison circuit and a resistance network, wherein the rate adjusting circuit adjusts the set-up time of the digital-to-analog converter through a conversion rate selection end according to the requirement of analog output voltage conversion rate, the digital comparison circuit compares at least one bit of digital input end data with data output by a counter in the digital comparison circuit, and the resistance network converts digital output end data into corresponding analog voltage values.
The clock signal output end of the rate adjusting circuit is connected with the digital input end of the digital comparison circuit, and the digital output end of the digital comparison circuit is connected with the input end of the resistor network.
The rate adjustment circuit is composed of a D trigger and a data selector.
The clock signal of the speed regulating circuit is connected with the clock signal of the first D trigger dff1 and the data end D of the first data selector mux1 1 The conversion rate selection end is connected with the data selection ends of the first data selector mux1, the second data selector mux2 and the third data selector mux3, and the data input end of the first D trigger dff1 is connected with the reverse data output end of the first D trigger dff1 and the data end D of the first data selector mux1 0 The data input end of the second D trigger dff2 is connected with the reverse data output end of the second D trigger dff2, the data input end of the third D trigger dff3 is connected with the reverse data output end of the third D trigger dff3 and the data end D of the second data selector mux2 0 The data input end of the fourth D trigger dff4 is connected with the reverse data output end of the fourth D trigger dff4, and the data input end of the fifth D trigger dff5 is connected with the reverse of the fifth D trigger dff5To the data output end, the data input end of the sixth D trigger dff6 is connected with the reverse data output end of the sixth D trigger dff6, the data input end of the seventh D trigger dff7 is connected with the reverse data output end of the seventh D trigger dff7 and the data end D of the third data selector mux3 0 The output end of the first data selector mux1 is connected with the clock signal of the second D trigger dff2 and the data end D of the second data selector mux2 1 The output end of the second data selector mux2 is connected with the clock signal of the fourth D flip-flop dff4 and the data end D of the third data selector mux3 1 The clock signal output terminal is connected to the inverted output terminal of the third data selector mux 3.
The rate adjusting circuit generates signal waveforms with different frequencies according to the clock signal and the signal value of the conversion rate selecting end, and dynamically adjusts the conversion rate of the analog voltage output value according to the signal value set by the conversion rate selecting end.
The digital comparison circuit consists of at least one exclusive-or gate, a NAND gate, an inverter and a D trigger.
The input end of the first inverter inx1 of the digital comparison circuit is connected with the forward output end of the first D trigger and the input end of the n-th NAND gate, the output end of the first inverter inx1 is connected with the input end of the first exclusive-OR gate xor1, the input end of the first D trigger is connected with the output end of the first exclusive-OR gate xor1, the clock signal input end of the first D trigger is connected with the clock signal output end from the rate adjustment circuit, the reverse output end of the first D trigger is connected with the input end of the digital comparator 1, the other input end of the digital comparator 1 is connected with the highest-order digital input end, and the output end of the digital comparator 1 is connected with the input end of the second inverter inx 2.
The digital comparison circuit is used for continuously converting digital signal values, judging whether the data at the digital input end is equal to the data output by the counter in the digital comparison circuit, if the signals of the digital comparison circuit are all high-level representing conversion completion, outputting the data at the digital output end to the input end of the resistor network, and if the conversion is not completed, continuing to perform counting conversion.
The resistor network consists of at least one resistor and a switch tube and is used for converting a six-bit digital signal into an analog signal voltage value corresponding to the digital signal.
The reference voltage of the resistor network is sequentially connected with the resistor R with the ground terminal 1 To R 64 Switch S 0 The first end of the resistor with even number is connected with the switch
The first ends of the resistors with odd subscripts are connected, and the switch S 1 And->
Respectively connected with each switch S 0 、/>
In this connection, S 5 、/>
Connecting signal output terminal V OUT 。
The voltage value at the ith resistance joint of the resistance network is as follows:
wherein V is REF Is the reference voltage value. Output voltage value V of analog output terminal OUT The size is determined based on the binary word of the selected switch.
The invention has the beneficial effects that: the voltage conversion rate-adjustable digital-to-analog converter can control the conversion rate of the chip output voltage in real time when in switching, and the rate value is controlled according to the rate regulating circuit, so that the time for soft start of the chip is regulated according to the working state of the circuit, and the chip can work normally. The chip can reach voltage value of every millivolt change in regulating speed, the conversion speed reaches microsecond magnitude, and the digital-to-analog converter has the characteristics of higher conversion accuracy and wider practical range. And the digital-to-analog converter adopts the realization form of a resistor network instead of an active operational amplifier, thereby being beneficial to saving the static power consumption of the circuit and being worthy of application and popularization.
Drawings
The invention is further described below with reference to the accompanying drawings:
FIG. 1 is a schematic block diagram of a digital-to-analog converter with adjustable voltage slew rate according to the present invention;
FIG. 2 is a schematic diagram of a rate adjustment circuit configuration;
FIG. 3 is a schematic diagram of a logic comparison circuit;
FIG. 4 is a schematic diagram of a resistor network structure;
fig. 5 is a graph of simulated output variation at each slew rate.
Detailed Description
The digital-to-analog converter applied by the invention comprises a rate adjusting circuit, a logic comparison circuit and a resistor network. The specific implementation mode is as follows:
FIG. 1 is a block diagram of the present invention, a voltage conversion rate adjustable digital to analog converter, comprising a rate adjustment circuit, a digital comparison circuit and a resistor network.
Fig. 2 is a schematic diagram of a rate adjustment circuit corresponding to the embodiment of fig. 1, and is specifically as follows:
the clock signal is connected with the clock signal of the first D trigger dff1 and the data end D of the first data selector mux1 1 The conversion rate selection end is connected with the data selection ends of the first data selector mux1, the second data selector mux2 and the third data selector mux3, and the data input end of the first D trigger dff1 is connected with the reverse data output end of the first D trigger dff1 and the data end D of the first data selector mux1 0 The data input end of the second D trigger dff2 is connected with the reverse data output end of the second D trigger dff2, the data input end of the third D trigger dff3 is connected with the reverse data output end of the third D trigger dff3 and the data end D of the second data selector mux2 0 The data input end of the fourth D trigger dff4 is connected with the reverse data output end of the fourth D trigger dff4, and the data input end of the fifth D trigger dff5 is connected withThe data input end of the sixth D trigger dff6 is connected with the reverse data output end of the sixth D trigger dff6, the data input end of the seventh D trigger dff7 is connected with the reverse data output end of the seventh D trigger dff7 and the data end D of the third data selector mux3 0 The output end of the first data selector mux1 is connected with the clock signal of the second D trigger dff2 and the data end D of the second data selector mux2 1 The output end of the second data selector mux2 is connected with the clock signal of the fourth D flip-flop dff4 and the data end D of the third data selector mux3 1 The clock signal output terminal is connected to the inverted output terminal of the third data selector mux 3. The rate adjusting circuit can adjust the set-up time of the digital-to-analog converter through the conversion rate selection end according to the conversion rate requirement, namely dynamically adjust the frequency of the clock signal output end according to the three-bit conversion rate selection end, so that the digital-to-analog converter can be ensured to stably switch the conversion rate.
Fig. 3 is a schematic diagram of a digital comparison circuit corresponding to the embodiment of fig. 1, specifically as follows:
the input end of the first inverter inx1 is connected with the forward output end of the first D trigger and the input end of the n-th NAND gate, the output end of the first inverter inx1 is connected with the input end of the first exclusive-OR gate xor1, the input end of the first D trigger is connected with the output end of the first exclusive-OR gate xor1, the clock signal input end of the first D trigger is connected with the clock signal output end from the rate adjusting circuit, the reverse output end of the first D trigger is connected with the input end of the digital comparator 1, the other input end of the digital comparator 1 is connected with the highest-order digital input end, the output end of the digital comparator 1 is connected with the input end of the second inverter inx2, and the connection method is similar to obtain the digital output end.
The digital comparison circuit judges whether the data of the input signal end and the converted data are equal, and if the data are equal, the logic conversion is completed, and a switch of the binary level control resistor network is generated.
Fig. 4 is a schematic circuit diagram of a resistor network corresponding to the embodiment of fig. 1, specifically as follows:
reference voltage and ground are connected with resistor R in turn 1 To R 64 Switch S 0 The first end of the resistor with even number is connected with the switch
The first ends of the resistors with odd subscripts are connected, and the switch S 1 And->
Respectively connected with each switch S 0 、/>
In this connection, S 5 、/>
Connecting signal output terminal V OUT . The voltage value at the i-th resistor junction is:
wherein V is REF Is the reference voltage value. Output voltage value V OUT The size is determined based on the binary word of the selected switch.
Fig. 5 is a graph of analog output variation at slew rate, where the left plot signal has a flatter slope than the right plot signal, so the rise time for the left plot signal to settle is slower than the rise time for the right plot signal to settle. It can be seen that the degree of slew rate can be adjusted as the output voltage switches.
In summary, the scheme of this embodiment is as follows: the clock signal of the rate adjusting circuit is connected with the clock signal of the first D trigger dff1 and the data end D of the first data selector mux1 1 The conversion rate selection end is connected with the data selection ends of the first data selector mux1, the second data selector mux2 and the third data selector mux3, and the data input end of the first D trigger dff1 is connected with the reverse data output end of the first D trigger dff1 and the data end D of the first data selector mux1 0 Number of second D flip-flop dff2The data input end of the third D trigger dff3 is connected with the reverse data output end of the third D trigger dff3 and the data end D of the second data selector mux2 0 The data input end of the fourth D trigger dff4 is connected with the reverse data output end of the fourth D trigger dff4, the data input end of the fifth D trigger dff5 is connected with the reverse data output end of the fifth D trigger dff5, the data input end of the sixth D trigger dff6 is connected with the reverse data output end of the sixth D trigger dff6, the data input end of the seventh D trigger dff7 is connected with the reverse data output end of the seventh D trigger dff7 and the data end D of the third data selector mux3 0 The output end of the first data selector mux1 is connected with the clock signal of the second D trigger dff2 and the data end D of the second data selector mux2 1 The output end of the second data selector mux2 is connected with the clock signal of the fourth D flip-flop dff4 and the data end D of the third data selector mux3 1 The clock signal output terminal is connected to the inverted output terminal of the third data selector mux 3.
The input end of the first inverter inx1 of the digital comparison circuit is connected with the forward output end of the first D trigger and the input end of the sixth NAND gate, the output end of the first inverter inx1 is connected with the input end of the first exclusive-OR gate xor1, the input end of the first D trigger is connected with the output end of the first exclusive-OR gate xor1, the clock signal input end of the first D trigger is connected with the clock signal output end from the rate adjustment circuit, the reverse output end of the first D trigger is connected with the input end of the digital comparator 1, the other input end of the digital comparator 1 is connected with the highest-order digital input end, and the output end of the digital comparator 1 is connected with the input end of the second inverter inx 2.
Resistor R is connected with reference voltage of resistor network and ground end in sequence 1 To R 64 Switch S 0 A first end of the resistor with even subscript is connected, and a switch end is connected with the digital output end of the digital comparator 1, and is switched
Connected to the odd-numbered resistor first end and openedThe switch end is connected with the digital output end of the digital comparator 1 after passing through the inverter inx2, and the switch S 1 And->
Respectively connected with each switch S 0 、/>
In this connection, S 5 、/>
Connecting signal output terminal V OUT 。
The rate adjusting circuit generates signal waveforms of different frequencies according to the clock signal and the signal value of the slew rate selecting end, and dynamically adjusts the slew rate of the analog voltage output value according to the signal value set by the slew rate selecting end. The digital comparison circuit is used for continuously converting the digital signal value, judging whether the data at the digital input end is equal to the data output by the counter in the digital comparison circuit, if the signals of the digital comparison circuit are all high-level representing conversion completion, outputting the data at the digital output end to the input end of the resistor network, and if the conversion is not completed, continuing to perform counting conversion. When the signals of the digital comparison circuit are all high level generations, the voltage value at the ith resistance joint of the resistance network is as follows:
wherein V is REF The output voltage value V of the analog output terminal is the reference voltage value OUT The size is determined based on the binary word of the selected switch.
The digital-to-analog converter can adjust the conversion rate of the chip output voltage during switching according to the working state of the chip, namely, according to the coding value of the conversion rate selection end, the conversion rate can reach 10mV/0.15us at the highest speed and 10mV/19.2us at the lowest speed, so that the time of soft start of the chip can be controlled, and the accurate and stable conversion of the analog voltage value of the output end is ensured. And the digital-to-analog converter adopts the realization form of a resistor network instead of an active operational amplifier, thereby being beneficial to saving the static power consumption of the circuit and being worthy of application and popularization.
Claims (8)
1. The digital-to-analog converter with adjustable voltage conversion rate comprises a rate adjusting circuit, a digital comparison circuit and a resistance network, wherein the rate adjusting circuit adjusts the set-up time of the digital-to-analog converter through a conversion rate selection end according to the requirement of analog output voltage conversion rate, the digital comparison circuit compares at least one bit of digital input end data with data output by a counter in the digital comparison circuit, and the resistance network converts digital output end data into corresponding analog voltage values;
the rate adjusting circuit is composed of a D trigger and a data selector, the clock signal of the rate adjusting circuit is connected with the clock signal of the first D trigger dff1, the data end D1 of the first data selector mux1, the data selecting end of the conversion rate selector mux1, the second data selector mux2 and the data selecting end of the third data selector mux3, the data input end of the first D trigger dff1 is connected with the reverse data output end of the first D trigger dff1, the data end D0 of the first data selector mux1, the data input end of the second D trigger dff2 is connected with the reverse data output end of the second D trigger dff2, the data input end of the third D trigger dff3 is connected with the reverse data output end D0 of the third data selector mux3, the data input end D0 of the fourth data selector mux2, the data input end of the fifth D trigger dff4 is connected with the reverse data output end D output end of the fourth D trigger dff4, the data input end of the fifth D trigger dff5 is connected with the reverse data output end D trigger dff6, the data input end of the third D trigger dff2 is connected with the data output end D3, the data input end of the third D trigger dff7, and the data input end of the third D trigger dff2 is connected with the data output end of the third D trigger dff 7.
2. The rate-of-voltage-conversion adjustable digital-to-analog converter of claim 1, wherein the clock signal output of the rate adjustment circuit is coupled to a digital input of a digital compare circuit, and wherein the digital output of the digital compare circuit is coupled to an input of a resistor network.
3. The voltage slew rate adjustable digital-to-analog converter of claim 1 or 2 where the rate adjustment circuit generates signal waveforms of different frequencies based on the clock signal and the signal values at the slew rate selection terminal and dynamically adjusts the slew rate of the analog voltage output value based on the signal values set at the slew rate selection terminal.
4. The digital-to-analog converter with adjustable voltage conversion rate according to claim 1, wherein the digital comparison circuit is composed of at least one exclusive-or gate, a nand gate, an inverter and a D flip-flop, the input end of the first inverter inx1 of the digital comparison circuit is connected with the forward output end of the first D flip-flop, the input end of the n-th nand gate, the output end of the first inverter inx1 is connected with the input end of the first exclusive-or gate xor1, the input end of the first D flip-flop is connected with the output end of the first exclusive-or gate xor1, the clock signal input end of the first D flip-flop is connected with the clock signal output end from the rate adjustment circuit, the reverse output end of the first D flip-flop is connected with the input end of the digital comparator 1, the other input end of the digital comparator 1 is connected with the most digital input end, the output end of the digital comparator 1 is connected with the input end of the second inverter inx2, and so on.
5. The digital-to-analog converter of claim 4, wherein said digital comparator circuit is configured to continuously convert the digital signal value to determine whether the digital input data is equal to the data output from the counter in the digital comparator circuit, and if the digital comparator circuit signals are all high, the digital output data is output to the input of the resistor network, and if not, the count conversion is continued.
6. The adjustable voltage slew rate digital-to-analog converter of claim 1 where the resistor network comprises at least one resistor and a switching tube for converting a six-bit digital signal to an analog signal voltage value corresponding to the digital signal.
7. The digital-to-analog converter with adjustable voltage conversion rate according to claim 6, wherein said resistor network reference voltage and ground are sequentially connected with a resistor R 1 To R 64 Switch S 0 A first end of the resistor with even subscript is connected, and a switch end is connected with the digital output end of the digital comparator 1, and is switched
A first end of a resistor with odd index is connected, a switch end is connected with a digital output end of the digital comparator 1 after passing through the inverter inx2, and a switch S 1 And->
Respectively connected with each switch S 0 、/>
In this connection, S 5 、/>
Connecting signal output terminal V OUT 。
8. The voltage slew rate adjustable digital to analog converter of claim 6 or 7 where the voltage value at the i-th resistor junction of the resistor network is:
wherein V is REF The output voltage value V of the analog output terminal is the reference voltage value OUT The size is determined based on the binary word of the selected switch.
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| TWI321403B (en) * | 2006-08-30 | 2010-03-01 | Novatek Microelectronics Corp | Overdrive digital-to-analog converter, source driver and method thereof |
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| US5748128A (en) * | 1995-05-15 | 1998-05-05 | Sgs-Thomson Microelectronics, S.R.L. | Reduced current quadratic digital/analog converter with improved settling-time |
| JP2004260603A (en) * | 2003-02-26 | 2004-09-16 | Sharp Corp | Digital/analog converter, display panel drive circuit using the same, and display device |
| CN101741389A (en) * | 2009-12-21 | 2010-06-16 | 西安电子科技大学 | Segmented current-steering digital-to-analog converter |
| CN104267228A (en) * | 2014-09-30 | 2015-01-07 | 中国电子科技集团公司第四十一研究所 | Circuit allowing trigger sensitivity of digital oscilloscope to be continuously adjustable |
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Effective date of registration: 20230407 Address after: Building 3, No.2528 Youyi Road, Guali Town, Xiaoshan District, Hangzhou City, Zhejiang Province, 311241 Applicant after: Hangzhou Shanger Semiconductor Co.,Ltd. Address before: B201, zero one square, Xi'an Software Park, 72 Keji 2nd Road, high tech Zone, Xi'an City, Shaanxi Province, 710000 Applicant before: Tuoer Microelectronics Co.,Ltd. |
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