CN104660261B - A kind of analog-digital commutator of adaptive quantizing - Google Patents
A kind of analog-digital commutator of adaptive quantizing Download PDFInfo
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Abstract
The present invention discloses a kind of analog-digital commutator of adaptive quantizing, and comparison result compared with feedback reference signal, is exported analog input signal to M shift register and division summing elements by comparing unit；The output result of comparing unit is clocked out storage, output M bit parallel data to adaptive quantizing arithmetic element by shift register；Adaptive quantizing arithmetic element determines initial quantization value according to the M bit parallel data of M shift register output, and initial quantization value is exported to division summing elements；Division summing elements carry out initial quantization value the result that cumulative or decrement operations obtain is exported to the output end to the input terminal of D/A conversion unit and analog-digital commutator except 2 operations in the 1st time to the M times comparison course of work of comparing unit；D/A conversion unit carries out digital-to-analogue conversion to the output result of division summing elements and exports to the negative input of comparing unit.
Description
Technical field
The present invention relates to field of signal processing, in particular to a kind of analog-digital commutator of adaptive quantizing
(Adaptive Quantized Analog-to-Digital Converter).
Background technique
For traditional Approach by inchmeal analog-digital conversion method using comparator input signal and reference signal difference, search is all
Possible quantization position is to obtain effective numeral output.Fig. 1 is successive approximation analog-digital converter in the related technology
Structure chart.For the output of digital quantization value each time in Fig. 1, comparator needs to carry out n times comparison, and N is numeral output
Number of bits.
After initialization conversion starts, simulation input is compared with the reference signal of feedback, according to the result of the comparison,
Using the numerical value of dichotomy adjustment feedback reference signal, compared next time.Each comparison result is sent into shift register
In the middle.After carrying out n times comparison, the value in shift register means that N digit of the input analog quantity after quantization
Word exports result.
Digital quantizer (Successive Approximation Register is simulated in traditional successive approximation
Analog-to-Digital Converter, SAR ADC) in, as shown in Figure 1, providing it when starting (START) 11 signal
Afterwards, sequential control circuit (TIMING) 9 provides sampling enable signal, is connected to sampling hold circuit (S/H) 2, simulation input letter
Number 1 will sample signal by sampling hold circuit 2.Sampling period is exactly the output of analog-digital converter digital signal
Period.The other end 5 of the positive input terminal 3 for being signally attached to comparator (COMPARATOR) 4 after sampling, comparator connects
Reference signal.The reference signal is provided by digital analog converter (DAC) 7, and when comparing for the first time, digital analog converter is given
Reference voltage signal out is 1/2 full width reference value, i.e. N-1 is 1, remaining the 0th to N-2 are 0.Comparator 4
Output result is given to control logic (CONTROL LOGIC) 6.N output is moved to right one by control logic, later by comparator
Output result be placed in N highest orders (Most Significant Bit, MSB), i.e., N-1.Control logic will be defeated
N bit digital quantity is connected to the input terminal of digital analog converter out.It the results change of digital analog converter and then carries out down
Primary comparison.The sampled signal of comparator input terminal 3 does not change, and 5 signal becomes 1/4 or 3/4 full width reference letter
Number.Comparator can export this comparison result, and control logic moves to right N output valves again, and the value of comparator is placed on
On the position N-2, and input signal of the N bit digital quantity as digital analog converter, i.e. reference voltage signal are exported, carried out next
Secondary comparison.The value of third time digital analog converter output may be 1/8,3/8,5/8,7/8 full width reference signal.So into
Row n times compare.Control logic can move to right n times, and the comparison result of n-th is put into the 0th above.When completion n times compare, when
Sequence circuit 9 can export the signal of completion (DONE) 10.N control logic output valves are exactly this analog-digital converter at this time
Output result.
In Fig. 1 conventional successive approaching simulation digital conversion method, the conversion rate of converter is FS, converts digit as N,
Then the internal quick clock for needing N*FS controls control logic circuit.Analog input signal is needed to sample and be kept simultaneously
Value when circuit remains sampling in the n times comparison procedure that a data export will increase circuit realization very big
Power consumption and circuit noise.
The n times that Approach by inchmeal analog-digital conversion method need compare just available output as a result, in this method needs
The high speed sampling clock in portion is completed.The internal clocking frequency domain of this converter being increased by, while increasing power loss.How
Reach the conversion time for improving similar successive approximation simulation digital switching device using less number of comparisons, reduces power
Loss, while the performance for not reducing converter is a problem in the urgent need to address.
Summary of the invention
The present invention provides a kind of analog-digital commutator of adaptive quantizing, to solve conventional successive approaching simulation number
The problem that number of comparisons is excessive in character conversion method, sampling clock is too fast, power loss is excessive.
In order to achieve the above objectives, it the present invention provides a kind of analog-digital commutator of adaptive quantizing, includes at least:
Comparing unit for analog input signal to be compared with feedback reference signal, and comparison result is exported
To M shift register and division summing elements, wherein feedback reference signal is the output of D/A conversion unit, digital mould
In the N bit digital quantity of the initial input of quasi- converter, N-1 are 1, and N-2 to the 0th are 0, and M, N are natural number, M
Less than N；
Shift register for storing the output result of comparing unit by clock sequencing, and exports M parallel-by-bit number
According to adaptive quantizing arithmetic element；
Adaptive quantizing arithmetic element, for determining initial quantization according to the M bit parallel data of M shift register output
Value, and initial quantization value is exported to division summing elements；
Division summing elements, in the 1st time to the M times of the comparing unit relatively course of work, to initial quantization value
It carries out except 2 operations, cumulative or decrement operations is carried out to except the quantized value after 2 operations according to the Sequential output result of comparing unit,
And the mould exported the result that cumulative or decrement operations obtain to the input terminal of D/A conversion unit and adaptive quantizing
The output end of quasi- digital switching device；
D/A conversion unit, the 2 system result of the position N for the output to division summing elements carry out digital simulation and turn
It changes, and the result after conversion is exported to the negative input of comparing unit, as feedback reference signal, wherein simulation numeral turns
The output for changing unit is 2 binary data of the position N.
Further, index step-length look-up table and quantization table, adaptive quantizing are preserved in adaptive quantizing arithmetic element
Arithmetic element searches corresponding output valve from index step-length look-up table according to the M bit parallel data of shift register output, and
According to the sum of the output valve and the step value in a upper period from the corresponding quantized value of quantization table acquisition.
Further, index step-length look-up table shared M-1 inputs, 2M-1The value of a optional output, wherein maximum value is 2(M-1)- 1, minimum value is -2(M-1)+1。
Further, the quantized value Yi of quantized value look-up table is determined according to the following formula:
Yi=2i*STEP, i=0,1,2,3 ... K
Wherein, STEP is the positive real number less than 1, and K is less than N；Yi maximum value is 2(N-1), minimum value 2M-1。
Further, in the l-th period, the output valve that division summing elements read adaptive quantizing unit is defeated as its
Enter, wherein L=n*M, n=0,1,2,3 ...；The L+1~M+L-1 period, adder accumulator is removed in each period to its input value
Move to right one operation, i.e., except 2 operations, using output result as the input of division summing elements described in next cycle
Value；Except adder accumulator repeats it in the operation in l-th period the M+L period.
Further, when the output of comparing unit is 1, division summing elements carry out tired the L~M+L-1 period
Add operation；When the output of comparing unit is 0, division summing elements carry out decrement operations the L~M+L-1 period, on the contrary
?.
Further, when analog input signal is greater than feedback reference signal, the output of comparing unit is 1；It is defeated when simulating
When entering signal less than or equal to feedback reference signal, the output of comparing unit is 0, and vice versa.
Further, the reference voltage of D/A conversion unit is fixed level voltage, and is not become at any time
Change.
Further, 1 of comparing unit is exported the output for being selected as analog-digital commutator.
Further, when analog-digital commutator is set as 1 bit comparison unit output result, external connection is just like right
It is required that the adaptive quantizing arithmetic element and division summing elements of any one of 1-8, to generate N digit word output signal, as
The output of the analog-digital commutator of adaptive quantizing.
When converting initial using the comparison result of feedback reference signal and real simulation input signal, control removes the present invention
Method summing elements are adjusted feedback voltage signal, and after M adjustment, using adaptive quantizing algorithm, amendment is anti-
It presents reference signal and improves the accuracy of each feedback reference signal to be more nearly true analog input signal, thus
In the case where the performance of guarantee output signal is constant, reduce the number of comparisons of input analog signal and feedback reference signal,
Clock frequency is reduced, conversion time is reduced, reduces power loss, solves and is converted in conventional successive approaching simulation number
The problem that number of comparisons is excessive in method, sampling clock is too fast, power loss is excessive.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is conventional successive approximation analog-digital converter structural block diagram in the related technology；
Fig. 2 is the analog-digital converter structural block diagram based on adaptive quantizing of one embodiment of the invention；
Fig. 3 is the shift register structure block diagram of one embodiment of the invention；
The adaptive quantizing arithmetic element structural schematic diagram of Fig. 4 one embodiment of the invention；
Fig. 5 is the division multi-accumulator structure block diagram of one embodiment of the invention；
Fig. 6 is the pass of quantized value and index value in the adaptive quantizing method based on look-up table of one embodiment of the invention
It is schematic diagram.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under that premise of not paying creative labor
Embodiment shall fall within the protection scope of the present invention.
Fig. 2 is the analog-digital commutator structural schematic diagram of the adaptive quantizing of one embodiment of the invention；As schemed
Show, which includes at least:
Comparing unit 4, the feedback for being inputted by the analog input signal inputted from positive input terminal 31 and from negative input end 5
Reference signal is compared, and comparison result is exported to M shift register 13 and division summing elements 15, wherein feeding back
Reference signal is the output of D/A conversion unit (DAC) 7, the N bit digital quantity of the initial input of digital analog converter 7
In, N-1 are 1, and N-2 to the 0th are 0, and M, N are natural number, and M is less than N；
When analog input signal is greater than feedback reference signal, the output of comparing unit is 1；When analog input signal is less than
When equal to feedback reference signal, the output of comparing unit is 0.
Shift register 13 for storing the output result of comparing unit 4 by clock sequencing, and exports M simultaneously
Row data are to adaptive quantizing arithmetic element 14；
Fig. 3 is the shift register structure block diagram of one embodiment of the invention；As shown, in the output of shift register
End 18 can be obtained by M bit comparator parallel output as a result, R0~Rm-1.This M result is connected to adaptive quantizer 14 and works as
In.
Adaptive quantizing arithmetic element 14, the M bit parallel data for being exported according to M shift register 13 determine initial
Quantized value, and initial quantization value is exported to division summing elements 15；
Fig. 4 is the adaptive quantizing arithmetic element schematic diagram of one embodiment of the invention；As shown, implementing
When, index step-length look-up table 19 and quantization table 20 can be preserved in adaptive quantizing arithmetic element 14, M quantized results are led to
It crosses index step-length look-up table (INDEX STEP LOOK UP TABLE) 19 and obtains the step value of quantized value, according to this step value
New quantized value is obtained in quantization table (QUANTIZER TABLE) 20.This new quantized value will tire out as division next time
Add the initial quantization value of unit 15.
Wherein, index step-length look-up table shared M-1 inputs, 2M-1A output.The maximum value of index value is 2M-1- 1, it is minimum
Value is -2M-1+1.The quantized value Yi of quantized value look-up table is determined according to the following formula:
Yi=2i*STEP, i=0,1,2,3 ... K
Wherein, STEP is less than 1 positive real number, and K is less than N.The maximum value of Yi is 2N-1, minimum value 2M-1。
Step-length look-up table 19 is indexed as N=16, M=4 and quantized value table 20 is as shown in Table 1 and Table 2.But the value of N, M are not
It is only limitted to this.As long as meeting N, M is positive integer, and M < N.
Table 1
| Index M-1 input values (M=4) of step-length look-up table | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
| Index step-length look-up table output valve | -1 | -1 | -1 | -1 | 2 | 3 | 4 | 6 |
Table 2
| 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 16 | 17 |
| 19 | 21 | 23 | 25 | 28 | 31 | 34 | 37 | 41 | 45 |
| 50 | 55 | 60 | 66 | 73 | 80 | 88 | 97 | 107 | 117 |
| 130 | 143 | 157 | 173 | 190 | 209 | 230 | 253 | 279 | 307 |
| 337 | 371 | 408 | 449 | 494 | 544 | 598 | 658 | 724 | 796 |
| 876 | 963 | 1060 | 1166 | 1282 | 1411 | 1552 | 1707 | 1878 | 2066 |
| 2272 | 2499 | 2749 | 3024 | 3327 | 3660 | 4026 | 4428 | 4871 | 5358 |
| 5894 | 6484 | 7132 | 7854 | 8630 | 9493 | 10442 | 11487 | 12635 | 13899 |
| 15289 | 16818 | 18500 | 20350 | 22385 | 24623 | 27086 | 29794 | 32767 |
Quantized value 25 in quantization table meets Yi=2i*STEP, i=1,2,3 ... K.All quantized values are using Yi as logarithm
Approximate log relationship is shown as in coordinate system, as shown in Figure 6.
After again passing by M conversion, the value 18 of new shift register is obtained.The value 18 of this shift register will again
The secondary step value 19 that quantized value next time is calculated in adaptive quantizer 14 and this step value are corresponding in quantization table
Quantized value 20.Repeatedly convert.
Division summing elements 15, in the 1st time to the M times comparison course of work of comparing unit 4, division to be cumulative single
Member 15 constantly move to right to quantized value 1 operation according to the output of comparator 4, that is, removes 2 operation, according to than
Sequential output result compared with unit 4 carries out cumulative or decrement operations to except the quantized value after 2 operations, and will cumulative or decrement operations
Obtained result exports the output end 8 to the input terminal of D/A conversion unit 7 and analog-digital commutator；
In the l-th period, the output valve that division summing elements read adaptive quantizing unit is inputted as it, wherein L=n*
M, n=0,1,2,3 ...；The L+1~M+L-1 period, except adder accumulator carries out its input value in each period to move to right one
Operation；Except adder accumulator repeats it in the operation in l-th period the M+L period.
When the output of comparing unit is 1, accumulation operations that division summing elements are carried out the L~M+L-1 period；When
When the output of comparing unit is 0, division summing elements carry out decrement operations the L~M+L-1 period.
Fig. 5 is the division summing elements structural schematic diagram of one embodiment of the invention；As shown, quantized value selects 1 by 2
Selector 24 select the input value of accumulator 23.Selection adaptive quantizing value input be the n-th * M period (n=1,
2 ....).At the 1st to the M-1 period, except adder accumulator 15 carries out except 2 operations 22 adaptive quantizing value.Trigger 17
The calculated result of a upper clock cycle was saved in next rising edge clock, and is exported as summing elements operation next time
Input value.The R of shift register0~Rm-1Output end 21 is used to select the operation behavior of accumulator 23, in the m-th period, R0It is 1
When cumulative, R0Successively decrease when being 0, the M+1 period, R1It adds up when being 1, R1Successively decrease when being 0, and so on to the 2M-1 week
Phase.Input value of the output valve of accumulator 23 as digital analog converter 7, is converted into analog signal, carries out in comparator 4
Comparison next time.
D/A conversion unit 7 carries out digital-to-analogue conversion for the output result to division summing elements 15, and will
Result after conversion is exported to the negative input 5 of comparing unit 4, as feedback reference signal.
Wherein, in specific implementation, the reference voltage of D/A conversion unit 7 is fixed level voltage, and
It does not change over time.When converting beginning, in the N bit digital quantity of the initial input of D/A conversion unit, N-1 are 1,
N-2 to the 0th are 0.
The data output of analog-digital commutator is the input letter of the position N of D/A conversion unit in above-described embodiment
Numbers 8, this signal and analog input signal are consistent in long-term comparison procedure.But Analog-digital Converter in the embodiment of the present invention
The data output of device is not limited to that, as shown in Figure 1, the output 12 of comparator can also be used as this conversion equipment
Data output.Shift register and adaptive quantizer can be used to restore conversion signal for external reception device, to generate N
Digital output signal.
In conclusion above-described embodiment utilizes the ratio of feedback reference signal and real simulation input signal when converting initial
Feedback voltage signal is adjusted compared with as a result, controlling division summing elements, after M adjustment, utilizes adaptive quantity
Change algorithm, corrects feedback reference signal to be more nearly true analog input signal and improve each feedback reference signal
Accuracy, thus guarantee output signal performance it is constant in the case where, reduce input analog signal and feedback reference believe
Number number of comparisons, reduce clock frequency, reduce conversion time, reduce power loss, solve and forced in conventional successive
The problem that number of comparisons is excessive, sampling clock is too fast, power loss is excessive in nearly analog-digital conversion method.
Those of ordinary skill in the art will appreciate that: attached drawing is the schematic diagram of one embodiment, module in attached drawing or
Process is not necessarily implemented necessary to the present invention.
Those of ordinary skill in the art will appreciate that: the module in device in embodiment can describe to divide according to embodiment
It is distributed in the device of embodiment, corresponding change can also be carried out and be located in one or more devices different from the present embodiment.On
The module for stating embodiment can be merged into a module, can also be further split into multiple submodule.
Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
Present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: it still may be used
To modify to technical solution documented by previous embodiment or equivalent replacement of some of the technical features；And
These are modified or replaceed, the spirit and model of technical solution of the embodiment of the present invention that it does not separate the essence of the corresponding technical solution
It encloses.
Claims (7)
1. a kind of analog-digital commutator of adaptive quantizing, which is characterized in that include at least:
Comparing unit is exported for analog input signal to be compared with feedback reference signal, and by comparison result to M
Shift register and division summing elements, wherein the feedback reference signal is the output of D/A conversion unit, the number
In the N bit digital quantity of the initial input of word analog converter, N-1 are 1, and N-2 to the 0th are 0, and M, N are nature
Number, M are less than N；
The shift register for storing the output result of the comparing unit by clock sequencing, and exports M simultaneously
Row data are to adaptive quantizing arithmetic element；
The adaptive quantizing arithmetic element determines initial for the M bit parallel data according to the M shift register outputs
Quantized value, and the initial quantization value is exported to the division summing elements；
The division summing elements, in the 1st time to the M times of the comparing unit relatively course of work, to it is described just
Beginning quantized value is carried out except 2 operations, is added up according to the Sequential output result of the comparing unit to except the quantized value after 2 operations
Or decrement operations, and the result that cumulative or decrement operations obtain exported to the input terminal of the D/A conversion unit and
The output end of the analog-digital commutator of the adaptive quantizing；
The D/A conversion unit, the 2 system result of the position N for the output to the division summing elements carry out digital mould
Quasi- conversion, and the result after conversion is exported to the negative input of the comparing unit, as the feedback reference signal,
Described in the output of analog digital converting unit of adaptive quantizing be 2 binary data of the position N；
Index step-length look-up table and quantization table, the adaptive quantizing operation list are preserved in the adaptive quantizing arithmetic element
Member searches corresponding output valve from the index step-length look-up table according to the M bit parallel data of the shift register output,
And according to the sum of the output valve and the step value in a upper period from the corresponding quantized value of the quantization table acquisition；
The index step-length look-up table shared M-1 inputs, 2M-1The value of a optional output, wherein maximum value is 2(M-1)- 1, it is minimum
Value is -2(M-1)+1；
The quantized value Yi of the quantized value look-up table is determined according to the following formula:
Yi=2i*STEP, i=0,1,2,3 ... K
Wherein, K is less than N；STEP is the positive real number less than 1；Yi maximum value is 2(N-1), minimum value 2M-1。
2. analog-digital commutator according to claim 1, which is characterized in that in the l-th period, the division is cumulative
The output valve that unit reads adaptive quantizing unit is inputted as it, wherein L=n*M, n=0,1, and 2,3 ...；In L+1~M+
L-1 period, the operation for move to right to its input value one in each period except adder accumulator, i.e., except 2 operations, defeated
Input value of the result as division summing elements described in next cycle out；The adder accumulator that removes is repeated the M+L period
Its operation in the l-th period.
3. analog-digital commutator according to claim 1, which is characterized in that when the output of the comparing unit is 1
When, accumulation operations that the division summing elements are carried out the L~M+L-1 period；When the output of the comparing unit is 0
When, the division summing elements carry out decrement operations the L~M+L-1 period.
4. analog-digital commutator according to claim 1, which is characterized in that when the analog input signal is greater than institute
When stating feedback reference signal, the output of the comparing unit is 1；When the analog input signal is less than or equal to the feedback reference
When signal, the output of the comparing unit is 0.
5. analog-digital commutator according to claim 1, which is characterized in that the base of the D/A conversion unit
Quasi- reference voltage is fixed level voltage, and is not changed over time.
6. analog-digital commutator according to claim 1, which is characterized in that by 1 output of the comparing unit
It is selected as the output of the analog-digital commutator.
7. analog-digital commutator according to claim 6, which is characterized in that the analog-digital commutator setting
When exporting result for 1 bit comparison unit, external connection is just like adaptive quantizing operation list of any of claims 1-6
Member and division summing elements, to generate N digit word output signal, analog-digital commutator as the adaptive quantizing
Output.
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| CN105653241B (en) * | 2016-01-04 | 2018-06-26 | 湖南工业大学 | Seek the device of ratio value between two input voltages |
| CN106656191A (en) * | 2016-09-22 | 2017-05-10 | 天津大学 | Successive approximation type ADC adjusting reference voltage adaptively |
| US9859910B1 (en) * | 2017-02-13 | 2018-01-02 | SK Hynix Inc. | Analog to digital converter and semiconductor apparatus using the same |
| CN109379082B (en) * | 2018-09-29 | 2023-12-26 | 长沙学院 | Successive approximation analog-to-digital converter |
| CN111384857B (en) | 2018-12-29 | 2022-05-06 | 东南大学 | Flyback converter and output voltage obtaining method and device thereof |
| CN111525928B (en) * | 2020-05-28 | 2023-06-27 | 南开大学深圳研究院 | Analog-digital converter for quantizing two inputs and quantizing method |
| CN112817255B (en) * | 2020-12-31 | 2022-03-18 | 深圳贝特莱电子科技股份有限公司 | Touch data denoising processing method |
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