JP2004253582A - Method and apparatus for driving semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable method and apparatus for driving a voltage-driven semiconductor device comprising a voltage-driven semiconductor element which reduces a time-varying rate of a current at the time of switching, reduces switching loss, and has a considerably low risk of malfunction and breakage. <P>SOLUTION: A control unit comprises a timing determining device for determining timing for switching driving circuits, and a logic circuit for switching between a first driving circuit and a second driving circuit according to the outputs from the timing determining device. In the control unit, the timing determining device detects a collector voltage of an IGBT and determines the timing for switching the driving circuits, and the switching timing is controlled so that the switching is carried out after expiration of a mirror period of the IGBT. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a driving method thereof, and particularly to a voltage-driven semiconductor device and a driving method thereof.
[0002]
[Prior art]
A voltage-driven semiconductor element such as an insulated gate bipolar transistor (hereinafter, referred to as an IGBT) or a metal oxide semiconductor gate turn-off transistor (MOSGTO) is smaller than a current-driven semiconductor element. Due to the simplicity of the drive circuit, it is rapidly spreading to fields such as power supplies and inverters. The driving method is conventionally fixed and controlled by focusing on the gate resistance. However, as disclosed in, for example, Japanese Patent Application Laid-Open No. 9-46201, the drive method reduces the turn-on loss and the time change rate of the main current at the time of turn-on. For the purpose of reducing di / dt, there has been proposed a method of controlling by switching to a resistor having an appropriate value in various modes of the turn-on operation.
[0003]
FIG. 12 shows an example of a conventional drive circuit. In the figure, only the IGBT to be driven is displayed, and the load connected to the IGBT, the configuration related to turn-off control, and the configuration of other IGBT devices are omitted.
[0004]
The driving device of this conventional example drives the IGBT 1 in accordance with the ON signal Vin applied to the input terminal 7, and connects the driving circuit 2 and the driving circuit 3 with the driving circuit 2, the driving circuit 3 and the gate of the IGBT 1, respectively. It has gate resistors 4 and 5, a gate power supply VGE, and a control device 6 for controlling the operation of each drive circuit. The control device 6 includes a timing determination device 8 that determines a timing for switching the drive circuit, and a logic circuit that switches between the drive circuit 2 and the drive circuit 3 according to the output of the timing determination device 8. The resistance value Rb of the gate resistor 5 is set smaller than the resistance value Ra of the gate resistor 4.
[0005]
The timing determining device 8 in the conventional example detects the collector voltage of the IGBT 1 and determines the timing for switching between the driving circuit 2 and the driving circuit 3. The configuration of the timing determination device 8 in this conventional example is such that the base is connected to a connection point of the Zener diode 13, the resistor 14, and the resistor 15 connected in series to the collector of the IGBT 1 and the resistor 14 and the resistor 15, respectively. It comprises a transistor 16 and a pnp transistor 17. The Zener diode 13 is selected to have a breakdown voltage higher than the collector-emitter voltage Vce (res) during the mirror period in which the gate voltage during the turn-on operation is constant due to the collector-gate capacitance of the IGBT 1.
[0006]
FIG. 13 shows waveforms at various parts of the conventional example shown in FIG. When the gate-on signal shown in FIG. 13A is input from the input terminal 7, the collector voltage of the IGBT 1 drops, but when the collector voltage is higher than the Zener voltage of the Zener diode 13 at the beginning of turn-on, the Zener The diode 13 conducts and current flows through the resistors 14 and 15. At this time, the npn transistor 16 is turned on by a voltage drop generated in the resistor 15, and a high level is output from the timing determination device 8.
[0007]
During the period when this output voltage is at the high level and the on signal is being input to the input terminal 7 at the high level, the off signal is transmitted to the npn transistor Q3 by the NAND gate 10, and the drive circuit 2 operates. As a result, a charging current is supplied to the gate of the IGBT1 from the Q1 of the drive circuit 2 through the gate resistor 4 having the resistance value Ra.
[0008]
Next, when the gate capacitance of the IGBT 1 is charged and the collector voltage drops below the Zener voltage of the Zener diode 13, no current flows through the Zener diode 13. Then, the pnp transistor 17 is turned on, and the output from the timing determination device 8 becomes Low level.
[0009]
During a period when this output is at a low level and a high-level ON signal is applied to the input terminal 7, the npn transistor Q3 is turned on by the NAND gate 10, the driving circuit 2 is stopped, and the npn transistor Q6 is turned off by the NAND gate 11. The signal is output, and the drive circuit 3 operates. Therefore, as shown in FIG. 13D, the charging current is supplied to the gate of the IGBT 1 through the gate resistor 5 having a resistance value Rb smaller than the gate resistance 4 having the resistance value Ra.
[0010]
Here, since the Zener voltage of the Zener diode 13 is a breakdown voltage higher than the collector-emitter voltage Vce (res) during the mirror period, the switching timing t1 is the mirror period during which the gate voltage of the IGBT 1 becomes substantially constant during the turn-on operation. That is, the feature is set during the period t3 in FIG. 13 (5), and can be expressed as td + t2 <t1 <td + t2 + t3.
[0011]
[Patent Document 1]
JP-A-9-46201
[0012]
[Problems to be solved by the invention]
The mirror phenomenon of the IGBT differs for each element, and the gate voltage during the mirror period and the length of the mirror period vary greatly for each element. In the conventional example, the timing at which the gate resistance is switched is characterized by the mirror period, but the IGBT may not have reached the stable ON state at that timing.
[0013]
When the gate resistance is switched to a small resistance value before reaching a stable ON state, the rise of the main current of the IGBT becomes steep as shown in FIG. The jump voltage (L × di / dt) generated by the time change of the current flowing through the floating inductance L of the IGBT circuit also increases. In the conventional drive circuit, there is a problem that an element or a device is destroyed by the jumping voltage or a malfunction occurs due to noise generated by the jumping voltage.
[0014]
[Means for Solving the Problems]
In order to achieve the above object, a method of driving a voltage-driven semiconductor device according to the present invention includes a first period in which a gate voltage rises and / or falls with time after a control signal is applied to a gate electrode; And a drive voltage applied to the gate electrode after the first and second periods have elapsed is a drive voltage applied during the first and second periods. It is characterized in that it is lower than the above.
[0015]
This is characterized in that the drive voltage applied to the gate electrode is changed after the initial state in which the control signal is applied to the gate electrode ends.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
In order to achieve the above object, a method of driving a voltage-driven semiconductor device according to an embodiment of the present invention is characterized in that an initial state after a control signal is applied to a gate electrode is such that a gate voltage rises and / or falls with time. And a second period during which the gate voltage is substantially constant after the first period. The first electrode on the high potential side and the second electrode on the low potential side for allowing the main current to flow are included. In a method for driving a semiconductor device including a power semiconductor element having an electrode and a gate electrode for controlling a main current, a driving voltage applied to the gate electrode in a third period including all initial states is controlled by the driving voltage applied to the gate electrode. The drive voltage applied to the gate is made lower in the fourth period following the third period, and the drive voltage applied to the gate electrode is changed after the initial state ends.
[0017]
In the method of driving the voltage-driven semiconductor device according to the embodiment of the present invention, the initial state after the control signal is applied to the gate electrode includes a first period in which the gate voltage rises and / or falls with time and the first period. A first electrode on the high potential side and a second electrode on the low potential side for flowing the main current, and a main current controlled, including at least a second period in which the gate voltage is substantially constant following the period. A semiconductor device provided with a power semiconductor element having a gate electrode for driving the semiconductor device, wherein a predetermined voltage is set as a drive voltage during a third period through a first gate resistor having a first resistance value. Applying a predetermined driving voltage to the gate electrode through a second resistor having a second resistance value smaller than the first resistance value during a fourth period; Voltage and From the third period in which the predetermined voltage generated by applying the predetermined voltage to the gate electrode through the first gate resistor having the first resistance value, the predetermined drive voltage is changed to a third drive voltage having a resistance value smaller than the first resistance value. In the fourth period in which the voltage is applied to the gate electrode through the second resistor having the resistance value of 2, the voltage is changed after the initial state is completed.
[0018]
The driving method of the voltage-driven semiconductor device according to the embodiment of the present invention includes a fifth period in which the main current rises and / or falls with time after the control signal is applied to the gate electrode, and a main period after the fifth period. A method for driving a power semiconductor device including at least a sixth period until a current falls and / or rises to reach a stable state, wherein the gate electrode is provided in a seventh period including all the sixth periods. The drive voltage applied to the gate electrode is made lower than the drive voltage applied to the gate in the eighth period following the seventh period, and the drive voltage applied to the gate electrode is changed after the initial state ends. .
[0019]
The driving method of the voltage-driven semiconductor device according to the embodiment of the present invention includes a fifth period in which the main current rises and / or falls with time after the control signal is applied to the gate electrode, and a main period after the fifth period. In the method for driving a power semiconductor device, at least including a sixth period until the current falls and / or increases to reach a stable state, a predetermined voltage as a driving voltage is changed to a second voltage during the seventh period. Applying a predetermined drive voltage to the gate electrode through a first gate resistor having a resistance value of 1 and a second drive voltage having a second resistance value smaller than the first resistance value during an eighth period. From a seventh period in which a predetermined voltage as a drive voltage is applied to the gate electrode through a first gate resistor having a first resistance value. The eighth period to be applied to the gate electrode through a second resistor having a second resistance value smaller resistance value than the first resistance value is varied after the period of the fifth has been completed.
[0020]
A method for driving a voltage-driven semiconductor device according to an embodiment of the present invention is directed to a first and second drive circuit for generating a drive voltage in a semiconductor device drive device that drives by applying a drive voltage to a gate electrode of the semiconductor device. A first gate resistance connecting the first drive circuit and the gate electrode; and a second resistance value smaller than the resistance value of the first gate resistance connecting the second drive circuit and the gate electrode. The first drive circuit is first operated according to the second gate resistance and the input control signal, and the timing for switching the drive circuit to be operated is determined. A control circuit for stopping the operation and starting the operation of the second drive circuit, the control circuit having a timing determination device for determining a timing for switching from the third period to the fourth period. .
[0021]
A method for driving a voltage-driven semiconductor device according to an embodiment of the present invention is directed to a first and second drive circuit for generating a drive voltage in a semiconductor device drive device that drives by applying a drive voltage to a gate electrode of the semiconductor device. And a second resistance value smaller than a resistance value of a first gate resistance connecting the first drive circuit and the gate electrode, and a first gate resistance connecting the second drive circuit and the gate electrode. After the first drive circuit is first operated according to the second gate resistor having the following and the input ON signal, the timing is determined, and the operation of the second drive circuit is started according to the timing. And a control circuit, the control circuit including a timing determination device that determines a timing for activating the second drive circuit in the fourth period.
[0022]
The timing determination device includes a delay circuit that delays by a set period including an initial state including first and second periods after the input ON signal is input, and determines a timing when the delayed signal is output. And
[0023]
Alternatively, the timing determination device detects a potential of the first electrode of the semiconductor element and includes a determination circuit that determines whether the detected potential of the first electrode is equal to or lower than a predetermined reference voltage value and / or higher. The point in time when the first potential of the semiconductor element detected as a result of the determination becomes equal to or less than a predetermined voltage value and / or equal to or more than a predetermined voltage value.
[0024]
Alternatively, the timing determination device includes a gate voltage determination circuit that detects a gate voltage of the semiconductor element and determines whether the detected gate voltage is equal to or more than and / or equal to or less than a predetermined reference voltage value. The timing at which the detected gate voltage becomes equal to or higher than a predetermined voltage value is set as timing.
[0025]
Alternatively, the timing determination device detects any one of a main current of the semiconductor element and a current that changes in accordance with the amount of the main current, and a detected current value is equal to or more than a predetermined reference current value and / or Alternatively, a current determination circuit is provided for determining whether the current value is equal to or less than a predetermined value.
[0026]
Alternatively, the timing determination device has a timer circuit that measures only a predetermined time from various detection times, and sets a timing at which an output is output from the timer circuit after a predetermined time has elapsed from the various detection times.
[0027]
Alternatively, the timing determination device has a filter circuit that detects that the detection is continuously performed for a predetermined time from various detection times, and an output is output from the filter circuit after a predetermined time has elapsed from the various detection times. The point in time is the timing.
[0028]
Alternatively, it has a function of making a reference value variable in various determination circuits included in the timing determination device.
[0029]
According to the driving device and the method according to the above-described embodiment, since the mode switching timing is set after the mirror period is completely completed, the mode is not switched before the main element reaches a stable ON state, It is possible to obtain a highly reliable drive circuit free from the risk of element destruction and device destruction due to a jumping voltage generated due to a sudden current change that has occurred in conventional devices and the problem of malfunction.
[0030]
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0031]
FIG. 1 shows a first embodiment of the present invention. In the figure, only the IGBT to be driven is displayed, and the load connected to the IGBT, the configuration related to turn-off control, and the configuration of other IGBT devices are omitted.
[0032]
The drive device of this embodiment drives the IGBT 1 in accordance with the ON signal Vin applied to the input terminal 7, and connects the drive circuits 2 and 3, the drive circuits 2, the drive circuit 3, and the gate of the IGBT 1, respectively. It has resistors 4 and 5, a power supply for gate + V, and a control device 6 for controlling the operation of each drive circuit. The control device 6 includes a timing determination device 8 that determines a timing for switching the drive circuit, and a logic circuit that switches between the drive circuit 2 and the drive circuit 3 according to the output of the timing determination device 8. The resistance value Rb of the gate resistor 5 is set smaller than the resistance value Ra of the gate resistor 4. Further, in this embodiment, the drive circuit is constituted by a pMOS transistor, but any other device having a switch function may be used.
[0033]
The timing determining device 8 in the present embodiment detects the collector voltage of the IGBT 1 and determines the timing for switching between the driving circuit 2 and the driving circuit 3.
[0034]
The configuration of the timing determination device 8 in the present embodiment is such that the base is connected to a connection point between the Zener diode 13, the resistor 14, the resistor 15 and the resistor 14 and the resistor 15 connected in series to the collector of the IGBT 1. It comprises a transistor 16, a pnp transistor 17, and a timer circuit. The Zener diode 13 has a breakdown voltage lower than the collector-emitter voltage Vce (res) at the end of the mirror period in which the gate voltage during the turn-on operation becomes constant due to the collector-gate capacitance of the IGBT 1. Things are selected. As a result, the drive circuit is switched after the mirror period ends.
[0035]
FIG. 2 shows waveforms at various points in the embodiment shown in FIG. When the gate-on signal Vin shown in FIG. 2A is input from the input terminal 7, the collector voltage of the IGBT 1 drops, but when the collector voltage is higher than the Zener voltage of the Zener diode 13 at the initial stage of turn-on, The Zener diode 13 conducts, and a current flows through the resistors 14 and 15. At this time, the npn transistor 16 is turned on by a voltage drop generated in the resistor 15, and a high level is output from the timing determination device 8.
[0036]
During a period in which this output voltage is at a high level and a high-level on signal Vin is being input to the input terminal 7, the on signal is transmitted to the pMOS transistor Sa by the NAND gate 10 and the drive circuit 2 operates. As a result, a current is supplied from the drive circuit 2 to the gate of the IGBT 1 through the gate resistor 4 having the resistance value Ra.
[0037]
Next, when the gate capacitance of the IGBT 1 is charged and the collector voltage drops below the Zener voltage of the Zener diode 13, no current flows through the Zener diode 13. Then, the pnp transistor 17 is turned on, and the output from the timing determination device 8 becomes Low level.
[0038]
During a period in which this output is Low level and a High level ON signal Vin is applied to the input terminal 7, an OFF signal is input to the pMOS transistor Sa by the NAND gate 10, the drive circuit 2 is stopped, and the pMOS transistor is An ON signal is output to Sb, and the drive circuit 3 operates. Therefore, as shown in FIG. 2D, a current is supplied to the gate of the IGBT 1 through the gate resistor 5 having a smaller resistance value Rb than the gate resistance 4 having the resistance value Ra.
[0039]
Here, since the Zener voltage of the Zener diode 13 has a characteristic lower than the collector-emitter voltage Vce (res) at the end of the mirror period, the switching timing is the mirror period during which the gate voltage of the IGBT 1 becomes substantially constant during the turn-on operation. That is, it is characterized in that it is set after the period t3 in FIG. 2 (5) ends.
[0040]
The timing of this switching is different from that set during the mirror period t3 shown in FIG. 13 (5) in the conventional example, as shown in the waveforms in the respective parts of this embodiment in FIG. 1 shown in FIG. 2 (5). It is set after the mirror period t3 has completely ended and the IGBT has reached a stable ON state.
[0041]
At the end of the mirror period, the IGBT 1 is in a stable ON state, so that there is no danger of destruction or malfunction caused by a sudden change in the main current due to the switching of the drive circuit during the turn-on operation as in the prior art. The driving device can be significantly reduced and a highly reliable driving device can be provided.
[0042]
Further, the addition of the timer circuit 9 allows the drive circuit to be switched after a predetermined time t4 has elapsed from the detection of the timing as shown in FIG. The configuration is more reliable after the end of the mirror period t3. The timer circuit 9 may be constituted by an existing technology, and may be a delay circuit or the like for delaying the output by the time t4.
[0043]
When the timer circuit 9 detects that the detection signal is continuously output for a predetermined time t4 after detecting the timing, and then shifts to a subsequent operation, the reliability is further improved. High configuration. In this configuration, when a detection signal is instantaneously output due to noise or the like, the operation does not shift to a subsequent stage, so that a filter function is provided, and the risk of malfunction or destruction can be significantly reduced. .
[0044]
Further, in the present embodiment, each of the drive circuits 2 and 3 is constituted by a pMOS transistor, but any other components having the same switch function may be employed. Further, in the present embodiment, an example in which an IGBT is used as a main element is used. However, the effects of applying the present invention can be obtained in exactly the same manner for other voltage-controlled semiconductor elements.
[0045]
FIG. 3 shows a control method that does not stop the driving circuit 2 that has been operating first after switching the driving circuit. According to this control method, the effective gate resistance value of the IGBT 1 is switched from Ra alone to the parallel connection resistance of Ra and Rb as shown in FIG. 3 (4), and the same effect is obtained. In this case, since a circuit configuration for stopping Sa is not required, the control device in FIG. 1 can have, for example, the configuration illustrated in FIG. That is, the number of components can be reduced, and in the case of an IC, the chip area can be reduced.
[0046]
Next, a second embodiment of the present invention will be described in detail with reference to FIG. In this embodiment, the gate voltage of the IGBT 1 is detected to control the operation timing of the drive circuits 2 and 3, and the control is executed based on the gate voltage.
[0047]
As shown in FIG. 5, the driving device of this embodiment has driving circuits 2 and 3 having the same configuration as that of the first embodiment, and gate resistors 4 and 5 connecting the driving circuits 2 and 3 and the gate of the IGBT 1. And a control device 6 for controlling the operation timing of the drive circuits 2 and 3. Here, it is assumed that the resistance value Ra of the gate resistor 4 is larger than the resistance value Rb of the gate resistor 5 as in the first embodiment. Further, the control device 6 includes a timing determination device 8 that determines the timing of switching the drive circuit, and a logic circuit that switches between the drive circuit 2 and the drive circuit 3 according to the output of the timing determination device 8. In the present embodiment, as an example of the logic circuit, a NAND gate 20 which receives the output signal of the timing determination device 8 via the inverter 22 and the input signal Vin as input and sends the output to the drive circuit 2, And a NAND gate 21 that receives an output signal and an input signal Vin as inputs and sends an output to the drive circuit 3.
[0048]
The timing determining device 8 in the present embodiment detects the gate voltage of the IGBT 1 and determines the timing for switching between the driving circuit 2 and the driving circuit 3. The configuration of the timing determination device 8 in the present embodiment includes a comparator 23 that compares the gate voltage of the IGBT 1 with a predetermined reference voltage Vref24 and the timer circuit 9.
[0049]
Next, the operation of this embodiment will be described. While the ON signal Vin is input to the input terminal 7 and the gate voltage of the IGBT 1 is lower than the reference voltage Vref, the output of the comparator 23 is at the low level. Therefore, an ON signal is output from the NAND gate 20 to the gate of the pMOS transistor Sa of the drive circuit 2 to operate the drive circuit 2, and as a result, a gate current is supplied to the IGBT 1 through the gate resistor 4. Thereafter, when the gate voltage of the IGBT 1 rises and exceeds a predetermined reference voltage Vref of the comparator 23, the output of the comparator 23 goes high, the output of the NAND gate 20 goes high and the drive circuit 2 stops, The output of the NAND gate 21 becomes Low level, the drive circuit 3 operates, and the effective gate resistance of the IGBT 1 is switched from the large resistance value Ra to the small resistance value Rb.
[0050]
Here, the reference voltage Vref of the comparator 23 is set higher than the gate voltage in the mirror period. As a result, the drive circuit switching timing is set after the mirror period ends, and the same operation as in the first embodiment of the present invention shown in FIG. 2 is performed.
[0051]
Therefore, as in the first embodiment, when the mirror period ends, the IGBT is in a stable ON state, so that the drive circuit switches during the turn-on operation and the main current changes abruptly as in the conventional case. The danger of destruction or malfunction caused by this can be significantly reduced, and a highly reliable drive device can be provided.
[0052]
Further, the addition of the timer circuit 9 allows the drive circuit to be switched after a predetermined time t4 has elapsed from the detection of the timing as shown in FIG. The configuration is highly reliable after the mirror period t3 ends. As in the first embodiment of the present invention, the timer circuit 9 may be constituted by an existing delay circuit or a filter circuit capable of significantly reducing the risk of malfunction or destruction.
[0053]
In the present embodiment, the drive circuit is formed by pMOS transistors, but any other component having the same switch function may be used. Further, in the present embodiment, an example in which an IGBT is used as a main element is described. However, the effect of applying the present invention in exactly the same manner to other voltage-controlled semiconductor elements can be obtained. This is the same as the embodiment.
[0054]
Further, as shown in FIG. 3, even in the control method in which the driving circuit 2 that has been operating first after switching the driving circuit is not stopped, the effective gate of the IGBT 1 is used in the same manner as in the first embodiment of the present invention. The resistance value is switched from Ra alone to the parallel connection resistance of Ra and Rb, and the same effect is obtained. In this case, since a circuit configuration for stopping Sa is not required, the number of components can be reduced.
[0055]
Regarding the reference voltage Vref of the comparator 23, the mirror phenomenon in which the gate voltage of the IGBT becomes constant at the time of turn-on differs depending on the element, and the drive circuit switching timing is determined from the outside of the drive device of the present invention depending on the peripheral circuit configuration, operating conditions, and the like. You may need to make adjustments. In that case, a function of adjusting the reference voltage Vref of the comparator from outside the device may be added.
[0056]
Next, a third embodiment of the present invention will be described in detail with reference to FIG. This embodiment detects the emitter current of the IGBT 1 to control the operation timing of the drive circuits 2 and 3, and executes control based on the emitter current. In this embodiment, an IGBT having a multi-emitter structure and having a so-called current sensing function of detecting a part of the total emitter current from a part of the emitters is used.
[0057]
As shown in FIG. 6, the driving device according to the present embodiment has driving circuits 2 and 3 having the same configuration as the first and second embodiments, and a gate resistor connecting the driving circuits 2 and 3 and the gate of the IGBT 1. 4 and 5 and a control device 6 for controlling the operation timing of the drive circuits 2 and 3. Here, it is assumed that the resistance value Ra of the gate resistor 4 is larger than the resistance value Rb of the gate resistor 5 as in the first and second embodiments. Further, the control device 6 includes a timing determination device 8 that determines the timing of switching the drive circuit, and a logic circuit that switches between the drive circuit 2 and the drive circuit 3 according to the output of the timing determination device 8. In the present embodiment, as an example of the logic circuit, a NAND gate 20 which receives the output signal of the timing determination device 8 via the inverter 22 and the input signal Vin as input and sends the output to the drive circuit 2, And a NAND gate 21 that receives an output signal and an input signal Vin as inputs and sends an output to the drive circuit 3.
[0058]
The timing determining device 8 in the present embodiment detects the emitter current of the IGBT 1 and determines the timing for switching between the driving circuit 2 and the driving circuit 3. The configuration of the timing determination device 8 according to the present embodiment includes a resistor 25, a comparator 23 that compares a voltage of the resistor 25 that changes according to an emitter current amount of the IGBT 1 with a predetermined reference voltage Vref 24, and a JK flip-flop 26. And a timer circuit 9. The reference voltage Vref is set slightly higher than the main current value after turning on.
[0059]
Next, the operation of this embodiment will be described in detail with reference to FIG. After the high-level ON signal Vin shown in FIG. 7A is input to the input terminal 7, the emitter current increases as shown in FIG. 7C, and the voltage generated at the resistor 25 also rises and peaks. If the drive circuit is switched during the period t5 until the emitter current is reached, the emitter current changes sharply as in the conventional example, and there is a danger of malfunction or destruction due to the noise generated thereby. In order to avoid this danger, the timing for switching the drive circuit may be set in a period t6 following the period t5.
[0060]
While the high-level ON signal Vin is input to the input terminal 7 and the voltage generated in the resistor 25 that changes according to the emitter current value of the IGBT 1 is lower than the reference voltage Vref set slightly higher than the main current value after turn-on. Indicates that the output of the comparator 23 is at the low level. At this time, since the output of the JK flip-flop 26 is also at the Low level, an ON signal is output from the NAND gate 20 to the gate of the pMOS transistor Sa of the drive circuit 2 to operate the drive circuit 2, and as a result, the gate current flows to the IGBT 1 through the gate resistor 4. Supplied.
[0061]
Thereafter, when the emitter current of the IGBT 1 increases and the voltage generated in the resistor 25 rises and exceeds the reference voltage Vref of the comparator 23 which is set slightly higher than the main current value after turning on, the output of the comparator 23 becomes High level. The output of the comparator 23 has the waveform shown in FIG. The next-stage JK flip-flop 26 outputs the High level when the output of the comparator 23 returns to the Low level.
The output of the NAND gate 21 goes high, the drive circuit 2 stops, the output of the NAND gate 21 goes low, the drive circuit 3 operates, and the effective gate resistance of the IGBT 1 changes from a large resistance Ra to a small resistance Rb. Is switched to.
[0062]
In this embodiment, the emitter current is directly detected, unlike the case where the drive circuit is switched by detecting the end of the mirror period described in the first and second embodiments of the present invention. In order to directly detect that the emitter current has passed the peak and has reached a stable ON state, the drive circuit switches during the turn-on operation as in the past, and the destruction caused by the sudden change in the main current causes The risk of malfunction can be significantly reduced, and a highly reliable drive device can be provided. Further, it is possible to switch the drive circuit at an earlier timing than in the first and second embodiments of the present invention, and it is possible to provide a drive device having a low-loss soft switching operation.
[0063]
Further, in the present embodiment, the drive circuit is configured by the pMOS transistor, but any other configuration having the same switch function may be used. Further, in the present embodiment, an example in which an IGBT is used as a main element is described. However, the effect of applying the present invention in exactly the same manner to other voltage-controlled semiconductor elements can be obtained. This is the same as the embodiment.
[0064]
Further, even in the control method shown in FIG. 3 which does not stop the driving circuit 2 which has been operating first after switching the driving circuit, the effective gate resistance value of the IGBT 1 is the same as in the first embodiment of the present invention. Is switched from Ra alone to the parallel connection resistance of Ra and Rb, and the same effect is obtained. In this case, since a circuit configuration for stopping Sa is not required, the number of components can be reduced.
[0065]
In this embodiment, an example is described in which an IGBT having a current sensing function is used, but the emitter current may be detected by other methods. In addition, the present invention is not limited to the emitter current, and may be configured to use the current as long as the current amount changes in accordance with the time change characteristic in the initial state.
[0066]
Next, a fourth embodiment of the present invention will be described in detail with reference to FIG. In the present embodiment, similarly to the second embodiment of the present invention, the switching timing of the driving circuit is determined by detecting the gate voltage of the IGBT 1 and the control is executed. The driving circuit 2 and the driving circuit 3, and the driving circuit 2, a resistor 4 for connecting the drive circuit 3 and the gate of the IGBT 1 and a control device having the same configuration as the control device of the second embodiment of the present invention. The driving device 2 includes a pMOS transistor Sa and a gate power supply Va, and the driving device 3 includes a pMOS transistor Sb and a gate power supply Vb, and Va is set to a voltage lower than Vb. Therefore, during the period from the input signal Vin being applied to the timing determined by the timing determining device 8, the drive circuit 2 is activated, the gate power supply Va is enabled, and the gate voltage of the IGBT 1 rises slowly. After that, when the drive circuit 3 is started by the control device 6, the high-voltage gate power supply Vb becomes effective. Since the drive device switching timing is determined by the same control device 6 as in the second embodiment of the present invention, the operation of the IGBT 1 is the same as the characteristics shown in FIGS. , A low-loss drive device can be realized.
[0067]
FIG. 9 shows a fifth embodiment of the present invention. This embodiment controls the drive circuits 2 and 3, the drive circuits 2, the resistors 4 and 5, respectively connecting the drive circuit 3 and the gate of the IGBT, the gate power supply + V, and the operation of each drive circuit. And a control device 6 for performing the operation. The control device 6 includes a timing determination device 8 that determines a timing for switching the drive circuit, and a logic circuit that switches between the drive circuit 2 and the drive circuit 3 according to the output of the timing determination device 8. The resistance value Rb of the gate resistor 5 is set smaller than the resistance value Ra of the gate resistor 4. Further, in this embodiment, the drive circuit is constituted by a pMOS transistor, but any other device having a switch function may be used.
[0068]
The timing determining device 8 according to the present embodiment includes a delay circuit 19. The operation of this embodiment will be described in detail with reference to the waveforms of the respective units shown in FIG. When a high-level ON signal Vin is input to the input terminal 7, the pMOS transistor Sa is turned on, the drive circuit 2 is activated, and the resistor 4 having the resistance value Ra becomes effective. Thereafter, a signal in which the ON signal Vin is delayed by the predetermined time t1 is formed by the delay circuit 19, and after the input of the ON signal Vin, the signal is switched to the driving circuit 3 after t1 to enable the resistor 5 having the resistance value Rb. Here, the predetermined time t1 is, as shown in FIG.
t1> td + t2 + t3
Therefore, a high-reliability and low-loss drive device can be realized as in the other embodiments described above.
[0069]
Although the embodiments of the present invention have been described with respect to the turn-on operation, the sixth embodiment of the present invention will now be described in detail with reference to FIG. In this embodiment, as in the second embodiment of the present invention, the gate voltage of the IGBT 1 is detected to control the operation timing of the drive circuits 2 and 3, and the control is executed based on the gate voltage. In this figure, only the IGBT to be driven is displayed, and the load connected to the IGBT, the configuration related to turn-on control, and the configuration of other IGBT devices are omitted.
[0070]
Even in the turn-off operation, if the operation is performed at a high speed, the IGBT is likely to be in a latch-up state and easily broken. Also, since di / dt increases, the jump voltage L × di / dt generated by the floating inductance L of the wiring or the like increases. Therefore, for example, it is necessary to control not to operate too fast by increasing the gate resistance. However, if the gate resistance is increased, erroneous ignition due to noise or the like will occur even after the turn-off operation is turned off after the latter half of the turn-off operation. The danger increases. Therefore, in the turn-off operation, the control of increasing the gate resistance in the first half and switching to the small gate resistance in the second half is very effective.
[0071]
The drive device of the present embodiment drives the IGBT 1 according to the off signal Vin applied to the input terminal 7, and connects the drive circuit 2 and the drive circuit 3 with the drive circuit 2, the drive circuit 3, and the gate of the IGBT 1, respectively. It has resistors 4 and 5, a gate power supply V ', and a control device 6 for controlling the operation of each drive circuit. The control device 6 includes a timing determination device 8 that determines a timing for switching the drive circuit, and a logic circuit that switches between the drive circuit 2 and the drive circuit 3 according to the output of the timing determination device 8. The resistance value Rd of the gate resistor 5 is set smaller than the resistance value Rc of the gate resistor 4. Further, in the present embodiment, the drive circuit is constituted by nMOS transistors, but may be any other device having a switch function.
[0072]
In the present embodiment, as an example of this logic circuit, a NAND gate 20 which receives an output signal of the timing determination device 8 via the inverter 22 and an inverted signal of the input signal Vin by the inverter 25 and sends an output to the drive circuit 2 is provided. And a NAND gate 21 which receives an output of the timing determination device 8 and an inverted signal of the input signal Vin and sends an output to the drive circuit 3.
[0073]
The timing determining device 8 in the present embodiment detects the gate voltage of the IGBT 1 and determines the timing for switching between the driving circuit 2 and the driving circuit 3. The configuration of the timing determination device 8 in the present embodiment includes a comparator 23 that compares the gate voltage of the IGBT 1 with a predetermined reference voltage Vref24 and the timer circuit 9.
[0074]
Next, the operation of this embodiment will be described. While the off signal Vin is input to the input terminal 7 and the gate voltage of the IGBT 1 is higher than the reference voltage Vref, the output of the comparator 23 is at the low level. Therefore, the nMOS transistor Sc of the drive circuit 2 is turned on, and the drive circuit 2 is activated. As a result, the gate capacitance of the IGBT 1 is discharged through the gate resistor 4. Thereafter, when the gate voltage of the IGBT 1 falls and the gate voltage becomes equal to or lower than a predetermined reference voltage Vref of the comparator 23, the output of the comparator 23 becomes High level, the output of the NAND gate 20 becomes Low level, and the drive circuit 2 At the same time, the output of the NAND gate 21 becomes High level and the drive circuit 3 starts, and the effective gate resistance of the IGBT 1 is switched from the large resistance value Rc to the small resistance value Rd.
[0075]
Here, the switching timing of the gate resistance may be a timing after the mirror period ends. Specifically, in this embodiment, the reference voltage Vref of the comparator 23 may be set lower than the gate voltage during the mirror period. Thus, the timing of switching the driving circuit can be set after the mirror period ends. Alternatively, the same effect can be obtained even if the reference voltage Vref of the comparator 23 is set to be equal to or lower than the threshold voltage of the IGBT1. In some cases, it may be devised that the power is turned off after the end of the mirror period through the timer circuit 9. The timer circuit 9 may be constituted by an existing delay circuit or a filter circuit that can significantly reduce the risk of malfunction or destruction.
[0076]
As described above, by reducing the gate resistance until the mirror is turned off and stable after the end of the mirror period, the danger of erroneous ignition due to noise or the like can be remarkably reduced from the latter half of the turn-off operation to the off-state as in the related art, and high reliability Drive device can be provided.
[0077]
Further, in the present embodiment, the drive circuit is constituted by nMOS transistors, but any other component having the same switch function may be employed. Further, in this embodiment, only the case of the turn-off operation has been described. However, by applying to both the turn-on and turn-off simultaneously in combination with the above-described embodiment of the turn-on operation, low loss and high reliability can be achieved over the entire switching operation. A drive circuit capable of performing optimal control can be provided. Further, in this embodiment, an example in which an IGBT is used as a main element is described. However, the effect of applying the present invention to other voltage-controlled semiconductor elements can be obtained in the same manner as in the present invention. This is similar to the first embodiment.
[0078]
【The invention's effect】
According to the present invention, in a semiconductor device including a voltage-driven semiconductor element such as an IGBT, it is possible to reduce a time change rate of a current at the time of turn-on and to reduce a turn-on loss, and furthermore, there is a risk of malfunction or destruction. It is possible to provide a method and a device for driving a voltage-driven semiconductor device with extremely low reliability.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a first embodiment to which the present invention is applied.
FIG. 2 is a waveform chart illustrating a control method according to the first embodiment.
FIG. 3 is a waveform chart for explaining another control method of the first embodiment.
FIG. 4 is a circuit diagram for realizing another control method.
FIG. 5 is a circuit diagram of a second embodiment to which the present invention is applied.
FIG. 6 is a circuit diagram of a third embodiment to which the present invention is applied.
FIG. 7 is a waveform chart illustrating a control method according to a third embodiment.
FIG. 8 is a circuit diagram of a fourth embodiment to which the present invention is applied.
FIG. 9 is a circuit diagram of a fifth embodiment to which the present invention is applied.
FIG. 10 is a circuit diagram of a sixth embodiment to which the present invention is applied.
FIG. 11 is a waveform chart illustrating a control method according to a sixth embodiment.
FIG. 12 is a circuit diagram of a conventional driving circuit.
FIG. 13 is a waveform chart illustrating a conventional control method.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... IGBT, 2,3 ... Drive circuit, 4,5 ... Gate resistance, 6 ... Control device, 7 ... Input terminal, 8 ... Timing determination device, 9 ... Timer circuit, 10, 11, 20,
21: NAND gate, 12, 22, inverter, 23: comparator.

Claims (13)

The initial state after the control signal is applied to the gate electrode includes a first period in which the gate voltage rises and / or falls with time and a second period in which the gate voltage is substantially constant after the first period. A semiconductor including a power semiconductor element having at least a first electrode on a high potential side for flowing a main current, a second electrode on a low potential side, and a gate electrode for controlling a main current. In the driving method of the device, a driving voltage applied to the gate electrode in a third period including all of the initial state is set to be lower than a driving voltage applied to the gate in a fourth period following the third period. And a driving voltage applied to the gate electrode is changed after the initial state is completed. The initial state after the control signal is applied to the gate electrode includes a first period in which the gate voltage rises and / or falls with time and a second period in which the gate voltage is substantially constant after the first period. A semiconductor including at least a power semiconductor element having a first electrode on a high potential side for flowing a main current, a second electrode on a low potential side, and a gate electrode for controlling a main current. In the driving method of the device, a predetermined voltage as the driving voltage is applied to the gate electrode through a first gate resistor having a first resistance value during the third period, and the driving voltage is applied during the fourth period. A predetermined drive voltage is applied to the gate electrode through a second resistor having a second resistance value smaller than the first resistance value, and a predetermined voltage generated as the drive voltage is applied to the gate electrode. From the third period in which the predetermined drive voltage is applied to the gate electrode through a first gate resistor having a first resistance value, the second resistance having a smaller resistance value than the first resistance value. A driving method of the semiconductor device, wherein the voltage is changed after the initial state is completed in the fourth period in which the voltage is applied to the gate electrode through a second resistor having a value. A fifth period in which the main current rises and / or falls with time after the control signal is applied to the gate electrode; and a fifth period during which the main current falls or rises to a stable state after the fifth period. A driving voltage applied to the gate electrode in a seventh period including all of the sixth periods, wherein a driving voltage applied to the gate electrode in a seventh period including all of the sixth periods is changed. A driving method of a semiconductor device, wherein the driving voltage is lower than the driving voltage applied to the gate during a period of 8, and the driving voltage applied to the gate electrode is changed after the initial state is completed. A fifth period during which the main current rises and / or falls with time after the control signal is applied to the gate electrode, and a period until the main current falls and / or rises to a stable state after the fifth period. The driving method of the power semiconductor device including at least a sixth period of the first gate resistance having the first resistance value at a predetermined voltage as the driving voltage during the seventh period. And applying the predetermined drive voltage to the gate electrode through the second resistor having a second resistance value smaller than the first resistance value during the eighth period. Applied to the electrodes,
From the seventh period in which a predetermined voltage is applied as the drive voltage to the gate electrode through the first gate resistor having the first resistance value, the predetermined drive voltage is changed to the first resistance value. In the eighth period applied to the gate electrode through the second resistor having the second resistance value smaller than the second resistance value, the voltage is changed after the fifth period ends. A method for driving a semiconductor device. In a driving device for a semiconductor device that drives by applying a driving voltage to a gate electrode of a semiconductor device, a first and a second driving circuit that generates the driving voltage are connected to the first driving circuit and the gate electrode. A first gate resistance, and a second gate resistance having a second resistance smaller than the resistance of the first gate resistance connecting the second drive circuit and the gate electrode. First, the first drive circuit is operated in accordance with the control signal, and the timing for switching the drive circuit to be operated is determined. In response to the timing, the operation of the first drive circuit is stopped. A control circuit for starting operation of the drive circuit, wherein the control circuit includes a timing determination device for determining the timing for switching from the third period to the fourth period. Drive apparatus for a semiconductor device to be. In a driving device for a semiconductor device that drives by applying a driving voltage to a gate electrode of a semiconductor device, a first and a second driving circuit that generates the driving voltage are connected to the first driving circuit and the gate electrode. A first gate resistor, a second gate resistor having a second resistance smaller than a resistance of the first gate resistor connecting the second drive circuit and the gate electrode, and an input. A control circuit that first determines the timing after operating the first drive circuit according to the control signal to be performed, and starts the operation of the second drive circuit according to the timing. The driving device of a semiconductor device, wherein the control circuit includes a timing determination device that determines the timing for activating the second driving circuit during a fourth period. In any one of claims 3 to 6,
The timing determination device has a delay circuit that delays by a set period including an initial state including the first and second periods after the input of the control signal to be input, and when the delay signal is output Is the timing described above. In any one of claims 3 to 6,
The timing determination device detects a potential of a first electrode of the semiconductor element, and determines whether the detected potential of the first electrode is equal to or less than and / or equal to a predetermined reference voltage value. A semiconductor circuit having a determination circuit, wherein a timing at which the detected first potential of the semiconductor element becomes equal to or lower than the predetermined voltage value as a result of the determination is set as the timing; The drive of the device. In any one of claims 3 to 6,
The timing determination device includes a gate voltage determination circuit that detects a gate voltage of the semiconductor element and determines whether the detected gate voltage is equal to or higher than a predetermined reference voltage value and / or lower. A driving device for a semiconductor device, wherein a timing when the detected gate voltage becomes equal to or more than the predetermined voltage value as a result of the determination is set as the timing. In any one of claims 3 to 6,
The timing determination device detects any one of a main current of the semiconductor element and a current that changes according to a current amount of the main current, and the detected current value is equal to or more than a predetermined reference current value. And / or a current judging circuit for judging whether or not the current value is equal to or less than the predetermined current value as a result of the judgment. Circuit for driving a semiconductor device. In any one of claims 6 to 10,
The timing determination device has a timer circuit that measures only a predetermined time from various detection times, and a time when an output is output from the timer circuit after a predetermined time has elapsed from various detection times is the timing. A driving circuit for a semiconductor device, comprising: In any one of claims 6 to 11,
The timing determination device has a filter circuit that detects that the detection is continuously performed for a predetermined time from various detection times, and an output is output from the filter circuit after a predetermined time has elapsed from the various detection times. A driving circuit for a semiconductor device, wherein a timing at which the driving is performed is the timing. In any one of claims 6 to 12,
A device for driving a semiconductor element, characterized by having a function of making a reference value variable in various determination circuits included in the timing determination device.

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