JP2016208089A - Gate drive circuit for voltage-driven semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a gate drive circuit for a voltage-driven semiconductor element capable of accurately changing a drive mode and suppressing a voltage signal of a free wheeling diode of an opposite arm while suppressing a turn-on loss of the voltage-driven semiconductor element.SOLUTION: The gate drive circuit for the voltage-driven semiconductor element is configured to drive gates of voltage-driven semiconductor elements 12U and 12D in which free wheeling diodes 13U and 13D are connected in reverse parallel. The gate drive circuit comprises: gate drive parts 16U and 16D capable of driving the gates of the voltage-driven semiconductor elements in different gate drive modes when turning on the gates; voltage detection parts 17U and 17D that detect voltages across main terminals of the voltage-driven semiconductor elements; and drive mode change parts 18U and 18D which change the gate drive modes in the gate drive parts based on the voltages that have been detected by the voltage detection parts.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a gate drive circuit for a voltage-driven semiconductor element capable of suppressing loss and vibration at turn-on of a voltage-driven semiconductor element having free wheeling diodes connected in antiparallel.

  The basic circuit of the gate drive circuit of this type of voltage-driven semiconductor element is configured as shown in FIG. This gate drive circuit has an insulated gate bipolar transistor (hereinafter referred to as IGBT) 102 as a voltage drive type semiconductor element in which freewheeling diodes 101 are connected in antiparallel, and a gate drive circuit 103 is connected to the gate of the IGBT 102. Is connected.

  The gate drive circuit 103 includes, for example, an N-channel MOSFET 104 and a P-channel MOSFET 105 connected in series, and DC power sources 106 and 107 connected in series. The drain of the N-channel MOSFET 104 is connected to the positive side of the DC power source 106 through a turn-on resistor 108, and the drain of the P-channel MOSFET 105 is connected to the negative side of the DC power source 107 through a turn-off resistor 109.

A connection point between the N-channel MOSFET 104 and the P-channel MOSFET 105 is connected to the gate of the IGBT 102, and the gates of the N-channel MOSFET 104 and the P-channel MOSFET 105 are connected to each other and connected to the control circuit 110.
The emitter of the IGBT 102 is connected to a connection point between the DC power source 106 and the DC power source 107.

  An IGBT 102 driven by such a gate drive circuit 103 (hereinafter, as shown in FIG. 11, an IGBT as a voltage drive type semiconductor element, a gate drive circuit for driving the IGBT, and a freewheeling reversely connected to the IGBT When an inverter circuit is configured by connecting two series of diode circuits simply as an arm), when the IGBT 102 is turned on, the diode of the opposite arm becomes reverse recovery operation and is transient. To generate a voltage. As shown in FIG. 12, the jump voltage changes according to the change in the main circuit voltage Vdc of the inverter circuit. That is, as the main circuit voltage Vdc rises, the peak value of the reverse recovery voltage jump voltage also rises and oscillates when the main circuit voltage exceeds a certain voltage.

  In order to suppress this oscillation, generally, the turn-on resistance is adjusted. When the turn-on resistance is changed at turn-on, the main terminal voltage (collector-emitter voltage) Vce and the collector current Ic of the IGBT 102 change as shown in FIG. 13A, and the freewheeling diode 101 of the opposing arm changes. The anode-cathode voltage Vak and the cathode current Ik change as shown in FIG.

  That is, when the turn-on resistance is small, the switching of the IGBT 102 becomes faster as indicated by the characteristic lines L31 and L33 shown by broken lines in FIG. 13A, and dI / dt increases relatively steeply. Is large, the switching of the IGBT 102 becomes gradual and dI / dt becomes small, as indicated by the characteristic lines L32 and L34 shown by solid lines in FIG. Characteristic lines L31 and L33 indicate the collector current Ic and collector-emitter voltage Vce of the IGBT 102 when the turn-on resistance is small, respectively. Characteristic lines L32 and L34 indicate the collector current Ic and collector of the IGBT 102 when the turn-on resistance is large, respectively. Indicates the emitter voltage Vce.

  When the switching speed of the IGBT changes in this manner, the anode-cathode voltage Vak of the freewheeling diode 101 of the opposing arm has a characteristic line L41 shown by a broken line in FIG. 13B when the turn-on resistance is small. As shown in FIG. 13B, when the turn-on resistance is large, as shown by a characteristic line L42 shown by a solid line in FIG. 13B, the jump peak value becomes small and the same main circuit voltage is obtained. Even if there is, it becomes difficult to oscillate. In FIG. 13B, the characteristic line L43 indicates the cathode current Ik when the turn-on resistance is small, and the characteristic line L44 indicates the cathode current Ik when the turn-on resistance is large.

As another method, as described in Patent Document 1, a gate drive circuit is proposed in which the gate resistance for turn-on is switched by the second-order differential value of the main circuit current.
As shown schematically in FIG. 14, this gate drive circuit is configured by connecting a series circuit of a turn-on resistor 111 and a semiconductor switch element 112 in parallel with the turn-on resistor 108 in the configuration of FIG. Then, a differentiating circuit 113 for differentiating the voltage across the sense resistor (not shown) for detecting the main circuit current flowing in the IGBT 102 and a differentiating circuit 114 for further differentiating the first-order differential value of the differentiating circuit 113 are provided. When the comparator 115 detects that the second-order differential value output from the differentiating circuit 114 is equal to or lower than the set value, the turn-on loss is obtained by turning off the semiconductor switch element 112 and increasing the gate resistance value of the IGBT 102 with the output. The reverse recovery voltage increase rate (dV / dt) is reduced within a range in which the oscillation is not increased to suppress oscillation.

  Further, in the conventional example described in Patent Document 2, the gate drive resistor connected between the gate terminal of the voltage control type semiconductor switching element and the turn-on power supply and the gate voltage of the voltage control type semiconductor switching element are the main current. Threshold detection means for detecting that the threshold has been reached and the gate drive resistance are set to the first resistance value at the start of the turn-on operation, and the threshold detection means detects that the gate voltage has reached the voltage. And a gate drive resistance setting means for setting the second resistance value larger than the first resistance value and then setting the third resistance value smaller than the first and second resistance values. Yes.

Japanese Patent Laid-Open No. 11-69778 JP 2013-223265 A

However, the method of simply increasing the gate resistance at the turn-on has a problem that the IGBT dI / dt becomes small and the loss of the IGBT at the turn-on becomes large.
On the other hand, in the conventional example described in Patent Document 1, since the second-order differential value of the main circuit current flowing through the IGBT is detected and the gate resistance is switched, the dI / dt of the IGBT at the initial turn-on is maintained by a small gate resistance. Therefore, the loss of the IGBT at turn-on does not increase so much, but two differentiating circuits for detecting the second-order differential value are required, and there is a problem that the gate driving circuit becomes complicated.

  Further, in the conventional example described in Patent Document 1, the reverse of the freewheeling diode of the counter arm shown in the lower diagram of FIG. 15 with respect to the gate current Ig when the conventional turn-on resistance shown in the solid line in FIG. A region in which the gate current Ig is sharply decreased by changing the turn-on resistance to a large resistance value before the anode-cathode voltage Vak reaches the peak voltage at the time of recovery, and the gate current at the end period of the reverse recovery operation becomes negative. There is also a problem that the gate current is insufficient.

  Further, in the conventional example described in Patent Document 2, the threshold voltage detecting means detects the gate voltage between the gate and the emitter of the voltage controlled semiconductor switching element, and this gate voltage reaches the threshold value at which the main current starts to flow. Before and after, the first resistance value and the second resistance value larger than the first resistance value are switched, and then the third resistance value smaller than the first and second resistance values is switched.

  In the conventional example described in Patent Document 2, the start of the flow of the main current is detected by the gate voltage between the gate and the emitter, but the gate voltage and the collector-emitter voltage of the voltage controlled semiconductor switching element are Does not correspond one-to-one, and the behavior of the collector-emitter voltage differs even with the same gate voltage depending on the load state. In addition, since the detection of the switching timing in the switching control circuit is detected by the threshold voltage and delay time of the inverter, the inverter threshold and delay time cannot be determined accurately, and precise control is performed. I can't. In addition, the delay time from when the gate-emitter voltage exceeds the threshold value until it reaches the appropriate collector-emitter voltage varies depending on the main circuit configuration including the load and the driving mode. There are problems such as difficulty in performing.

  Therefore, the present invention has been made paying attention to the problems of the above-described conventional example, can appropriately change the driving mode, and freewheeling the opposing arm while suppressing the turn-on loss of the voltage-driven semiconductor element. An object of the present invention is to provide a gate drive circuit for a voltage-driven semiconductor element capable of suppressing a voltage signal of a diode.

  In order to achieve the above object, a gate drive circuit for a voltage-driven semiconductor device according to an aspect of the present invention is a voltage-driven semiconductor that drives a gate of a voltage-driven semiconductor device in which freewheeling diodes are connected in antiparallel. It is a gate drive circuit of the element. The voltage detection unit detects the voltage between the main terminals of the voltage-driven semiconductor element, the gate drive unit that can drive the gate of the voltage-driven semiconductor element in a different gate drive mode at the time of turn-on, and the voltage detection unit And a driving mode changing unit that changes the gate driving mode in the gate driving unit based on the voltage.

  According to one aspect of the present invention, it is possible to appropriately change the driving mode with a simple configuration and suppress both the turn-on loss of the voltage-driven semiconductor element and the vibration of the freewheeling diode of the opposing arm.

1 is a circuit diagram illustrating an embodiment of a gate drive circuit for a voltage-driven semiconductor device according to an aspect of the present invention. FIG. 2 is a circuit diagram showing a specific configuration of the gate drive circuit of FIG. 1. FIG. 2 is a characteristic diagram showing voltage / current characteristics of the insulated gate bipolar transistor and the freewheeling diode of FIG. 1. It is explanatory drawing which shows the current pathway in the OFF period of the insulated gate bipolar transistor in the lower arm of FIG. FIG. 2 is an explanatory diagram showing a current path in an initial turn-on period of an insulated gate bipolar transistor in the lower arm of FIG. 1. It is explanatory drawing which shows the electric current path in the reverse recovery operation start period of the freewheeling diode of the opposing arm in the lower arm of FIG. It is explanatory drawing which shows the electric current path in the reverse recovery operation | movement period of the freewheeling diode of the opposing arm in the lower arm of FIG. It is a circuit diagram which shows 2nd Embodiment of the gate drive circuit of the voltage drive type semiconductor device which shows one form of this invention. It is a characteristic diagram which shows the drain-source voltage characteristic of MOSFET of the gate drive circuit used for 2nd Embodiment. It is a circuit diagram which shows the modification of 3rd Embodiment of the gate drive circuit of the voltage drive type semiconductor device which shows one form of this invention. It is a circuit diagram which shows the basic composition of a gate drive circuit. It is a characteristic diagram which shows the anode-sword voltage characteristic of a freewheeling diode. It is a characteristic diagram which shows the voltage-current characteristic of the insulated gate bipolar transistor and the freewheeling diode of an opposing arm. It is a circuit diagram which shows the prior art example of a gate drive circuit. It is a characteristic diagram which shows the relationship between the gate current characteristic of a prior art example, and the anode-cathode voltage of the freewheeling diode of an opposing arm.

Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals.
Further, the embodiment described below exemplifies an apparatus and a method for embodying the technical idea of the present invention, and the technical idea of the present invention is the material, shape, structure, The layout is not specified as follows. The technical idea of the present invention can be variously modified within the technical scope defined by the claims described in the claims.

First, a first embodiment in which a gate drive circuit of a voltage drive type semiconductor element representing one aspect of the present invention is applied to an inverter circuit will be described.
The inverter circuit 1 generates, for example, a three-phase alternating current and drives a load. As shown in FIG. 1, a circuit that generates a single-phase alternating current for one phase will be described. For example, the upper arm 11U and the lower arm 11D are connected in series between the positive electrode side line Lp and the negative electrode side line Ln connected to 720V).

The upper arm 11U includes an insulated gate bipolar transistor (hereinafter simply referred to as IGBT) 12U as a voltage-controlled semiconductor element, and a freewheeling diode (hereinafter simply referred to as FWD) 13U connected in reverse parallel to the IGBT 12U. And a gate drive circuit 14U for driving the gate of the IGBT 12U.
The lower arm 11D also includes an IGBT 12D as a voltage-controlled semiconductor element, an FWD 13D connected in reverse parallel to the IGBT 12D, and a gate drive circuit 14D that drives the gate of the IGBT 12D.

A load 15 such as a three-phase motor is connected to a connection point P between the upper arm 11U and the lower arm 11D. FIG. 1 shows a case where the lower arm 10D shifts from the off state to the turn on state, and the load 15 is connected between the connection point P and the positive electrode side line Lp. Moreover, as shown with a broken line, another load is connected between the negative electrode side line Ln.
The gate drive circuit 14U is based on a gate drive unit 16U that drives the gate of the IGBT 12U, a voltage detection unit 17U that detects a voltage between the collector and the emitter that is a main terminal of the IGBT 12U, and a voltage that is detected by the voltage detection unit 17U. And a drive mode change unit 18U that changes the gate drive mode in the gate drive unit 16U.

  Gate drive unit 16U includes DC power supplies 21a and 21b connected in series, and N-channel MOSFET 22a and P-channel MOSFET 22b as semiconductor switching elements connected in series. A turn-on resistor 23a is connected between the positive side of the DC power supply 21a and the drain of the N-channel MOSFET 22a. A turn-off resistor 23b is connected between the negative electrode side of the DC power supply 21b and the drain of the P-channel MOSFET 22b. The connection point between the DC power supplies 21a and 21b is connected to the emitter of the IGBT 12U. Further, the gates of the N-channel MOSFET 22a and the P-channel MOSFET 22b are connected to the control circuit 25, and the N-channel MOSFET 22a and the P-channel MOSFET 22b are on / off controlled by the drive signal Sa output from the control circuit 25.

The turn-on resistance portion 23a changes the driving capability of the IGBT 12U when it is turned on, and is the same as the resistance value of the gate resistance Rg1 having a relatively high resistance value and the gate resistance Rg1 connected in parallel with the gate resistance Rg1. The gate resistance Rg2 having a resistance value lower than that and a series circuit of an N-channel MOSFET 24 as a semiconductor switching element are configured.
Therefore, the resistance value of the turn-on resistance portion 23a is a high resistance value of only the gate resistance Rg1 when the N-channel MOSFET 24 is in the off state, and the gate resistance Rg2 is connected in parallel to the gate resistance Rg1 when the N-channel MOSFET 24 is in the on state. Therefore, the resistance value is a half or less of the resistance values of Rg1 and Rg2.

The voltage detector 17U includes voltage dividing resistors R1 and R2 connected in series between the collector and emitter of the IGBT 12U, and the detection voltage Vud between the main terminals output from the connection point of the voltage dividing resistors R1 and R2 is driven. It is supplied to the changing unit 18U.
As shown in FIG. 2, the drive mode change unit 18U includes a first comparator 31, a second comparator 32, and an OR circuit 33 to which the main terminal detection voltage Vud output from the voltage detection unit 17U is input. A logic inversion circuit 34 is provided. The first comparator 31 constitutes a first comparison unit, and the OR circuit 33 and the logic inversion circuit 34 constitute a second comparison unit.

  In the first comparator 31, the divided voltage Vud of the detection voltage Vce between the main terminals is input to the non-inverting input terminal, and the first reference voltage Vref1 is input to the inverting input terminal. Here, as shown in FIG. 3A, the first reference voltage Vref1 is such that the voltage Vce between the main terminals decreases when the IGBT 12U is turned on and the FWD 13D of the opposite arm is in a state where the turn-on resistance portion 23a has a low resistance value. Is set to the voltage when shifting to the reverse recovery operation.

  In the second comparator 32, the divided voltage Vud of the detection voltage Vce between the main terminals is input to the non-inverting input terminal, and the second reference voltage Vref2 is input to the inverting input terminal. Here, as shown in FIG. 3A, when the IGBT 12U is turned on, the second reference voltage Vref2 has the main terminal voltage Vce lower than the first reference voltage Vref1, and a high resistance value is selected by the turn-on resistor 23a. In this state, the FWD 13D of the opposite arm is set to a voltage that shifts to the reverse recovery operation continuation period.

  The output signal of the first comparator 31 is directly input to the input side of the OR circuit 33 and the output signal of the second comparator 32 is input via the logic inversion circuit 34. The driving mode change signal output from the OR circuit 33 is input to the gate of the N-channel MOSFET 24 of the turn-on resistance unit 23a in the gate driving units 16U and 16D. Note that the logic inversion circuit 34 may be deleted and the input to the inverting input terminal and the input to the non-inverting input terminal of the second comparator 32 may be interchanged so that the second comparator 32 is configured by the second comparator 32 alone. Good.

  The gate drive circuit 14D is also detected by the gate drive unit 16D that drives the gate of the IGBT 12U, the voltage detection unit 17D that detects the voltage between the collector and the emitter that is the main terminal of the IGBT 12D, and the voltage detection unit 17U. And a driving mode changing unit 18D that changes the gate driving mode in the gate driving unit 16D based on the voltage. The configurations of the gate drive unit 16D, the voltage detection unit 17D, and the drive mode change unit 18D are the same as the configurations of the gate drive unit 16U, the voltage detection unit 17U, and the drive mode change unit 18U of the gate drive circuit 14U described above. The detailed description thereof will be omitted.

FIG. 3A shows the relationship between the resistance value of the turn-on resistor 23a when the lower arm 11D is turned on, the collector-emitter main terminal voltage Vce and the collector current Ic when the IGBT 12D is turned on.
In FIG. 3A, characteristic lines L11 and L12 shown by solid lines indicate the main terminal voltage Vce and the collector current Ic in the present embodiment, respectively. Characteristic lines L13 and L14 shown by broken lines indicate the main-terminal voltage Vce and the collector current Ic when the resistance value of the turn-on resistance portion 23a is kept low.

  In the present embodiment, as will be described later, periods T1 and T2 in which the divided voltage Vud (Vdd) of the main-terminal voltage Vce is higher than the first reference voltage Vref1, and the divided voltage Vud (Vdd) is the first reference. The resistance value of the turn-on resistor 23a is changed in a period T3 between the voltage Vref and the second reference voltage Vref2, and in a period T4 in which the divided voltage Vud (Vdd) is lower than the second reference voltage Vref2. More specifically, the resistance value of the turn-on resistance portion 23a is decreased during the periods T1, T2, and T4, and the resistance value of the turn-on resistance portion 23a is increased during the period T3.

  In the period T1 in which the IGBT 12D is in the OFF state, the main terminal voltage Vce is maintained at about 720V, for example, as shown by the characteristic line L11 shown by the solid line, and the collector current Ic is zero, as shown by the characteristic line L12 shown by the solid line. To maintain. Thereafter, in a period T2 in which the turn-on is initially performed, when the gate voltage (not shown) exceeds the threshold voltage, the collector current Ic increases relatively steeply with a large dI / dt, and the main-terminal voltage Vce is accordingly increased. It decreases relatively steeply with a large dV / dt. Next, in the period T3 in which the FWD 13U of the upper arm 11U serving as the opposite arm starts the reverse recovery operation (as described above, the resistance value of the turn-on resistance portion 23a is high only during this period), the IGBT 12D is in the first half. The collector current Ic continues to increase sharply, but reaches a maximum value in the middle portion, and thereafter gradually decreases at a relatively small dI / dt. In response to this, the voltage Vce between the main terminals gradually decreases at a small dV / dt in the period T3. Next, in the period T4 in which the reverse recovery operation of the FWD 13U is continued, the collector current Ic continues to decrease at a relatively small dI / dt, and the main-terminal voltage Vce relatively decreases after a relatively large dV / dt in the first half. Decrease with small dV / dt.

  On the other hand, when the resistance value of the turn-on resistance portion 23a is kept low, the main-terminal voltage Vce and the collector current Ic are represented by characteristic lines L13 and L14 shown by broken lines in FIG. As shown, in the period T3 in which the reverse recovery operation of the FWD 13U of the opposite arm is started, the collector current Ic dI / dt becomes larger than that in the present embodiment, and the maximum value becomes larger and the period T3 ends. It becomes.

  Accordingly, the main terminal voltage Vce decreases at a relatively large dV / dt in the period T3. Thereafter, when the period T4 in which the reverse recovery operation of the FWD 13U is continued, the collector current Ic decreases relatively gently in the first half of the period T4, and then decreases relatively steeply in the middle of the period T4 and then substantially constant in the latter half. Keep the value. Accordingly, the main terminal voltage Vce decreases at a relatively small dV / dt in the period T4. The circuit constant in the period T4 is the same as that of the present embodiment, but the overshoot of the collector current Ic in the period T3 is large and the influence remains in the period T4. Therefore, the behavior of the characteristic lines L12 and L14 in the period T4 is greatly different. Yes.

FIG. 3B shows changes in the cathode current Ik and the anode-cathode voltage Vak of the FWD 13U of the upper arm 11U, which is an opposing arm when the IGBT 12D of the lower arm 11D is turned on.
In FIG. 3 (b), the cathode current Ik and the anode-cathode voltage Vak of the upper arm 11U in the present embodiment are indicated by characteristic lines L21 and L22 shown by solid lines, respectively. That is, the cathode current Ik maintains a forward high current (for example, 200 A) until the first half of the period T1 in which the IGBT 12D of the lower arm 11D is in the off state and the period T2 in the initial turn-on state, but thereafter has a large dI / dt. The reverse recovery current starts to flow sharply and begins to flow in the period T3 when the reverse recovery operation starts. In the middle of the period T3, the cathode current Ik becomes the minimum value, and then the reverse recovery current flows, whereby the cathode current Ik increases again. Note that the cathode current Ik in the second half of the period T3 and in the period T4 is basically equal to the reverse recovery current. In the period T4 during which the reverse recovery operation continues, dI / dt of the reverse recovery current becomes moderate. The reverse recovery current decreases and returns to zero in a period after T4 (not shown).

On the other hand, the anode-cathode voltage Vak maintains a negative low constant voltage (for example, about -1V) in the periods T1 and T2, and enters a reverse recovery start period T3, and increases sharply at a high dV / dt, In the period T4 in which the reverse recovery operation is continued, the voltage increases at a smaller dV / dt and then becomes a constant voltage (for example, about 720V).
Further, the cathode current Ik and the anode-cathode voltage Vak when the turn-on resistance portion 23a of the lower arm 11D remains low are indicated by characteristic lines L23 and L24 shown by broken lines in FIG. Yes. As can be seen from FIG. 3 (b), the cathode current Ik and the anode-cathode voltage Vak after the period T3 are greatly changed compared to the present embodiment. In particular, the change in the characteristic line L23 indicating the cathode current Ik in the period T4 is large and has a peak that greatly exceeds the voltage 720V of the DC power supply 10, and the adverse effect on the operation of the circuit is large.

Next, the operation of the first embodiment will be described with reference to FIGS. 4 to 7 in the case where the IGBT 12D of the lower arm 11D is turned on from the off state.
First, as shown in FIG. 4, it is assumed that a low-level drive signal is output from the control circuit 25 of the lower arm 11D and the N-channel MOSFET 22a is controlled to be in an off state and the P-channel MOSFET 22b is controlled to be in an on state. In this state, a current path is formed in which the charge accumulated in the gate capacitance of the IGBT 12D reaches the emitter of the IGBT 12D via the negative and positive sides of the P-channel MOSFET 22b and the DC power supply 21b, and the gate of the IGBT 12D is discharged. Has been turned off.

  In the above-described period T1 of FIG. 3A in which the IGBT 12D is in the OFF state, the resistance value of the turn-on resistance portion 23a is as shown in the characteristic curves L11 and L13 in FIG. Regardless of the high voltage. This high voltage state is detected by the voltage detector 17D, and the detection voltage Vdd between the main terminals is supplied to the non-inverting input side of the first comparator 31 and the second comparator 32 of the drive state changing unit 18D. Since the detection voltage Vdd between the main terminals is higher than the first reference voltage Vref1 and the second reference voltage Vref2 of the first comparator 31 and the second comparator 32, the output signals of the first comparator 31 and the second comparator 32 However, since the output signal of the second comparator 32 is inverted to a low level by the logic inversion circuit 34, the high level output signal of the first comparator 31 is gated through the OR circuit 33. The voltage is supplied to the gate of the N-channel MOSFET 24 in the turn-on resistance section 23a of the driving section 16D. Therefore, the N-channel MOSFET 24 is turned on, the gate resistances Rg1 and Rg2 are connected in parallel, and the resistance value of the turn-on resistance unit 23a becomes a low resistance value.

However, since the N-channel MOSFET 22a is in the OFF state, the current from the DC power supply 21a is not supplied to the gate of the IGBT 12D through the turn-on resistance portion 23a.
Next, when the IGBT 12D shifts from the off state to the turn on state, a high level drive signal is supplied from the control circuit 25 to the N channel MOSFET 22a and the P channel MOSFET 22b, the N channel MOSFET 22a is turned on, and the P channel MOSFET 22b is turned off. Control to the state. Thereby, as shown in FIG. 5, the current path from the emitter of the IGBT 12D to the negative and positive sides of the DC power supply 21a, the gate resistances Rg1 and Rg2 of the turn-on resistor 23a, and the N-channel MOSFET 22a to the gate of the IGBT 12D. Is formed. Thereby, the charging of the gate capacitance of the IGBT 12D is started, and the turn-on initial period T2 of FIG. Even during this period T2, the detection voltage Vdd between the main terminals detected by the voltage detector 17D is higher than the first reference voltage Vref1 and the second reference voltage Vref2 of the first comparator 31 and the second comparator 32. The resistance value of 23a is maintained at a low resistance value.

  For this reason, as shown by the characteristic curve L11 in FIG. 3A, when the gate voltage of the IGBT 12D exceeds the threshold at the end of the turn-on initial period T2, the voltage Vce between the main terminals of the IGBT 12D decreases at a large dV / dt, and the voltage When the detection voltage Vdd between the main terminals detected by the detection unit 17D becomes less than the first reference voltage Vref1 of the first comparator 31, the output signal of the first comparator 31 is inverted to a low level. On the other hand, in the second comparator 32, since the second reference voltage Vref2 is set lower than the first reference voltage Vref1, the output signal continues to be at a high level and is inverted to a low level by the logic inversion circuit 34.

  Accordingly, since the logical sum output of the logical sum circuit 33 is inverted from the high level to the low level, the N-channel MOSFET 24 in the turn-on resistance portion 23a of the gate driving portion 16D is turned off, and the turn-on resistance portion 23a as shown in FIG. Becomes a high resistance value only by the gate resistance Rg1, and the gate current supplied to the gate of the IGBT 12D is reduced and reduced.

  For this reason, the voltage Vce between the main terminals of the IGBT 12D gradually decreases at a small dV / dt in the period T3 when the reverse recovery operation of the FWD 13U of the upper arm 11U serving as the opposing arm starts as indicated by the solid line L11 in FIG. Will be reduced. Therefore, as shown in the characteristic diagram L12 shown by the solid line in FIG. 3A, an increase in the collector current of the IGBT 12D in the period T3 can be suppressed, so that the cathode of the reverse recovery operation of the FWD 13U of the upper arm 11U serving as the opposing arm is performed. The minimum value of the current Ik (the sum of the cathode current Ik of the diode 13U and the collector current Ic of the IGBT 12D is equal to the current flowing through the load 15 (which can be regarded as constant for a short time)) is shown by a solid line in FIG. As in L22, the influence value (reaction) on the subsequent period T4 can be reduced by making the resistance value of the turn-on resistance portion 23a larger than the state of L24 shown by the broken line when the resistance value is low.

  When the voltage Vce between the main terminals of the IGBT 12D further decreases and the detection voltage Vdd between the main terminals falls below the second reference voltage Vref2 of the second comparator 32 and becomes the duration T4 of the reverse recovery operation, the second comparison The output signal of the device 32 becomes low level. This low level output signal becomes high level by the logic inversion circuit 34, and this high level signal is supplied to the gate of the N-channel MOSFET 24 in the turn-on resistance section 23a of the gate drive section 16D via the OR circuit 33. The N-channel MOSFET 24 returns to the ON state, and the resistance value of the turn-on resistance portion 23a returns to the low resistance value in which the gate resistances Rg1 and Rg2 are connected in parallel. Therefore, as shown in FIG. 7, the current path passes through the emitter of the IGBT 12D, the negative and positive sides of the DC power supply 21a, the gate resistances Rg1 and Rg2 of the turn-on resistor 23a, and further through the N-channel MOSFET 22a to the gate of the IGBT 12D. Is formed.

For this reason, since the gate current supplied to the gate of the IGBT 12D is increased, the turn-on of the IGBT 12D is accelerated, and the main-terminal voltage Vce decreases at a large dV / dt and then gradually decreases. The collector current Ic exceeding the value decreases at a relatively small dI / dt and becomes a constant current value.
On the other hand, in the FWD 13U of the upper arm 11U serving as the opposite arm, the fall of the cathode current Ik is suppressed in the period T3 (the minimum value is large), so even if the gate current of the IGBT 12D increases in the period T4, As shown in FIG. 3 (b), the increase in the anode-cathode current Ik becomes gradual, so that the anode-cathode voltage Vak also increases gradually in a state where vibration is suppressed without jumping up, thereby reliably suppressing oscillation. Can do.

  Thus, according to the first embodiment, when the IGBT 12D is shifted from the off state to the turn on state, the voltage Vce between the main terminals of the IGBT 12D is directly detected by the voltage detection unit 17D, and the detected detection voltage between the main terminals is detected. Vdd is supplied to the drive state changing unit 18D. For this reason, the drive mode changing unit 18D can accurately set the drive mode according to the actual change in the main terminal voltage Vce based on the detection voltage Vdd between the main terminals. That is, the drive mode changing unit 18D is simply provided with the first comparator 31 and the second comparator 32, the OR circuit 33, and the logic inversion circuit 34, and without a complicated circuit such as a differentiation circuit. It can be set as a simple structure.

  Then, the main reference of the IGBT 12D when the first reference voltage Vref1 of the first comparator 31 is shifted to the reverse recovery operation of the FWD 13U of the opposing arm after the turn-on initial period T2 when the turn-on resistor 23a has a low resistance value is completed. A reverse recovery operation start period T3 when the voltage Vdd corresponding to the inter-terminal voltage Vce is set and the second reference voltage Vref2 of the second comparator 32 is switched from the low resistance value to the high resistance value is set to the reverse recovery operation start period T3. The voltage is set to the voltage Vdd corresponding to the voltage Vce between the main terminals of the IGBT 12D when the process ends and shifts to the reverse recovery operation continuation period T4. Accordingly, the reverse recovery operation start period T3 of the FWD 13U of the opposite arm can be accurately determined, and the N-channel MOSFET 24 of the turn-on resistor section 23a is turned off only during the reverse recovery operation start period T3. The resistance value can be set to a high resistance value.

  For this reason, the jump of the anode-cathode voltage Vak during the reverse recovery operation of the FWD 13U can be suppressed, and the occurrence of an oscillation state during the reverse recovery operation can be reliably suppressed. Moreover, when the collector current Ic of the IGBT 12D rises to an intermediate level, the reverse recovery operation start period T3 (for example, about 0.2 μs) of the FWD 13U is reached, and the gate current of the IGBT 12D is supplied only during the reverse recovery operation start period T3. Therefore, the influence of the collector current Ic of the IGBT 12D on the decrease in dI / dt is small, and the decrease in the switching loss of the IGBT 12D can be suppressed.

Further, compared to the case of detecting the gate voltage, the method of detecting the main terminal voltage Vce of the IGBT 12D according to the present invention directly detects the state of the IGBT 12D, and therefore more appropriately with respect to the state change of the IGBT 12D. Can be dealt with.
Next, a second embodiment of the gate driving circuit of the voltage driven semiconductor element which is one embodiment of the present invention will be described with reference to FIGS.

In the second embodiment, the driving mode of the gate driving units 16U and 16D is changed without using a resistor.
That is, in the second embodiment, as shown in FIG. 8, the gate driving units 16U and 16D are connected to the N-channel MOSFET 22a, the gate resistor Rg2, and the N-channel MOSFET 24 in the configuration of FIG. The series circuit is omitted, and N-channel MOSFETs 41 and 42 are connected in parallel between the gate resistor Rg1 and the P-channel MOSFET 20b instead.

  Here, the current drive capability of the N-channel MOSFETs 41 and 42 is such that the drain current Id of the N-channel MOSFET 41 has a drain-source voltage Vds of 0 as indicated by a characteristic line L31 shown by a broken line in FIG. 0 [A], and when the drain-source voltage Vds increases from now on, it increases in a parabolic manner up to 0.5 [A] at the start of the increase, and then regardless of the increase in the drain-source voltage Vds The low current drive capability is maintained at 0.5 [A].

  On the other hand, the drain current Id of the N-channel MOSFET 42 is 0 [A] when the drain-source voltage Vds is 0, as indicated by the characteristic line L32 shown by the solid line in FIG. When the source-to-source voltage Vds increases, it suddenly increases to about 2 [A], and then gradually increases with an increase in the drain-source voltage Vds. Compared with the low current driving capability of the N-channel MOSFET 20a. The current drive capacity is set to about 4 times higher.

  A drive mode change signal is input to the gate of the N-channel MOSFET 42 from drive mode change units 18U and 18D having the same configuration as in the first embodiment. For this reason, the N-channel MOSFET 42 is controlled to be in an off state only during a period T3 when the FWD of the opposite arm starts a reverse recovery operation, and is controlled to be in an on state during the other periods T1, T2, and T4. For this reason, when the N-channel MOSFET 42 is in the ON state, the N-channel MOSFET 41 having a low current driving capability and the N-channel MOSFET 42 having a high current driving capability are connected in parallel. Therefore, the characteristic line shown by the solid line in FIG. As indicated by L33, the current drive capability is obtained by adding both current drive capabilities.

According to the second embodiment, the gate resistor Rg1 and the two N-channel MOSFETs 41 and 42 exist as elements that determine the drive current capability for turning on the gates of the IGBTs 12U and 12D in the gate drivers 16U and 16D. .
In the turn-on initial period T2 of the IGBTs 12U and 12D, the N-channel MOSFETs 41 and 42 are both controlled to be turned on, so that the IGBTs 12U and 12D are turned on. The gate current at this time is determined by the resistance component as the sum of the resistance value of the gate resistor Rg1 and the ON resistances of the N-channel MOSFETs 41 and 42 and the voltage related to this resistance component.

The voltage is obtained by subtracting the voltage applied between the gate and emitter of the IGBT 12U or 12D from the power supply voltage of the DC power supply 21a. Since the gate-emitter voltage of the IGBT 12U or 12D changes transiently during on-time, the voltage related to the resistance portion also changes every moment during the on-operation.
Due to this voltage change, a large voltage is initially applied between the drain and source of the N-channel MOSFETs 41 and 42, the operation is in the saturation region, the on-resistance is large, and it is as large as the gate resistance Rg1. .

Therefore, the gate current is determined by the ON resistance (= drive capability) of the N-channel MOSFETs 41 and 42 and the gate resistance Rg1. Therefore, the gate current can be differentiated by the difference between the sum of the current drive capabilities of the N-channel MOSFETs 41 and 42 and the current drive capability of the N-channel MOSFET 41 alone.
Therefore, the N-channel MOSFET 42 is turned off only in the period T3 when the FWD of the opposing arm starts the reverse recovery operation in the drive mode changing units 18U and 18D, and the N-channel MOSFET 42 is turned on in the other periods T1, T2, and T4. Thus, by reducing the gate current only during the period T3 when the FWD of the opposite arm starts the reverse recovery operation, the reverse recovery of the FWD is suppressed while suppressing the reduction of the switching loss of the IGBTs 12U and 12D as in the first embodiment described above. Generation of vibration during operation can be suppressed.

  In addition, in the second embodiment, the driving mode of the gate driving units 16U and 16D can be changed by turning on / off the N-channel MOSFET 42 without providing a parallel resistance. Since the element configuration area on the substrate can be reduced as compared with the resistor, the chip size of the gate drive units 16U and 16D can be reduced to reduce the size, and the entire gate drive circuit can also be reduced in size. it can.

Next, a third embodiment of the gate drive circuit of the voltage driven semiconductor element which is one embodiment of the present invention will be described with reference to FIG.
In the third embodiment, the gate driving units 16U and 16D are configured without using a resistance element.
That is, in the third embodiment, as shown in FIG. 10, in the first embodiment described above, the gate resistance Rg1 of the turn-on resistance portion 23a has a small current drive capability and operates as a resistor. Replaced with the channel MOSFET 51, the series circuit of the N-channel MOSFET 24 and the gate resistor Rg2 is replaced with the N-channel MOSFET 52 having a large current driving capability, and the turn-off resistor 23b operates as a resistor with a large current driving capability, and the gate is connected to the drain The P channel MOSFET 53 is replaced.

Then, the gate of the N-channel MOSFET 52 is connected to the drive mode change units 18U and 18D, and the drive mode change signal is supplied.
According to the third embodiment, the N-channel MOSFET 52 of the turn-on resistance unit 23a is controlled to be turned on by the drive mode changing unit 18U or 18D in the above-described periods T1, T2, and T4 in FIG. 3, and the FWD 13D or Only in the period T3 when 13U starts the reverse recovery operation is controlled to be in the OFF state.

Therefore, a large gate current can be supplied to the IGBT 12U or 12D in the periods T2 and T4, and the gate current can be reduced in the period T3, and the switching of the IGBTs 12U and 12D can be performed as in the first and second embodiments described above. It is possible to suppress the occurrence of vibration during the FWD reverse recovery operation while suppressing loss reduction.
In the third embodiment, the turn-on resistor 23a is composed of N-channel MOSFETs 51 and 52, and similarly the turn-off resistor 23b is composed of a P-channel MOSFET 53. Therefore, the turn-on gate resistor and the turn-off gate resistor The gate driving units 16U and 16D can be configured without using. For this reason, the configuration of the gate driving units 16U and 16D can be further reduced as compared with the first and second embodiments, and the chip size can be reduced.

  In the first to third embodiments, the case where the gate driving circuit of the voltage-driven semiconductor element which is one embodiment of the present invention is applied to a three-phase inverter has been described. However, the present invention is not limited to this. However, it can be applied to various power conversion devices such as a single-phase inverter and a chopper circuit.

  DESCRIPTION OF SYMBOLS 10 ... DC power supply, 11U ... Upper arm, 11D ... Lower arm, 12U, 12D ... IGBT, 13U, 13D ... FWD, 14U, 14D ... Gate drive circuit, 15 ... Load, 16U, 16D ... Gate drive part, 17U, 17D ... Voltage detector, 18U, 18D ... Driving mode changer, 21a, 21b ... DC power supply, 22a ... N-channel MOSFET, 22b ... P-channel MOSFET, 23a ... Turn-on resistor, 23b ... Turn-off resistor, Rg1, Rg2 ... Gate resistance , 24 ... N-channel MOSFET, 31 ... 1st comparator, 32 ... 2nd comparator, 33 ... OR circuit, 34 ... Logical inversion circuit, 41, 42 ... N-channel MOSFET, 51, 52 ... N-channel MOSFET, 53 ... P-channel MOSFET

Claims (5)

A voltage-driven semiconductor element gate drive circuit for driving a gate of a voltage-driven semiconductor element in which freewheeling diodes are connected in reverse parallel,
A gate driver capable of driving the gate of the voltage-driven semiconductor element in a different gate driving mode at the time of turn-on;
A voltage detector for detecting a voltage between main terminals of the voltage-driven semiconductor element;
A gate driving circuit for a voltage-driven semiconductor element, comprising: a driving mode changing unit that changes a gate driving mode in the gate driving unit based on a voltage detected by the voltage detecting unit.   The gate driving unit is connected in series, and a connection point is connected to the gate of the voltage-driven semiconductor element, and the high-potential-side semiconductor switching element in series is connected in series with the semiconductor switching element. 2. The gate of the voltage-driven semiconductor element according to claim 1, further comprising a gate resistance selection unit that selects a different resistance value according to a gate drive mode from the drive mode change unit connected to the gate Driving circuit.   The gate driving unit is connected in series, and a connection point is connected to the gate of the voltage-driven semiconductor element, and the high-potential-side semiconductor switching element of the pair of semiconductor switching elements is parallel to the gate driving unit. 2. The voltage according to claim 1, further comprising: a semiconductor element having a current driving capability larger than that of the semiconductor switching element connected to the first switching element and driven by the driving mode changing unit. A gate driving circuit of a driving type semiconductor element.   The driving state changing unit includes a first comparing unit that outputs a high-level comparison signal when the voltage between the main terminals detected by the voltage detecting unit is equal to or higher than a first reference voltage, and the voltage between the main terminals is the first voltage. A second comparison unit that outputs a low-level comparison signal when the voltage is equal to or higher than a second reference voltage lower than one reference voltage, and a logical sum of the comparison signal of the first comparator and the comparison signal of the second comparison unit. 4. The gate drive circuit for a voltage driven semiconductor device according to claim 1, further comprising a circuit for generating a signal.   The first comparison unit outputs a high-level comparison signal when the voltage-driven semiconductor element is in an off period and a turn-on initial period, and the second comparison unit is configured to output the off period, the turn-on initial period, and the turn-on initial period. A high-level comparison signal is output when it is the reverse recovery operation start period of the freewheeling diode, and a low-level comparison signal is output when the reverse recovery operation continuation period is after the reverse recovery operation start period. 5. The gate drive circuit for a voltage-driven semiconductor device according to claim 4, wherein

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