JP2004241734A - Semiconductor module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make a semiconductor module compact and reduce inductance in the module as much as possible. <P>SOLUTION: Conductor patterns 2a and 2b are formed on the surface of an insulation circuit board 1. A semiconductor chip 3 is provided in a manner that a drain formed on its bottom is in contact with the conductor pattern 2a and a source formed on its upper surface is in contact with a heat spreader 5. A semiconductor chip 4 is provided in a manner that a source formed on its upper surface is in contact with the conductor pattern 2b and a source formed on its bottom is in contact with a heat spreader 6. A U electrode 23 is in contact with the heat spreaders 5 and 6. Furthermore, a P electrode 21 is in contact with the conductor pattern 2a and an N electrode 22 is in contact with the conductor pattern 2b. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor module, and more particularly, to a power semiconductor module that flows a large current.
[0002]
[Prior art]
Semiconductor modules including one or more semiconductor elements are widely used in various fields. A power semiconductor module for flowing a large current has been put to practical use, for example, as an inverter circuit or a power conversion circuit.
[0003]
FIG. 4 is a diagram illustrating a configuration of an example of an existing semiconductor module. Note that, for example, an inverter circuit shown in FIG. 5 is formed in this semiconductor module. Here, the inverter circuit shown in FIG. 5 includes a U-phase circuit 111, a V-phase circuit 112, and a W-phase circuit 113, and generates a three-phase AC according to an instruction from a control circuit (not shown). The U-phase circuit 111, the V-phase circuit 112, and the W-phase circuit 113 are each configured to include a pair of transistors (an upper-arm transistor and a lower-arm transistor) connected in series to each other. I have. FIG. 4 illustrates one of the U-phase circuit 111, the V-phase circuit 112, and the W-phase circuit 113 (for example, the U-phase circuit 111).
[0004]
4, the semiconductor chips 101 and 102 are mounted on the upper surface of the insulating circuit board 103. Here, upper-arm transistors and lower-arm transistors shown in FIG. 5 are formed on the semiconductor chips 101 and 102, respectively. Bonding wires 104 are provided between the P electrode and the semiconductor chip 101, between the semiconductor chip 101 and the U electrode, between the U electrode and the semiconductor chip 102, and between the semiconductor chip 102 and the N electrode. They are connected by 105, 106 and 107. Here, the main current of the semiconductor module flows as shown by an arrow in FIG.
[0005]
By the way, in the power semiconductor module, it is important to reduce the parasitic inductance in the module as the switching frequency increases. Conventionally, there has been known a technique for reducing such inductance by devising a path through which a main current flows in a module. In this case, the module is designed so that main currents flow in mutually opposite directions in paths formed in parallel with each other, and changes in magnetic flux generated in the paths formed in parallel with each other cancel each other out, so that the mutual inductance is reduced. Suppression is achieved (for example, see Patent Documents 1 and 2).
[0006]
In the power semiconductor module shown in FIG. 4, bonding wires 104 and bonding wires 107 are formed in parallel or substantially parallel to each other, and currents flowing in opposite directions flow through these bonding wires. Further, the bonding wires 105 and the bonding wires 106 are formed parallel or substantially parallel to each other, and currents in opposite directions flow through these bonding wires.
[0007]
[Patent Document 1]
JP-A-10-74886 (FIGS. 1, 2 and paragraphs 0016 to 0019 of the specification)
[0008]
[Patent Document 2]
JP 2001-7140 A (FIG. 1 and paragraphs 0051 to 0056 of the specification)
[0009]
[Problems to be solved by the invention]
However, even if the current path is devised as described above, there is a limit in suppressing the inductance of the bonding wire.
It is an object of the present invention to minimize the inductance in a semiconductor module. Another object of the present invention is to reduce the size of a semiconductor module.
[0010]
[Means for Solving the Problems]
The semiconductor module of the present invention includes an insulated circuit board having a first conductor pattern and a second conductor pattern formed on the same surface, a first electrode provided to contact the first conductor pattern, A second electrode provided in contact with the second conductor pattern, a main current input area on one surface and a main current output area on the other surface, and the main current input area is the first conductor; A first semiconductor chip mounted on the insulated circuit board so as to be in contact with the pattern; a main current input region on one surface and a main current output region on the other surface; The second semiconductor chip, the main current output area of the first semiconductor chip, and the main current input area of the second semiconductor chip mounted on the insulated circuit board so as to contact the conductive pattern of A third electrode, which connects.
[0011]
In the semiconductor module, a current input from the first electrode is guided to the third electrode via the first conductor pattern and the first semiconductor chip, and is output to the outside from the third electrode. On the other hand, a current input from the third electrode is guided to the second electrode via the second semiconductor chip and the second conductor pattern, and is output from the second electrode to the outside. Here, the first electrode and the second electrode are provided so as to be in contact with the first conductor pattern and the second conductor pattern, respectively. Further, the first semiconductor chip and the second semiconductor chip are mounted on the insulated circuit board so as to contact the first conductor pattern and the second conductor pattern, respectively. That is, in this semiconductor module, there is no bonding wire in the path where the main current flows. Therefore, no wiring inductance of the bonding wire occurs. Further, currents flow in opposite directions in the current path from the first electrode to the third electrode and in the current path from the third electrode to the second electrode, so that the mutual inductance is canceled.
[0012]
In the semiconductor module, the third electrode may be arranged to be in contact with a main current output region of the first semiconductor chip and a main current input region of the second semiconductor chip. According to this configuration, since the third electrode is located above each semiconductor chip, it is not necessary to secure an area for providing the third electrode on the insulated circuit board, and the module can be downsized.
[0013]
In the semiconductor module, a main current output region of the first semiconductor chip and a main current input region of the second semiconductor chip are respectively connected to the third electrode via a conductive heat spreader. You may do so. In this configuration, not only the heat radiation effect is improved, but also the force applied to the third electrode is less likely to be transmitted to the first and second semiconductor chips.
[0014]
A semiconductor module according to another aspect of the present invention includes an insulated circuit board having a conductor pattern formed on a surface thereof, a first electrode provided to be in contact with the conductor pattern, and a main current input region provided on one surface. A semiconductor chip mounted on the insulated circuit board such that one of the main current input area and the main current output area is in contact with the conductor pattern, and a main current of the semiconductor chip is provided. A second electrode electrically connected to the other of the input region and the main current output region. The first electrode and the second electrode are formed so as to extend in parallel with each other and in a direction perpendicular or substantially perpendicular to the insulated circuit board.
[0015]
Also in this semiconductor module, since there is no bonding wire in the path where the main current flows, no wiring inductance of the bonding wire occurs. Further, since each electrode is formed so as to extend in a vertical direction or a substantially vertical direction with respect to the insulated circuit board, the size of the module can be reduced. In addition, since the current flowing through each electrode is in the opposite direction, the mutual inductance is canceled.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing a configuration of a semiconductor module according to an embodiment of the present invention. Here, for example, an inverter circuit shown in FIG. 5 is formed in this semiconductor module. FIG. 1 illustrates one of the U-phase circuit 111, the V-phase circuit 112, and the W-phase circuit 113 (for example, the U-phase circuit 111) illustrated in FIG. 2A and 2B are views of the semiconductor module shown in FIG. 1 as viewed from the side.
[0017]
The insulated circuit board 1 is a circuit board for forming the inverter circuit shown in FIG. 5, and has a conductor pattern formed on the surface thereof. Here, a conductor pattern (first conductor pattern) 2a, a conductor pattern (second conductor pattern) 2b, and a conductor pattern 2c that are electrically insulated from each other are formed. Although only shown in FIG. 3, the conductor pattern 2d is also formed.
[0018]
A semiconductor chip (first semiconductor chip) 3 and a semiconductor chip (second semiconductor chip) 4 are mounted on the upper surface of the insulated circuit board 1. Here, source pads (main current output regions) 11, gate pads 12, and sense pads 13 are formed on the surfaces of the semiconductor chips 3, 4, respectively, as shown in FIG. The sense pad 13 is an electrode pad for extracting outputs of various sensors (for example, temperature sensors, etc.) included in the semiconductor chips 3 and 4 to the outside. On the other hand, drain electrodes (main current input regions) 14 are formed on the back surfaces of the semiconductor chips 3 and 4, respectively.
[0019]
The semiconductor chip 3 is attached to the insulated circuit board 1 with the surface on which the source pads 11 are formed facing upward. At this time, the semiconductor chip 3 is attached to the insulated circuit board 1 such that the drain electrode 14 formed on the back surface thereof contacts the conductor pattern 2a. On the other hand, the semiconductor chip 4 is attached to the insulated circuit board 1 with the surface on which the source pads 11 are formed facing downward. At this time, the semiconductor chip 4 is attached to the insulated circuit board 1 such that the source pad 11 contacts the conductor pattern 2b, the gate pad 12 contacts the conductor pattern 2c, and the sense pad 13 contacts the conductor pattern 2d. In this case, the conductor patterns 2a to 2d and the corresponding pads or electrodes of the semiconductor chips 3, 4 are in contact with each other by, for example, soldering.
[0020]
Note that “contact” basically means that metals are brought into contact with each other by brazing or the like, but it also includes that the metals are brought into contact by directly pressing each other. Further, as a filler material used for “brazing”, “solder” is used in the embodiment, but is not limited to this, and for example, silver brazing or the like may be used.
[0021]
The P electrode (first electrode) 21 is provided so as to contact the conductor pattern 2a. On the other hand, the N electrode (second electrode) 22 is provided to be in contact with the conductor pattern 2b. The P electrode 21 and the N electrode 22 are fixed, for example, such that a part thereof is embedded in the case of the semiconductor module, and correspond to the conductor pattern 2a when the module is assembled by fitting the case. , 2b. The P electrode 21 and the N electrode 22 are provided so as to extend in a direction perpendicular or substantially perpendicular to the insulated circuit board 1, respectively.
[0022]
Heat spreaders 5, 6 are attached to the upper portions of the semiconductor chips 3, 4, respectively. At this time, the heat spreader 5 is attached so as to contact the source pad 11 of the semiconductor chip 3 by soldering. On the other hand, the heat spreader 6 is attached so as to contact the drain electrode 14 of the semiconductor chip 4 by soldering. The heat spreaders 5 and 6 are formed of a metal having both high electrical conductivity and high thermal conductivity.
[0023]
The U electrode (third electrode) 23 is attached by soldering so as to contact both the heat spreaders 5 and 6. Here, the U electrode 23 is formed so as to extend in a direction perpendicular to or substantially perpendicular to the insulated circuit board 1 like the P electrode 21 and the N electrode 22. The U electrode 23 is provided with a play portion 23a in order to make it difficult for the force applied from the outside to be transmitted to the semiconductor chips 3 and 4.
[0024]
The gate electrode 24 is connected to the gate pad 12 of the semiconductor chip 3 via a bonding wire. The gate electrode 25 is connected to the conductor pattern 2c via a bonding wire. Although not shown for the sake of clarity, the sense pads 13 and the conductor patterns 2d of the semiconductor chip 3 are connected to sense electrodes (not shown) via bonding wires.
[0025]
The semiconductor module having the above configuration operates as follows. That is, the upper arm transistor formed on the semiconductor chip 3 is driven by a gate control signal provided via the gate electrode 24. The lower arm transistor formed on the semiconductor chip 4 is driven by a gate control signal provided via the gate electrode 25.
[0026]
When the upper arm transistor formed on the semiconductor chip 3 is controlled to be turned on, the current input from the P electrode 21 is applied to the conductor pattern 2a, the drain electrode 14 of the semiconductor chip 3, and the semiconductor chip 3 (for the upper arm). Transistor), the source pad 11 of the semiconductor chip 3, and the heat spreader 5, are guided to the U electrode 23, and output from the U electrode 23. That is, this current flows in the direction indicated by arrow A in FIG. On the other hand, when the transistor for the lower arm formed on the semiconductor chip 4 is controlled to be turned on, the current input from the U electrode 23 is supplied to the heat spreader 6, the drain electrode 14 of the semiconductor chip 4, and the semiconductor chip 4 (the lower arm). Transistor), the source pad 11 of the semiconductor chip 4, and the N-electrode 22 via the conductor pattern 2 b, and output from the N-electrode 22. That is, this current flows in the direction indicated by arrow B in FIG.
[0027]
As described above, in the semiconductor module of the embodiment, since the bonding wire is not used in the path where the main current flows, the wiring inductance of the bonding wire, which has been a problem in the related art, can be eliminated. The connection between the gate electrode 24 and the gate pad 12 of the semiconductor chip 3 and the connection between the gate electrode 25 and the conductor pattern 2c are respectively made by bonding wires. Since the current is small and the effect of the inductance generated in this path is small, it is not worth eliminating the inductance of the bonding wire. Similarly, the path connecting the sense pads 13 of the semiconductor chips 3 and 4 to the electrodes (not shown) has little effect on the inductance, and therefore, it is not worth eliminating the inductance of the bonding wire.
[0028]
In addition, the path through which the current flows through the semiconductor chip 3 and the path through which the current flows through the semiconductor chip 4 are parallel to each other, and the currents flow in opposite directions through these paths. The inductance cancels out.
Further, since the U electrode 23 is provided above the semiconductor chips 3 and 4, there is no need to secure an area for mounting the U electrode 23 on the insulated circuit board 1, and the module can be downsized. Further, the P electrode 21, the N electrode 22, and the U electrode 23 are formed so as to extend in a direction perpendicular or substantially perpendicular to the insulated circuit board 1, which also contributes to downsizing of the module.
[0029]
In the embodiment shown in FIGS. 1 and 2, the heat spreaders 5, 6 are provided between the semiconductor chips 3, 4 and the U electrode 23, but the present invention is not limited to this configuration. That is, in the present invention, the heat spreaders 5 and 6 are not indispensable components, and the U electrodes 23 may directly contact the semiconductor chips 3 and 4 by soldering or the like. The heat spreaders 5 and 6 not only improve the heat radiation effect, but also make the force applied to the U electrode 23 difficult to be transmitted to the semiconductor chips 3 and 4, and the withstand voltage between the U electrode 23 and the conductor patterns 2a and 2b. (Securing the insulation distance). Therefore, when these problems do not occur, or when these problems are solved by another measure, it is not necessary to provide the heat spreaders 5, 6.
[0030]
Further, in the above embodiment, the MOS transistor is formed on each semiconductor chip, but the present invention is not limited to this. That is, a semiconductor element (for example, IGBT) other than the MOS transistor may be formed on each semiconductor chip.
[0031]
Furthermore, in the above embodiment, the inverter circuit is formed in the semiconductor module, but the present invention is not limited to this.
Further, the effect of the present invention can be obtained in a semiconductor module incorporating one semiconductor chip. That is, for example, even when attention is paid to the semiconductor chip 3 shown in FIG. 2A, the main current flows so as to cancel the mutual inductance. Also in this case, it is not necessary to secure an area for disposing the U electrode 23 on the insulated circuit board 1.
[0032]
【The invention's effect】
According to the present invention, since the bonding wire is not used in the path where the main current flows, the wiring inductance of the bonding wire is eliminated. In addition, since the configuration is such that main currents flow in opposite directions via paths parallel to each other, mutual inductance is canceled. Furthermore, since the area for mounting the electrodes on the insulated circuit board is small, the size of the module can be reduced.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of a semiconductor module according to an embodiment of the present invention.
FIG. 2 is a side view of the semiconductor module shown in FIG. 1;
FIG. 3 is a diagram illustrating a method of attaching a semiconductor chip.
FIG. 4 is a diagram illustrating a configuration of an example of an existing semiconductor module.
FIG. 5 is a diagram illustrating an example of a circuit formed in a semiconductor module.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Insulated circuit board 2a-2c Conductor pattern 3, 4 Semiconductor chip 5, 6 Heat spreader 11 Source pad 14 Drain electrode 21 P electrode 22 N electrode 23 U electrode

Claims (4)

An insulated circuit board having a first conductor pattern and a second conductor pattern formed on the same surface;
A first electrode provided so as to contact the first conductor pattern;
A second electrode provided to contact the second conductor pattern;
A first semiconductor having a main current input region on one surface and a main current output region on the other surface, the first semiconductor being attached to the insulated circuit board such that the main current input region contacts the first conductor pattern; Chips and
A second semiconductor attached to the insulated circuit board such that a main current input area is provided on one surface and a main current output area is provided on the other surface, and the main current output area is in contact with the second conductor pattern; Chips and
A third electrode electrically connected to the main current output region of the first semiconductor chip and the main current input region of the second semiconductor chip;
A semiconductor module having: The semiconductor module according to claim 1, wherein:
The third electrode is arranged so as to be in contact with a main current output region of the first semiconductor chip and a main current input region of the second semiconductor chip. The semiconductor module according to claim 1, wherein:
The main current output area of the first semiconductor chip and the main current input area of the second semiconductor chip are respectively connected to the third electrode via a conductive heat spreader. An insulated circuit board having a conductor pattern formed on its surface,
A first electrode provided to contact the conductor pattern;
A main current input area is provided on one surface and a main current output area is provided on the other surface, and the main current input area and the main current output area are attached to the insulated circuit board such that one of the main current input area and the main current output area contacts the conductor pattern. Semiconductor chip,
A second electrode electrically connected to the other of the main current input region and the main current output region of the semiconductor chip;
A semiconductor module, wherein the first electrode and the second electrode are formed so as to extend in parallel to each other and in a direction perpendicular or substantially perpendicular to the insulated circuit board.

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