WO2020144907A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
WO2020144907A1
WO2020144907A1 PCT/JP2019/040223 JP2019040223W WO2020144907A1 WO 2020144907 A1 WO2020144907 A1 WO 2020144907A1 JP 2019040223 W JP2019040223 W JP 2019040223W WO 2020144907 A1 WO2020144907 A1 WO 2020144907A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductor plate
joint
semiconductor device
plate
semiconductor element
Prior art date
Application number
PCT/JP2019/040223
Other languages
French (fr)
Japanese (ja)
Inventor
小川　泰弘
崇功 川島
明徳 榊原
Original Assignee
トヨタ自動車株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by トヨタ自動車株式会社 filed Critical トヨタ自動車株式会社
Priority to JP2020565583A priority Critical patent/JP7192886B2/en
Publication of WO2020144907A1 publication Critical patent/WO2020144907A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the upper surface 42a of the second lower conductor plate 42 and the second main electrode 40c of the second semiconductor element 40 are bonded to each other via the solder layer 41.
  • the second lower conductor plate 42 is electrically and thermally connected to the second semiconductor element 40.
  • the first main electrode 40b of the second semiconductor element 40 and the lower surface 44b of the second conductor spacer 44 are joined to each other through the solder layer 43, and the upper surface 44a of the second conductor spacer 44 is connected to the upper surface 44a.
  • the lower surface 46b of the second upper conductor plate 46 is joined to each other via the solder layer 45.
  • the second upper conductor plate 46 is electrically and thermally connected to the second semiconductor element 40 via the second conductor spacer 44.
  • the joining between these constituent members is not limited to the solder layer, and the joining may be performed via another type of joining layer having conductivity.
  • the second lower conductor plate 42 is an example of the third conductor plate in the technique disclosed in the present specification
  • the second upper conductor plate 46 is the fourth conductor plate in the technique disclosed in the present specification. This is an example.
  • the first power terminal 14 and the second power terminal 15 are respectively connected to the high potential side and the low potential side of an external DC power source (not shown), and the tip portion 16a of the third power terminal 16 is connected to a load (for example, a motor). ) Is connected to.
  • the semiconductor device 10 can form, for example, a part of the inverter circuit.
  • the 3rd electric power terminal 16 constitutes a part of joint structure 30, and is an example of a joint member in the art indicated by this specification.
  • the third power terminal 16 is also referred to as the joint member 16.
  • a semiconductor device 100 of a second embodiment will be described with reference to FIG. As shown in FIG. 6, the semiconductor device 100 of the second embodiment is different from the semiconductor device 10 of the first embodiment in the structure of the first upper conductor plate 126, the second lower conductor plate 142, and the joint structure 130. Has been done. Since the configuration other than the second lower conductor plate 142 and the joint structure 130 can be configured in the same manner as in the first embodiment, redundant description will be omitted here.
  • the second joint portion 48 is joined to the base end portion 216b of the third power terminal 216 via the second joint solder layer 247.
  • the area in which the second joint solder layer 247 contacts the second joint portion 48 is larger than the area in which the second joint solder layer 247 contacts the base end portion 216b.
  • the second joint solder layer 247 forms a good fillet shape, and the second joint portion 48 and the base end portion 216b of the third power terminal 216 are firmly joined.
  • the second joint solder layer 247 is also not particularly limited, but its fillet angle may be an acute angle (that is, less than 90 degrees).
  • the intermediate plate-shaped portion 316b3 extends between the portion 316b2 and the portion 316b2. Further, the third power terminal 316 has a bent portion 316w at a boundary between the first plate-shaped portion 316b1 and the intermediate plate-shaped portion 316b3 and a boundary between the second plate-shaped portion 316b2 and the intermediate plate-shaped portion 316b3. have. As an example, the first plate-shaped portion 316b1 and the second plate-shaped portion 316b2 are bent in directions opposite to each other with respect to the intermediate plate-shaped portion 316b3.
  • the third power terminal 316 includes a boundary between the first plate-shaped portion 316b1 and the intermediate plate-shaped portion 316b3, a second plate-shaped portion 316b2, and an intermediate plate-shaped portion 316b3.
  • the intermediate plate-shaped portion 316b3 may also have at least one (here, two) bent portion 316w.
  • constrictions may be provided at both ends between the tip end portion 316a and the base end portion 316b of the intermediate plate-shaped portion 316b3.
  • the first lower conductor plate 22 and the second lower conductor plate 42 are provided on the common insulating substrate 334, and the first upper conductor plate 26 and the second upper conductor plate 46 are provided. It is provided on the common insulating substrate 338.
  • the conductor plates 22, 26, 42, 46 may be provided on different insulating substrates, and at least one of the plurality of conductor plates 22, 26, 42, 46 may be an insulating substrate. It may be provided above.
  • the joint member 417 connects the first upper conductor plate 26 and the second lower conductor plate 42 inside the sealing body 18. At the same time, a part of the joint member 417 is located outside the sealing body 18. As an example, a part of the joint member 417 projects from the second end surface 18d of the sealing body 18. However, a part of the joint member 417 does not need to project, and may be exposed from the sealing body 18 (the second end surface 18d in this embodiment). The joint member 417 in this embodiment does not have to function as a terminal outside the sealing body 18.

Abstract

This semiconductor device disclosed by the present specification comprises: a first semiconductor element and a second semiconductor element; and a sealing body that seals the first semiconductor element and the second semiconductor element. The semiconductor device comprises a first conductor plate, a second conductor plate, a third conductor plate, and a fourth conductor plate. The first conductor plate and the second conductor plate are facing sandwiching the first semiconductor element, each being electrically connected to the first semiconductor element inside the sealing body. The third conductor plate and the fourth conductor plate are facing sandwiching the second semiconductor element, each being electrically connected to the second semiconductor element inside the sealing body. Also, the semiconductor device comprises a joint structure that electrically connects the second conductor plate and the third conductor plate to each other inside the sealing body, and that joint structure includes at least one joint member, with a portion of the joint member positioned outside the sealing body.

Description

半導体装置Semiconductor device
　本明細書が開示する技術は、半導体装置に関する。 The technology disclosed in this specification relates to a semiconductor device.
　特開２０１７－１５９３３５号公報及び米国特許出願公開第２０１３／０２４９０６９号明細書に、半導体装置が開示されている。これらの半導体装置は、第１半導体素子及び第２半導体素子と、第１半導体素子及び第２半導体素子を封止する封止体と、第１半導体素子及び第２半導体素子をそれぞれ挟んで対向する第１導体板、第２導体板、第３導体板及び第４導体板とを備えている。封止体の内部において、第１導体板及び第２導体板は、第１半導体素子に電気的に接続されており、第３導体板及び第４導体板は第３導体板及び第４導体板に電気的に接続されている。そして、第２導体板と第３導体板は、封止体の内部において継手構造を介して互いに接続されている。 A semiconductor device is disclosed in Japanese Patent Application Laid-Open No. 2017-159335 and US Patent Application Publication No. 2013/0249069. These semiconductor devices face the first semiconductor element and the second semiconductor element, the sealing body that seals the first semiconductor element and the second semiconductor element, and the first semiconductor element and the second semiconductor element, respectively. A first conductor plate, a second conductor plate, a third conductor plate, and a fourth conductor plate are provided. Inside the sealing body, the first conductor plate and the second conductor plate are electrically connected to the first semiconductor element, and the third conductor plate and the fourth conductor plate are the third conductor plate and the fourth conductor plate. Is electrically connected to. The second conductor plate and the third conductor plate are connected to each other via a joint structure inside the sealing body.
　上記した継手構造を備える半導体装置では、継手構造が存在する分だけ、半導体装置を構成する部品点数が増加し、これによって工数が増加するといった製造工程の煩雑化に繋がるおそれがある。本明細書では、継手構造を備える半導体装置であっても、製造工程が煩雑化することを抑制し得る技術を提供する。 In a semiconductor device having the above-mentioned joint structure, the number of parts constituting the semiconductor device increases due to the existence of the joint structure, which may lead to complication of the manufacturing process such as an increase in man-hours. The present specification provides a technique capable of suppressing complication of a manufacturing process even in a semiconductor device having a joint structure.
　本明細書が開示する半導体装置は、第１半導体素子及び第２半導体素子と、第１半導体素子及び第２半導体素子を封止する封止体とを備える。半導体装置は、第１導体板、第２導体板、第３導体板及び第４導体板を備える。第１導体板及び第２導体板は、第１半導体素子を挟んで対向するとともに、各々が封止体の内部で第１半導体素子へ電気的に接続されている。第３導体板及び第４導体板は、第２半導体素子を挟んで対向するとともに、各々が封止体の内部で第２半導体素子へ電気的に接続されている。また、半導体装置は、封止体の内部で第２導体板と第３導体板とを互いに電気的に接続する継手構造を備えており、その継手構造は、少なくとも一つの継手部材を含み、該継手部材の一部は封止体の外部に位置する。 The semiconductor device disclosed in the present specification includes a first semiconductor element and a second semiconductor element, and a sealing body that seals the first semiconductor element and the second semiconductor element. The semiconductor device includes a first conductor plate, a second conductor plate, a third conductor plate, and a fourth conductor plate. The first conductor plate and the second conductor plate are opposed to each other with the first semiconductor element interposed therebetween, and are electrically connected to the first semiconductor element inside the sealing body. The third conductor plate and the fourth conductor plate are opposed to each other with the second semiconductor element interposed therebetween, and are electrically connected to the second semiconductor element inside the sealing body. Further, the semiconductor device includes a joint structure for electrically connecting the second conductor plate and the third conductor plate to each other inside the sealing body, and the joint structure includes at least one joint member, A part of the joint member is located outside the sealing body.
　上記した半導体装置では、第２導体板及び第３導体板を接続する継手構造が、少なくとも一つの継手部材を含んでおり、その継手部材の一部が封止体の外部に位置する。このような構成によると、封止体を形成する封止工程において、継手部材を封止体の外部から支持することができ、封止構造を精度よく形成しやすい。また、特に限定されないが、継手部材を、封止体の外部に位置する他の構成部材（例えば電力端子等）とともに、一つの部材（いわゆるリードフレーム）として用意することができる。これにより、半導体装置の製造工程が煩雑化することが抑制される。 In the semiconductor device described above, the joint structure that connects the second conductor plate and the third conductor plate includes at least one joint member, and a part of the joint member is located outside the sealing body. With such a configuration, in the sealing step of forming the sealing body, the joint member can be supported from the outside of the sealing body, and the sealing structure can be easily formed with high accuracy. In addition, although not particularly limited, the joint member can be prepared as one member (so-called lead frame) together with other constituent members (for example, power terminals etc.) located outside the sealing body. This prevents the manufacturing process of the semiconductor device from becoming complicated.
実施例１の半導体装置１０を示す平面図。なお、各図面において、Ｘ方向は、二つの半導体素子２０、４０が並ぶ方向を示しており、各々の導体板２２、２６、４２、４６に対して平行である。Ｙ方向は、Ｘ方向に対して垂直であるとともに、各々の導体板２２、２６、４２、４６に対して平行である。Ｚ方向は、Ｘ方向及びＹ方向に対して垂直であり、半導体素子２０、４０及び導体板２２、２６、４２、４６のそれぞれの厚み方向に対して平行である。第１下側導体板２２と第１上側導体板２６は、Ｚ方向において対向しており、第２下側導体板４２と第２上側導体板４６も、Ｚ方向において対向している。また、第１下側導体板２２と第２下側導体板４２は、Ｘ方向において横並びに配置されており、第１上側導体板２６と第２上側導体板４６も、Ｘ方向において横並びに配置されている。3 is a plan view showing the semiconductor device 10 of Example 1. FIG. In each drawing, the X direction indicates the direction in which the two semiconductor elements 20 and 40 are arranged, and is parallel to the respective conductor plates 22, 26, 42, and 46. The Y direction is perpendicular to the X direction and parallel to each conductor plate 22, 26, 42, 46. The Z direction is perpendicular to the X direction and the Y direction, and is parallel to the respective thickness directions of the semiconductor elements 20, 40 and the conductor plates 22, 26, 42, 46. The first lower conductor plate 22 and the first upper conductor plate 26 face each other in the Z direction, and the second lower conductor plate 42 and the second upper conductor plate 46 also face each other in the Z direction. The first lower conductor plate 22 and the second lower conductor plate 42 are arranged side by side in the X direction, and the first upper conductor plate 26 and the second upper conductor plate 46 are also arranged side by side in the X direction. Has been done. 半導体装置１０の内部構造を示す平面図。但し、内部構造を明確に示すために、封止体１８は破線で表記し、導体スペーサ２４、４４は省略する。3 is a plan view showing the internal structure of the semiconductor device 10. FIG. However, in order to clearly show the internal structure, the sealing body 18 is shown by a broken line, and the conductor spacers 24 and 44 are omitted. 図１のＩＩＩ－ＩＩＩ線における断面図であって、半導体装置１０の内部構造を示す。FIG. 3 is a cross-sectional view taken along the line III-III in FIG. 1, showing an internal structure of the semiconductor device 10. 半導体装置１０の電子回路図。3 is an electronic circuit diagram of the semiconductor device 10. FIG. 半導体装置１０の一使用例を示す斜視図。3 is a perspective view showing an example of use of the semiconductor device 10. 実施例２の半導体装置１００の内部構造を示す断面図。FIG. 6 is a cross-sectional view showing the internal structure of the semiconductor device 100 of Example 2. 実施例３の半導体装置２００の内部構造を示す断面図。FIG. 6 is a cross-sectional view showing the internal structure of a semiconductor device 200 of Example 3. 実施例４の半導体装置３００の内部構造を示す平面図。内部構造を明確に示すために、封止体１８及び上側導体板２６、４６は破線で表記し、導体スペーサ２４、４４、絶縁基板３３４、３３８、第３下側導体板３３５及び第３上側導体板３３９は省略する。なお、図１０、１２、１４、１６、１８についても、図８と同様に図示する。6 is a plan view showing the internal structure of a semiconductor device 300 of Example 4. FIG. In order to clearly show the internal structure, the sealing body 18 and the upper conductor plates 26 and 46 are indicated by broken lines, and the conductor spacers 24 and 44, the insulating substrates 334 and 338, the third lower conductor plate 335 and the third upper conductor. The plate 339 is omitted. Note that FIGS. 10, 12, 14, 16, and 18 are also illustrated in the same manner as FIG. 8. 図８のＩＸ－ＩＸ線における断面図。Sectional drawing in the IX-IX line of FIG. 第３電力端子３１６の一変形例を示す平面図。The top view which shows the modification of the 3rd power terminal 316. 図１０のＸＩ－ＸＩ線における断面図。Sectional drawing in the XI-XI line of FIG. 第３電力端子３１６の一変形例を示す平面図。The top view which shows the modification of the 3rd power terminal 316. 図１２のＸＩＩＩ－ＸＩＩＩ線における断面図。Sectional drawing in the line XIII-XIII of FIG. 第３電力端子３１６の一変形例を示す平面図。The top view which shows the modification of the 3rd power terminal 316. 図１４のＸＶ－ＸＶ線における断面図。Sectional drawing in the XV-XV line of FIG. 第３電力端子３１６の一変形例を示す平面図。The top view which shows the modification of the 3rd power terminal 316. 図１６のＸＶＩＩ－ＸＶＩＩ線における断面図。Sectional drawing in the XVII-XVII line of FIG. 実施例５の半導体装置４００の内部構造を示す平面図。FIG. 10 is a plan view showing the internal structure of a semiconductor device 400 of Example 5.
　本技術の一実施形態では、封止体の外部に位置する継手部材の一部は、第１半導体素子又は第２半導体素子を外部の回路へ電気的に接続するための電力端子として機能するように構成されていてもよい。このような構成によると、継手部材と電力端子とを単一の部材で構成することができ、部品点数の削減や半導体装置の小型化を図ることができる。 In an embodiment of the present technology, a part of the joint member located outside the sealing body functions as a power terminal for electrically connecting the first semiconductor element or the second semiconductor element to an external circuit. May be configured. With such a configuration, the joint member and the power terminal can be formed of a single member, and the number of parts can be reduced and the semiconductor device can be downsized.
　一例ではあるが、上記構成において、半導体装置は、封止体の内部で第１導体板に接続されているとともに、封止体から突出する第１電力端子と、封止体の内部で第４導体板に接続されているとともに、封止体から突出する第２電力端子と、封止体の内部で前記第２導体板及び前記第３導体板に接続された第３電力端子とを備えていてよい。この場合、継手部材は、第３電力端子の基端部に一体に形成されていてもよい。 As an example, in the above-described configuration, the semiconductor device is connected to the first conductor plate inside the sealing body, and has the first power terminal protruding from the sealing body and the fourth power terminal inside the sealing body. A second power terminal connected to the conductor plate and protruding from the sealing body, and a third power terminal connected to the second conductor plate and the third conductor plate inside the sealing body are provided. You can In this case, the joint member may be integrally formed with the base end portion of the third power terminal.
　本技術の一実施形態では、継手部材は、封止体の内部で第２導体板に接合された第１接合面と、封止体の内部で第３導体板に接合された第２接合面とを有していてもよい。この場合、第１接合面と第２接合面は、継手部材の同じ面に位置してもよいし、継手部材の異なる面に位置してもよい。 In one embodiment of the present technology, the joint member includes a first joint surface that is joined to the second conductor plate inside the sealing body and a second joint surface that is joined to the third conductor plate inside the sealing body. And may have. In this case, the first joint surface and the second joint surface may be located on the same surface of the joint member or may be located on different surfaces of the joint member.
　上記した実施形態において、継手部材は、第１接合面を有する第１板状部分と、第２接合面を有する第２板状部分と、第１板状部分と第２板状部分との間を延びる中間板状部分とを有していてもよい。このような構成によると、第２導体板と第３導体板との位置関係に応じて、中間板状部分を適宜設計することができる。 In the above-described embodiment, the joint member includes the first plate-shaped portion having the first joint surface, the second plate-shaped portion having the second joint surface, and the first plate-shaped portion and the second plate-shaped portion. May have an intermediate plate-shaped portion that extends. With such a configuration, the intermediate plate-shaped portion can be appropriately designed according to the positional relationship between the second conductor plate and the third conductor plate.
　上記した実施形態において、継手部材は、第１板状部分と中間板状部分との間の境界と、第２板状部分と中間板状部分との間の境界との少なくとも一方に、屈曲部を有していてもよい。継手部材に屈曲部を設けることで、継手部材の変形性能（外力に応じて変形する性質）を高めることができる。これにより、半導体装置の構成部品を組み合わせるときに、第２導体板と第３導体板との間の位置関係に応じて、継手部材は柔軟に変形することができる。継手部材が柔軟に変形することで、第２導体板及び第３導体板が、対向する第１導体板又は第４導体板に対して意図せず傾くことを避けることができる。また、半導体装置の使用時においても、半導体装置に生じる熱膨張に応じて、継手部材が柔軟に変形することにより、半導体装置の内部に生じる応力が緩和される。 In the above-described embodiment, the joint member has the bent portion at least at one of the boundary between the first plate-shaped portion and the intermediate plate-shaped portion and the boundary between the second plate-shaped portion and the intermediate plate-shaped portion. May have. By providing the joint member with the bent portion, the deformability (the property of being deformed according to an external force) of the joint member can be enhanced. Thus, when the components of the semiconductor device are combined, the joint member can be flexibly deformed according to the positional relationship between the second conductor plate and the third conductor plate. The flexible deformation of the joint member can prevent the second conductor plate and the third conductor plate from unintentionally tilting with respect to the opposing first conductor plate or fourth conductor plate. Further, even when the semiconductor device is used, the stress generated inside the semiconductor device is relaxed by the flexible deformation of the joint member according to the thermal expansion of the semiconductor device.
　上記した実施形態において、第１板状部分と第２板状部分は、中間板状部分に対して同じ方向に屈曲していてもよい。あるいは、第１板状部分と第２板状部分は、中間板状部分に対して互いに反対方向へ屈曲していてもよい。これらに加えて、継手部材は、中間板状部分に少なくとも一つの屈曲部をさらに有していてもよい。継手部材に複数の屈曲部を設けることによって、継手部材の変形性能を高めるとともに、継手部材に所望の形状を与えることができる。 In the above-described embodiment, the first plate-shaped portion and the second plate-shaped portion may be bent in the same direction with respect to the intermediate plate-shaped portion. Alternatively, the first plate-shaped portion and the second plate-shaped portion may be bent in mutually opposite directions with respect to the intermediate plate-shaped portion. In addition to these, the joint member may further include at least one bent portion in the intermediate plate-shaped portion. By providing the joint member with a plurality of bent portions, it is possible to enhance the deformability of the joint member and to give the joint member a desired shape.
　本技術の一実施形態では、継手部材は、第１接合面を一方側に有するとともに第２接合面を他方側に有する共通板状部分を有していてもよい。 In an embodiment of the present technology, the joint member may have a common plate-shaped portion having a first joint surface on one side and a second joint surface on the other side.
　第１半導体素子の厚み方向における平面視において、第１接合面と第２接合面とのそれぞれは、第１半導体素子及び第２半導体素子の各中心を通過する直線を跨いで広がっていてもよい。このような構成によると、継手部材から各半導体素子への距離を比較的に短くすることができ、電流経路におけるインダクタンスを低減することができる。 When seen in a plan view in the thickness direction of the first semiconductor element, each of the first bonding surface and the second bonding surface may extend across a straight line passing through each center of the first semiconductor element and the second semiconductor element. .. With such a configuration, the distance from the joint member to each semiconductor element can be made relatively short, and the inductance in the current path can be reduced.
　本技術の一実施形態では、第１導体板と第３導体板は、第１の平面に沿って配置され、第２導体板と第４導体板は、第１の平面に平行な第２の平面に沿って配置されていてもよい。即ち、第１導体板と第３導体板とが隣り合うように配置され、第２導体板と第４導体板とが隣り合うように配置されてもよい。 In one embodiment of the present technology, the first conductor plate and the third conductor plate are arranged along a first plane, and the second conductor plate and the fourth conductor plate are arranged in a second plane parallel to the first plane. It may be arranged along a plane. That is, the first conductor plate and the third conductor plate may be arranged adjacent to each other, and the second conductor plate and the fourth conductor plate may be arranged adjacent to each other.
　本技術の一実施形態では、継手構造は、第２導体板に設けられており、第２導体板から第４導体板に向かって延びる第１継手部と、第３導体板に設けられており、第３導体板から第１導体板に向かって延びる第２継手部とを含んでいてもよい。この場合、第１継手部は、第２継手部に少なくとも部分的に対向していてもよい。そして、第３電力端子の基端部は、第１継手部と第２継手部との間において、第１継手部と第２継手部とのそれぞれに接続されていてもよい。このような構成によると、継手構造を簡素に構成することができる。 In one embodiment of the present technology, the joint structure is provided on the second conductor plate, and is provided on the first joint portion extending from the second conductor plate toward the fourth conductor plate and the third conductor plate. , And a second joint portion extending from the third conductor plate toward the first conductor plate. In this case, the first joint portion may at least partially oppose the second joint portion. The base end portion of the third power terminal may be connected to each of the first joint portion and the second joint portion between the first joint portion and the second joint portion. With such a configuration, the joint structure can be simply configured.
　本技術の一実施形態では、第１継手部は、第２導体板の第４導体板と対向する一側面から延びており、第２継手部は、第３導体板の第１導体板と対向する一側面から延びていてもよい。このような構成によると、継手構造をより簡素に構成することができる。但し、他の実施形態として、第１継手部は、例えば第２導体板の第１導体板に対向する主表面に設けられてもよい。加えて、又は代えて、第２継手部は、第３導体板の第４導体板に対向する主表面に設けられてもよい。 In one embodiment of the present technology, the first joint portion extends from one side surface of the second conductor plate that faces the fourth conductor plate, and the second joint portion faces the first conductor plate of the third conductor plate. It may extend from one side surface. With such a configuration, the joint structure can be configured more simply. However, as another embodiment, the first joint portion may be provided, for example, on the main surface of the second conductor plate that faces the first conductor plate. Additionally or alternatively, the second joint portion may be provided on the main surface of the third conductor plate that faces the fourth conductor plate.
　上記構成に加えて、本技術の一実施形態では、第１継手部の厚みは、第２導体板の厚みより小さくてもよい。また、第２継手部の厚みは、第３導体板の厚みより小さくてもよい。第１継手部や第２継手部の厚みが小さいと、半導体装置が動作して発熱したときに、継手構造で生じる熱応力を小さくすることができる。なお、第１継手部及び第２継手部の具体的な厚みは、適宜設計することができる。 In addition to the above configuration, in one embodiment of the present technology, the thickness of the first joint portion may be smaller than the thickness of the second conductor plate. The thickness of the second joint portion may be smaller than the thickness of the third conductor plate. When the thickness of the first joint portion or the second joint portion is small, the thermal stress generated in the joint structure can be reduced when the semiconductor device operates and generates heat. The specific thicknesses of the first joint portion and the second joint portion can be appropriately designed.
　本技術の一実施形態では、第１継手部が、第３電力端子の基端部に、第１継手接合層を介して接合されていてもよい。この場合、第１継手接合層が第１継手部に接触する面積は、第１継手接合層が基端部に接触する面積よりも、大きくてもよい。このような構成によると、第１継手接合層が良好なフィレット形状を形成して、第１継手部と第３電力端子の基端部との間がしっかりと接合される。なお、特に限定されないが、第１継手接合層のフィレット角度は、鋭角（即ち、９０度未満）であるとよい。同様に、第２継手部は、第３電力端子の基端部に、第２継手接合層を介して接合されていてもよい。この場合、第２継手接合層が第２継手部に接触する面積は、第２継手接合層が基端部に接触する面積よりも、大きくてもよい。このような構成によると、第２継手接合層が良好なフィレット形状を形成して、第２継手部と第３電力端子の基端部との間がしっかりと接合される。第２継手接合層についても、特に限定されないが、そのフィレット角度が鋭角（即ち、９０度未満）であるとよい。 In an embodiment of the present technology, the first joint portion may be joined to the base end portion of the third power terminal via the first joint joining layer. In this case, the area where the first joint bonding layer contacts the first joint portion may be larger than the area where the first joint joint layer contacts the base end portion. With such a configuration, the first joint bonding layer forms a favorable fillet shape, and the first joint portion and the base end portion of the third power terminal are firmly joined. In addition, although not particularly limited, the fillet angle of the first joint bonding layer is preferably an acute angle (that is, less than 90 degrees). Similarly, the second joint portion may be joined to the base end portion of the third power terminal via the second joint joining layer. In this case, the area where the second joint bonding layer contacts the second joint portion may be larger than the area where the second joint joint layer contacts the base end portion. With such a configuration, the second joint bonding layer forms a favorable fillet shape, and the second joint portion and the base end portion of the third power terminal are firmly joined. The second joint bonding layer is also not particularly limited, but its fillet angle is preferably an acute angle (that is, less than 90 degrees).
　本技術の一実施形態では、第１電力端子及び第２電力端子は、封止体の第１主表面と第２主表面との間を延びる第１側面から、互いに平行に突出していてもよい。第１電力端子と第２電力端子との間では、互いに反対方向へ電流が流れる。このような二つの電力端子が隣接して配置されていると、各々の電力端子を流れる電流によって形成される磁界が互いに打ち消されるので、半導体装置のインダクタンスが低減される。 In one embodiment of the present technology, the first power terminal and the second power terminal may project in parallel to each other from a first side surface that extends between the first main surface and the second main surface of the sealing body. .. Currents flow in opposite directions between the first power terminal and the second power terminal. When such two power terminals are arranged adjacent to each other, the magnetic fields formed by the currents flowing through the respective power terminals cancel each other out, so that the inductance of the semiconductor device is reduced.
　上記した実施形態において、第３電力端子は、封止体の第１側面とは反対側に位置する第２側面から突出していてもよい。このような構成によると、三つの電力端子が同一の側面から突出している場合に比べて、半導体装置の小型化を実現しつつ、各々の電力端子のサイズを大きくすることができる。加えて、又は代えて、第１電力端子と第２電力端子との間の間隔を比較的自由に設計することができる。 In the above-described embodiment, the third power terminal may project from the second side surface located on the opposite side of the first side surface of the sealing body. With such a configuration, it is possible to reduce the size of the semiconductor device and increase the size of each power terminal, as compared with the case where the three power terminals project from the same side surface. Additionally or alternatively, the spacing between the first and second power terminals can be designed relatively freely.
　本技術の一実施形態では、封止体は、互いに反対側に位置するとともに第１端面と第２端面との間に延びている第１主表面及び第２主表面を有し、第１主表面は第１導体板及び第３導体板を露出し、第２主表面は第２導体板及び第４導体板を露出する、このような構成によると、半導体装置は、各導体板が封止体の両面において露出し、それらが放熱板として機能する両面冷却構造を有することができる。 In one embodiment of the present technology, the sealing body has a first main surface and a second main surface that are located on opposite sides and extend between the first end surface and the second end surface. The surface exposes the first conductor plate and the third conductor plate, and the second main surface exposes the second conductor plate and the fourth conductor plate. With such a configuration, in the semiconductor device, each conductor plate is sealed. It may have a double-sided cooling structure that is exposed on both sides of the body and they act as heat sinks.
　本技術の一実施形態では、半導体装置は、絶縁基板をさらに備えていてもよい。この場合、第１導体板、第２導体板、第３導体板及び第４導体板の少なくとも一つは、絶縁基板上に設けられていてもよい。絶縁基板は比較的剛性が高く、半導体装置に生じ得る熱変形を抑制する。これにより、半導体装置の内部（特に、半導体素子の周辺）に生じ得る応力が抑制される。一例ではあるが、第１導体板、第２導体板、第３導体板及び第４導体板が、それぞれ異なる絶縁基板上に設けられていてもよい。あるいは、第１導体板及び第３導体板が共通の絶縁基板上に設けられていてもよいし、代えて、又は加えて、第２導体板及び第４導体板が、共通の絶縁基板上に設けられていてもよい。 In one embodiment of the present technology, the semiconductor device may further include an insulating substrate. In this case, at least one of the first conductor plate, the second conductor plate, the third conductor plate, and the fourth conductor plate may be provided on the insulating substrate. The insulating substrate has relatively high rigidity and suppresses thermal deformation that may occur in the semiconductor device. This suppresses the stress that can occur inside the semiconductor device (particularly around the semiconductor element). As an example, the first conductor plate, the second conductor plate, the third conductor plate, and the fourth conductor plate may be provided on different insulating substrates. Alternatively, the first conductor plate and the third conductor plate may be provided on a common insulating substrate. Alternatively, or in addition, the second conductor plate and the fourth conductor plate may be provided on the common insulating substrate. It may be provided.
　本技術の一実施形態では、第１半導体素子と第２半導体素子とのそれぞれは、スイッチング素子であってよい。具体的には、第１半導体素子と第２半導体素子とのそれぞれは、ＩＧＢＴ構造を有し、第１半導体素子のＩＧＢＴ構造は、第１導体板に接続されたコレクタと、第２導体板に接続されたエミッタとを有し、第２半導体素子のＩＧＢＴ構造は、第３導体板に接続されたコレクタと、第４導体板に接続されたエミッタとを有していてもよい。あるいは、第１半導体素子と第２半導体素子とのそれぞれは、ＭＯＳＦＥＴ構造を有し、第１半導体素子のＭＯＳＦＥＴ構造は、第１導体板に接続されたドレインと、第２導体板に接続されたソースとを有し、第２半導体素子のＭＯＳＦＥＴ構造は、第３導体板に接続されたドレインと、第４導体板に接続されたソースとを有していてもよい。 In one embodiment of the present technology, each of the first semiconductor element and the second semiconductor element may be a switching element. Specifically, each of the first semiconductor element and the second semiconductor element has an IGBT structure, and the IGBT structure of the first semiconductor element has a collector connected to the first conductor plate and a second conductor plate. The IGBT structure of the second semiconductor element having a connected emitter may have a collector connected to the third conductor plate and an emitter connected to the fourth conductor plate. Alternatively, each of the first semiconductor element and the second semiconductor element has a MOSFET structure, and the MOSFET structure of the first semiconductor element is connected to the drain connected to the first conductor plate and the second conductor plate. The MOSFET structure of the second semiconductor element having a source may have a drain connected to the third conductor plate and a source connected to the fourth conductor plate.
（実施例１）図１－図４を参照して、半導体装置１０について説明する。半導体装置１０は、例えば電気自動車の電力制御装置に採用され、コンバータやインバータといった電力変換回路の少なくとも一部を構成することができる。ここでいう電気自動車は、車輪を駆動するモータを有する自動車を広く意味し、例えば、外部の電力によって充電される電気自動車、モータに加えてエンジンを有するハイブリッド車、及び燃料電池を電源とする燃料電池車等を含む。 (Embodiment 1) A semiconductor device 10 will be described with reference to FIGS. The semiconductor device 10 is used, for example, in a power control device for an electric vehicle and can form at least a part of a power conversion circuit such as a converter or an inverter. The electric vehicle as used herein broadly means a vehicle having a motor that drives wheels, for example, an electric vehicle that is charged by external electric power, a hybrid vehicle that has an engine in addition to a motor, and fuel that uses a fuel cell as a power source. Including battery cars.
　図１－図４に示すように、半導体装置１０は、第１半導体素子２０、第２半導体素子４０及び封止体１８を有する。封止体１８は、絶縁性の材料を用いて構成されている。一例ではあるが、封止体１８は、例えばエポキシ樹脂を用いて形成されることができる。封止体１８は、概して板形状を有しており、第１主表面１８ａと、第１主表面１８ａとは反対側に位置する第２主表面１８ｂとを有する。また、封止体１８は、第１主表面１８ａと第２主表面１８ｂとの間を延びる第１端面１８ｃと、第１端面１８ｃとは反対側に位置する第２端面１８ｄとを有している。 As shown in FIGS. 1 to 4, the semiconductor device 10 has a first semiconductor element 20, a second semiconductor element 40, and a sealing body 18. The sealing body 18 is made of an insulating material. As an example, the sealing body 18 can be formed using, for example, an epoxy resin. The sealing body 18 has a generally plate shape, and has a first main surface 18a and a second main surface 18b located on the side opposite to the first main surface 18a. Moreover, the sealing body 18 has a first end surface 18c extending between the first main surface 18a and the second main surface 18b, and a second end surface 18d located on the opposite side of the first end surface 18c. There is.
　第１半導体素子２０は、パワー半導体素子であって、半導体基板２０ａと、複数の電極２０ｂ、２０ｃ、２０ｄとを有する。複数の電極２０ｂ、２０ｃ、２０ｄには、電力回路に接続される第１主電極２０ｂ及び第２主電極２０ｃと、信号回路に接続される複数の信号電極２０ｄとが含まれる。特に限定されないが、第１半導体素子２０はスイッチング素子であり、第１主電極２０ｂと第２主電極２０ｃとの間を導通及び遮断することができる。第１主電極２０ｂ及び複数の信号電極２０ｄは、半導体基板２０ａの一方の表面に位置しており、第２主電極２０ｃは、半導体基板２０ａの他方の表面に位置している。 The first semiconductor element 20 is a power semiconductor element and has a semiconductor substrate 20a and a plurality of electrodes 20b, 20c, 20d. The plurality of electrodes 20b, 20c, 20d include a first main electrode 20b and a second main electrode 20c connected to the power circuit, and a plurality of signal electrodes 20d connected to the signal circuit. Although not particularly limited, the first semiconductor element 20 is a switching element and can electrically connect and disconnect between the first main electrode 20b and the second main electrode 20c. The first main electrode 20b and the plurality of signal electrodes 20d are located on one surface of the semiconductor substrate 20a, and the second main electrode 20c is located on the other surface of the semiconductor substrate 20a.
　特に限定されないが、本実施例における第１半導体素子２０は、スイッチング素子であって、ＩＧＢＴ構造２０ｅを有している。第１主電極２０ｂは、ＩＧＢＴ構造２０ｅのエミッタに接続されており、第２主電極２０ｃは、ＩＧＢＴ構造２０ｅのコレクタに接続されており、信号電極２０ｄは、ＩＧＢＴ構造２０ｅのゲートに接続されている。加えて、第１半導体素子２０は、ＩＧＢＴ構造２０ｅと並列に接続されたダイオード構造２０ｆを有している。第１主電極２０ｂは、ダイオード構造２０ｆのアノードに接続されており、第２主電極２０ｃは、ダイオード構造２０ｆのカソードに接続されている。なお、他の実施形態として、第１半導体素子２０は、ＭＯＳＦＥＴ構造を有してもよい。この場合、第１主電極２０ｂは、ＭＯＳＦＥＴ構造のソースに接続され、第２主電極２０ｃは、ＭＯＳＦＥＴ構造のドレインに接続され、信号電極２０ｄは、ＭＯＳＦＥＴ構造のゲートに接続されている。 Although not particularly limited, the first semiconductor element 20 in the present embodiment is a switching element and has an IGBT structure 20e. The first main electrode 20b is connected to the emitter of the IGBT structure 20e, the second main electrode 20c is connected to the collector of the IGBT structure 20e, and the signal electrode 20d is connected to the gate of the IGBT structure 20e. There is. In addition, the first semiconductor element 20 has a diode structure 20f connected in parallel with the IGBT structure 20e. The first main electrode 20b is connected to the anode of the diode structure 20f, and the second main electrode 20c is connected to the cathode of the diode structure 20f. In addition, as another embodiment, the first semiconductor element 20 may have a MOSFET structure. In this case, the first main electrode 20b is connected to the source of the MOSFET structure, the second main electrode 20c is connected to the drain of the MOSFET structure, and the signal electrode 20d is connected to the gate of the MOSFET structure.
　同様に、第２半導体素子４０は、パワー半導体素子であって、半導体基板４０ａと、複数の電極４０ｂ、４０ｃ、４０ｄとを有する。複数の電極４０ｂ、４０ｃ、４０ｄには、電力回路に接続される第１主電極４０ｂ及び第２主電極４０ｃと、信号回路に接続される複数の信号電極４０ｄとが含まれる。特に限定されないが、第２半導体素子４０はスイッチング素子であり、第１主電極４０ｂと第２主電極４０ｃとの間を導通及び遮断することができる。第１主電極４０ｂ及び複数の信号電極４０ｄは、半導体基板４０ａの一方の表面に位置しており、第２主電極４０ｃは、半導体基板４０ａの他方の表面に位置している。 Similarly, the second semiconductor element 40 is a power semiconductor element and has a semiconductor substrate 40a and a plurality of electrodes 40b, 40c, 40d. The plurality of electrodes 40b, 40c, 40d include a first main electrode 40b and a second main electrode 40c connected to the power circuit, and a plurality of signal electrodes 40d connected to the signal circuit. Although not particularly limited, the second semiconductor element 40 is a switching element and can electrically connect and disconnect between the first main electrode 40b and the second main electrode 40c. The first main electrode 40b and the plurality of signal electrodes 40d are located on one surface of the semiconductor substrate 40a, and the second main electrode 40c is located on the other surface of the semiconductor substrate 40a.
　特に限定されないが、本実施例における第２半導体素子４０は、スイッチング素子であって、ＩＧＢＴ構造４０ｅを有している。第１主電極４０ｂは、ＩＧＢＴ構造４０ｅのエミッタに接続されており、第２主電極４０ｃは、ＩＧＢＴ構造４０ｅのコレクタに接続されており、信号電極４０ｄは、ＩＧＢＴ構造４０ｅのゲートに接続されている。加えて、第２半導体素子４０は、ＩＧＢＴ構造４０ｅと並列に接続されたダイオード構造４０ｆを有している。第１主電極４０ｂは、ダイオード構造４０ｆのアノードに接続されており、第２主電極４０ｃは、ダイオード構造４０ｆのカソードに接続されている。なお、他の実施形態として、第２半導体素子４０は、ＭＯＳＦＥＴ構造を有してもよい。この場合、第１主電極４０ｂは、ＭＯＳＦＥＴ構造のソースに接続され、第２主電極４０ｃは、ＭＯＳＦＥＴ構造のドレインに接続され、信号電極４０ｄは、ＭＯＳＦＥＴ構造のゲートに接続されている。 Although not particularly limited, the second semiconductor element 40 in the present embodiment is a switching element and has an IGBT structure 40e. The first main electrode 40b is connected to the emitter of the IGBT structure 40e, the second main electrode 40c is connected to the collector of the IGBT structure 40e, and the signal electrode 40d is connected to the gate of the IGBT structure 40e. There is. In addition, the second semiconductor element 40 has a diode structure 40f connected in parallel with the IGBT structure 40e. The first main electrode 40b is connected to the anode of the diode structure 40f, and the second main electrode 40c is connected to the cathode of the diode structure 40f. In addition, as another embodiment, the second semiconductor element 40 may have a MOSFET structure. In this case, the first main electrode 40b is connected to the source of the MOSFET structure, the second main electrode 40c is connected to the drain of the MOSFET structure, and the signal electrode 40d is connected to the gate of the MOSFET structure.
　本実施例では、第１半導体素子２０及び第２半導体素子４０は、互いに同種の半導体素子である。但し、同種に限定されず、第１半導体素子２０及び第２半導体素子４０は、互いに異種の半導体素子であってもよい。第１半導体素子２０及び第２半導体素子４０の具体的な構成は、特に限定されず、第１半導体素子２０及び第２半導体素子４０には、各種の半導体素子を採用することができる。第１半導体素子２０及び第２半導体素子４０の半導体基板２０ａ、４０ａを構成する材料についても特に限定されず、例えばシリコン（Ｓｉ）、炭化シリコン（ＳｉＣ）、又は窒化ガリウム（ＧａＮ）といった各種の半導体材料を採用することができる。 In this embodiment, the first semiconductor element 20 and the second semiconductor element 40 are semiconductor elements of the same kind. However, the first semiconductor element 20 and the second semiconductor element 40 are not limited to the same kind, and may be different kinds of semiconductor elements. The specific configurations of the first semiconductor element 20 and the second semiconductor element 40 are not particularly limited, and various semiconductor elements can be adopted as the first semiconductor element 20 and the second semiconductor element 40. The material forming the semiconductor substrates 20a, 40a of the first semiconductor element 20 and the second semiconductor element 40 is not particularly limited, and various semiconductors such as silicon (Si), silicon carbide (SiC), or gallium nitride (GaN) are included. Materials can be adopted.
　半導体装置１０は、複数の導体板２２、２６、４２、４６と、第１導体スペーサ２４及び第２導体スペーサ４４とを備える。第１導体スペーサ２４及び第２導体スペーサ４４は、概してブロック形状を有し、銅又は他の金属といった導体材料を用いて形成される。第１導体スペーサ２４は、上面２４ａと、その上面２４ａとは反対側に位置する下面２４ｂとを有する。導体スペーサ２４、４４は、必ずしも必要とされないが、後述する第１信号端子１２及び第２信号端子１３を信号電極２０ｄ、４０ｄに接続するためのスペースを確保している。 The semiconductor device 10 includes a plurality of conductor plates 22, 26, 42, 46, a first conductor spacer 24, and a second conductor spacer 44. The first conductor spacer 24 and the second conductor spacer 44 have a generally block shape, and are formed using a conductor material such as copper or another metal. The first conductor spacer 24 has an upper surface 24a and a lower surface 24b located on the opposite side of the upper surface 24a. The conductor spacers 24 and 44 are not necessarily required, but secure a space for connecting the first signal terminal 12 and the second signal terminal 13 described later to the signal electrodes 20d and 40d.
　複数の導体板２２、２６、４２、４６は、概して板形状を有する。複数の導体板２２、２６、４２、４６は、銅又は他の金属といった導体材料を用いて形成される。複数の導体板２２、２６、４２、４６には、第１下側導体板２２、第１上側導体板２６、第２下側導体板４２及び第２上側導体板４６が含まれる。第１下側導体板２２は、上面２２ａと、その上面２２ａとは反対側に位置する下面２２ｂと、その上面２２ａと下面２２ｂとの間に延びる側面とを有する。同様に、第１上側導体板２６は、上面２６ａと、その上面２６ａとは反対側に位置する下面２６ｂと、その上面２６ａと下面２６ｂとの間に延びる側面とを有する。第１下側導体板２２と第１上側導体板２６は、第１半導体素子２０を挟んで対向しており、第１導体スペーサ２４は、第１半導体素子２０と第１上側導体板２６との間に介挿されている。 The plurality of conductor plates 22, 26, 42, 46 generally have a plate shape. The plurality of conductor plates 22, 26, 42, 46 are formed using a conductor material such as copper or other metal. The plurality of conductor plates 22, 26, 42, 46 include a first lower conductor plate 22, a first upper conductor plate 26, a second lower conductor plate 42, and a second upper conductor plate 46. The first lower conductor plate 22 has an upper surface 22a, a lower surface 22b located on the opposite side of the upper surface 22a, and side surfaces extending between the upper surface 22a and the lower surface 22b. Similarly, the first upper conductor plate 26 has an upper surface 26a, a lower surface 26b located on the opposite side of the upper surface 26a, and side surfaces extending between the upper surface 26a and the lower surface 26b. The first lower conductor plate 22 and the first upper conductor plate 26 are opposed to each other with the first semiconductor element 20 interposed therebetween, and the first conductor spacer 24 includes the first semiconductor element 20 and the first upper conductor plate 26. It is inserted in between.
　一例ではあるが、第１下側導体板２２の上面２２ａと、第１半導体素子２０の第２主電極２０ｃとの間は、はんだ層２１を介して互いに接合されている。これにより、第１下側導体板２２は、第１半導体素子２０と電気的及び熱的に接続されている。同様に、第１半導体素子２０の第１主電極２０ｂと、第１導体スペーサ２４の下面２４ｂとの間は、はんだ層２３を介して互いに接合されており、第１導体スペーサ２４の上面２４ａと、第１上側導体板２６の下面２６ｂとの間は、はんだ層２５を介して互いに接合されている。これにより、第１上側導体板２６は、第１導体スペーサ２４を介して、第１半導体素子２０と電気的及び熱的に接続されている。但し、これらの構成部材の間の接合は、はんだ層に限定されず、導電性を有する他の種類の接合層を介して接合されてもよい。ここで、第１下側導体板２２は、本明細書が開示する技術における第１導体板の一例であり、第１上側導体板２６は、本明細書が開示する技術における第２導体板の一例である。 As an example, the upper surface 22a of the first lower conductor plate 22 and the second main electrode 20c of the first semiconductor element 20 are bonded to each other via the solder layer 21. As a result, the first lower conductor plate 22 is electrically and thermally connected to the first semiconductor element 20. Similarly, the first main electrode 20b of the first semiconductor element 20 and the lower surface 24b of the first conductor spacer 24 are joined to each other via the solder layer 23, and are connected to the upper surface 24a of the first conductor spacer 24. The lower surface 26b of the first upper conductor plate 26 is joined to each other via the solder layer 25. As a result, the first upper conductor plate 26 is electrically and thermally connected to the first semiconductor element 20 via the first conductor spacer 24. However, the joining between these constituent members is not limited to the solder layer, and the joining may be performed through another type of joining layer having conductivity. Here, the first lower conductor plate 22 is an example of the first conductor plate in the technique disclosed in the present specification, and the first upper conductor plate 26 is the second conductor plate in the technique disclosed in the present specification. This is an example.
　第２下側導体板４２は、上面４２ａと、その上面４２ａとは反対側に位置する下面４２ｂと、その上面４２ａと下面４２ｂとの間に延びる側面とを有する。同様に、第２上側導体板４６は、上面４６ａと、その上面４６ａとは反対側に位置する下面４６ｂと、その上面４６ａと下面４６ｂとの間に延びる側面とを有する。第２下側導体板４２と第２上側導体板４６は、第２半導体素子４０を挟んで対向しており、第２導体スペーサ４４は、第２半導体素子４０と第２上側導体板４６との間に介挿されている。 The second lower conductor plate 42 has an upper surface 42a, a lower surface 42b located on the side opposite to the upper surface 42a, and a side surface extending between the upper surface 42a and the lower surface 42b. Similarly, the second upper conductor plate 46 has an upper surface 46a, a lower surface 46b located on the opposite side of the upper surface 46a, and a side surface extending between the upper surface 46a and the lower surface 46b. The second lower conductor plate 42 and the second upper conductor plate 46 face each other with the second semiconductor element 40 interposed therebetween, and the second conductor spacer 44 separates the second semiconductor element 40 and the second upper conductor plate 46. It is inserted in between.
　一例ではあるが、第２下側導体板４２の上面４２ａと、第２半導体素子４０の第２主電極４０ｃとの間は、はんだ層４１を介して互いに接合されている。これにより、第２下側導体板４２は、第２半導体素子４０と電気的及び熱的に接続されている。同様に、第２半導体素子４０の第１主電極４０ｂと、第２導体スペーサ４４の下面４４ｂとの間は、はんだ層４３を介して互いに接合されており、第２導体スペーサ４４の上面４４ａと、第２上側導体板４６の下面４６ｂとの間は、はんだ層４５を介して互いに接合されている。これにより、第２上側導体板４６は、第２導体スペーサ４４を介して、第２半導体素子４０と電気的及び熱的に接続されている。但し、これらの構成部材の間の接合は、はんだ層に限定されず、導電性を有する他の種類の接合層を介して接合されていてもよい。ここで、第２下側導体板４２は、本明細書が開示する技術における第３導体板の一例であり、第２上側導体板４６は、本明細書が開示する技術における第４導体板の一例である。 As an example, the upper surface 42a of the second lower conductor plate 42 and the second main electrode 40c of the second semiconductor element 40 are bonded to each other via the solder layer 41. As a result, the second lower conductor plate 42 is electrically and thermally connected to the second semiconductor element 40. Similarly, the first main electrode 40b of the second semiconductor element 40 and the lower surface 44b of the second conductor spacer 44 are joined to each other through the solder layer 43, and the upper surface 44a of the second conductor spacer 44 is connected to the upper surface 44a. The lower surface 46b of the second upper conductor plate 46 is joined to each other via the solder layer 45. As a result, the second upper conductor plate 46 is electrically and thermally connected to the second semiconductor element 40 via the second conductor spacer 44. However, the joining between these constituent members is not limited to the solder layer, and the joining may be performed via another type of joining layer having conductivity. Here, the second lower conductor plate 42 is an example of the third conductor plate in the technique disclosed in the present specification, and the second upper conductor plate 46 is the fourth conductor plate in the technique disclosed in the present specification. This is an example.
　第１下側導体板２２と第２下側導体板４２は、封止体１８の第１主表面１８ａに沿って配置されており、それらの下面２２ｂ、４２ｂは、封止体１８の第１主表面１８ａにおいて露出されている。また、第２下側導体板４２の一側面４２ｃは、封止体１８の内部において、第１下側導体板２２に対向している。同様に、第１上側導体板２６と第２上側導体板４６は、封止体１８の第２主表面１８ｂに沿って配置されており、それらの上面２６ａ、４６ａは、封止体１８の第２主表面１８ｂにおいて露出されている。また、第１上側導体板２６の一側面２６ｃは、封止体１８の内部において、第２上側導体板４６に対向している。本実施例の半導体装置１０は、各導体板２２、２６、４２、４６が封止体１８の両主表面１８ａ、１８ｂにおいて露出し、それらが放熱板として機能する両面冷却構造を有する。ここで、特に限定されないが、封止体１８の第１主表面１８ａと第２主表面１８ｂは、互いに平行な平面である。 The first lower conductor plate 22 and the second lower conductor plate 42 are arranged along the first main surface 18a of the sealing body 18, and their lower surfaces 22b and 42b are the first lower surface of the sealing body 18. It is exposed on the main surface 18a. Further, the one side surface 42c of the second lower conductor plate 42 faces the first lower conductor plate 22 inside the sealing body 18. Similarly, the first upper conductor plate 26 and the second upper conductor plate 46 are arranged along the second main surface 18b of the sealing body 18, and the upper surfaces 26a and 46a thereof are the same as those of the sealing body 18. 2 Exposed on the main surface 18b. Further, the one side surface 26 c of the first upper conductor plate 26 faces the second upper conductor plate 46 inside the sealing body 18. The semiconductor device 10 of the present embodiment has a double-sided cooling structure in which the conductor plates 22, 26, 42, 46 are exposed on both main surfaces 18a, 18b of the sealing body 18, and they function as heat sinks. Here, although not particularly limited, the first main surface 18a and the second main surface 18b of the sealing body 18 are planes parallel to each other.
　半導体装置１０は、継手構造３０をさらに備える。継手構造３０は、第１上側導体板２６と第２下側導体板４２とを互いに接続する。一例ではあるが、継手構造３０は、第１継手部２８と第２継手部４８とを含む。第１継手部２８は、第１上側導体板２６の一側面２６ｃから、第２上側導体板４６に向かって延びている。本実施例の第１継手部２８は、第１上側導体板２６に一体に設けられているが、これに限定されない。第１継手部２８は、第１上側導体板２６とは別の部材で用意され、第１上側導体板２６に接合されていてもよい。第２継手部４８は、第２下側導体板４２の一側面４２ｃから、第１下側導体板２２に向かって延びている。本実施例の第２継手部４８は、第２下側導体板４２に一体に設けられているが、これに限定されない。第２継手部４８は、第２下側導体板４２とは別の部材で用意され、第２下側導体板４２に接合されていてもよい。第１継手部２８は、第２継手部４８に対向している。但し、第１継手部２８が第２継手部４８に対向する範囲は、特に限定されず、第２継手部４８に少なくとも部分的に対向していてもよい。 The semiconductor device 10 further includes a joint structure 30. The joint structure 30 connects the first upper conductor plate 26 and the second lower conductor plate 42 to each other. As an example, the joint structure 30 includes a first joint portion 28 and a second joint portion 48. The first joint portion 28 extends from one side surface 26c of the first upper conductor plate 26 toward the second upper conductor plate 46. The first joint portion 28 of the present embodiment is provided integrally with the first upper conductor plate 26, but is not limited to this. The first joint portion 28 may be prepared as a member different from the first upper conductor plate 26 and may be joined to the first upper conductor plate 26. The second joint portion 48 extends from the one side surface 42c of the second lower conductor plate 42 toward the first lower conductor plate 22. The second joint portion 48 of the present embodiment is provided integrally with the second lower conductor plate 42, but is not limited to this. The second joint portion 48 may be prepared as a member different from the second lower conductor plate 42, and may be joined to the second lower conductor plate 42. The first joint portion 28 faces the second joint portion 48. However, the range in which the first joint portion 28 faces the second joint portion 48 is not particularly limited, and may be at least partially opposed to the second joint portion 48.
　半導体装置１０は、複数の外部接続端子１２、１３、１４、１５、１６を備える。各々の外部接続端子１２、１３、１４、１５、１６は、例えば銅又は他の金属といった導電体で構成されており、封止体１８の内外に亘って延びている。複数の外部接続端子１２、１３、１４、１５、１６には、複数の第１信号端子１２と、複数の第２信号端子１３と、第１電力端子１４、第２電力端子１５及び第３電力端子１６とが含まれる。一例ではあるが、第１電力端子１４及び第２電力端子１５は、封止体１８の第１端面１８ｃから突出しており、第３電力端子１６及び複数の信号端子１２、１３は、封止体１８の第２端面１８ｄから突出している。 The semiconductor device 10 includes a plurality of external connection terminals 12, 13, 14, 15, 16. Each of the external connection terminals 12, 13, 14, 15, 16 is made of a conductor such as copper or another metal and extends inside and outside the sealing body 18. The plurality of external connection terminals 12, 13, 14, 15, 16 include a plurality of first signal terminals 12, a plurality of second signal terminals 13, a first power terminal 14, a second power terminal 15, and a third power. And a terminal 16. As an example, the first power terminal 14 and the second power terminal 15 are projected from the first end surface 18c of the sealing body 18, and the third power terminal 16 and the plurality of signal terminals 12 and 13 are the sealing bodies. It projects from the second end face 18 d of 18.
　第１信号端子１２は、第１半導体素子２０の信号電極２０ｄに、はんだ層（図示省略）を介して接合されている。即ち、第１信号端子１２は、第１半導体素子２０の信号電極２０ｄと電気的に接続されている。第２信号端子１３は、第２半導体素子４０の信号電極４０ｄに、はんだ層（図示省略）を介して接合されている。即ち、第２信号端子１３は、第２半導体素子４０の信号電極４０ｄと電気的に接続されている。なお、第１信号端子１２と信号電極２０ｄとの間、及び、第２信号端子１３と信号電極４０ｄとの間の接合は、はんだ層に限られず、導電性を有する他の種類の接合層を介して接合されてもよい。 The first signal terminal 12 is joined to the signal electrode 20d of the first semiconductor element 20 via a solder layer (not shown). That is, the first signal terminal 12 is electrically connected to the signal electrode 20d of the first semiconductor element 20. The second signal terminal 13 is joined to the signal electrode 40d of the second semiconductor element 40 via a solder layer (not shown). That is, the second signal terminal 13 is electrically connected to the signal electrode 40d of the second semiconductor element 40. Note that the bonding between the first signal terminal 12 and the signal electrode 20d and between the second signal terminal 13 and the signal electrode 40d is not limited to the solder layer, and another type of conductive bonding layer may be used. It may be joined via.
　第１電力端子１４及び第２電力端子１５は、概して幅広の板形状を有する。第１電力端子１４は、第１下側導体板２２に接続されている。第２電力端子１５は、第２上側導体板４６に接続されている。第３電力端子１６は、概して板形状を有し、幅広の先端部１６ａと先端部１６ａから細長く延びる基端部１６ｂとを有する。第３電力端子１６は、その基端部１６ｂにおいて第１上側導体板２６と第２下側導体板４２とに接続されている。従って、第１電力端子１４、第２電力端子１５及び第３電力端子１６は、第１半導体素子２０及び第２半導体素子４０に電気的に接続されている。第１電力端子１４及び第２電力端子１５は外部の直流電源（図示省略）の高電位側と低電位側へそれぞれ接続されており、第３電力端子１６の先端部１６ａは負荷（例えば、モータ）へ接続される。これにより、半導体装置１０は、例えば、インバータ回路の一部を構成することができる。ここで、第３電力端子１６は、継手構造３０の一部を構成しており、本明細書が開示する技術における継手部材の一例である。以降、第３電力端子１６は、継手部材１６とも称する。 The first power terminal 14 and the second power terminal 15 each have a generally wide plate shape. The first power terminal 14 is connected to the first lower conductor plate 22. The second power terminal 15 is connected to the second upper conductor plate 46. The third power terminal 16 has a generally plate shape, and has a wide front end portion 16a and a base end portion 16b elongated from the front end portion 16a. The third power terminal 16 is connected to the first upper conductor plate 26 and the second lower conductor plate 42 at the base end portion 16b thereof. Therefore, the first power terminal 14, the second power terminal 15, and the third power terminal 16 are electrically connected to the first semiconductor element 20 and the second semiconductor element 40. The first power terminal 14 and the second power terminal 15 are respectively connected to the high potential side and the low potential side of an external DC power source (not shown), and the tip portion 16a of the third power terminal 16 is connected to a load (for example, a motor). ) Is connected to. As a result, the semiconductor device 10 can form, for example, a part of the inverter circuit. Here, the 3rd electric power terminal 16 constitutes a part of joint structure 30, and is an example of a joint member in the art indicated by this specification. Hereinafter, the third power terminal 16 is also referred to as the joint member 16.
　実施例１において、半導体装置１０は継手構造３０を備えている。半導体装置１０の内部に継手構造３０が存在すると、その分だけ、半導体装置１０のサイズも大きくなりやすい。この点に関して、本実施例の半導体装置１０では、第３電力端子１６の基端部１６ｂが、第１継手部２８と第２継手部４８との間に位置しており、第１継手部２８と第２継手部４８とのそれぞれに、第１継手はんだ層２７又は第２継手はんだ層４７を介して接合されている。即ち、第１継手部２８と第２継手部４８との間が、第３電力端子１６の基端部１６ｂを介して互いに接続されている。このような構成によると、継手構造３０において、継手部材１６と第３電力端子１６とが単一の部材で構成されることができ、部品点数の削減や半導体装置１０の小型化を図ることができる。なお、第３電力端子１６の基端部１６ｂは、本技術における継手部材１６の共通板状部分の一例である。また、第３電力端子１６の基端部１６ｂと第１継手部２８との間、及び、第３電力端子１６の基端部１６ｂと第２継手部４８との間の接合は、継手はんだ層２７、４７に限られず、導電性を有する他の種類の接合層を介して接合されてもよい。 In the first embodiment, the semiconductor device 10 includes the joint structure 30. If the joint structure 30 exists inside the semiconductor device 10, the size of the semiconductor device 10 is likely to increase accordingly. In this regard, in the semiconductor device 10 of the present embodiment, the base end portion 16b of the third power terminal 16 is located between the first joint portion 28 and the second joint portion 48, and the first joint portion 28 And the second joint portion 48 are joined to each other via the first joint solder layer 27 or the second joint solder layer 47. That is, the first joint portion 28 and the second joint portion 48 are connected to each other via the base end portion 16b of the third power terminal 16. With such a configuration, in the joint structure 30, the joint member 16 and the third power terminal 16 can be formed of a single member, and the number of parts can be reduced and the semiconductor device 10 can be downsized. it can. The base end portion 16b of the third power terminal 16 is an example of a common plate-shaped portion of the joint member 16 in the present technology. The joint between the base end portion 16b of the third power terminal 16 and the first joint portion 28 and the joint between the base end portion 16b of the third power terminal 16 and the second joint portion 48 are joint solder layers. The bonding layer is not limited to 27 and 47, and may be bonded via another type of bonding layer having conductivity.
　継手部材１６は、上記のように第３電力端子１６の基端部１６ｂに一体に形成されていてもよいし、第３電力端子１６に限定されず、他の電力端子（例えば電力端子１４、１５）と一体に形成されていてもよい。継手部材１６は、第１半導体素子２０又は第２半導体素子４０を外部の回路へ電気的に接続するための電力端子として機能するように構成されていればよい。 The joint member 16 may be integrally formed with the base end portion 16b of the third power terminal 16 as described above, and is not limited to the third power terminal 16 and other power terminals (for example, the power terminal 14, It may be formed integrally with 15). The joint member 16 may be configured to function as a power terminal for electrically connecting the first semiconductor element 20 or the second semiconductor element 40 to an external circuit.
　本実施例の半導体装置１０では、第１上側導体板２６と第２上側導体板４６が、封止体１８の第２主表面１８ｂに沿って配置されており、第１下側導体板２２と第２下側導体板４２は、封止体１８の第１主表面１８ａに沿って配置されている。そして、第１継手部２８は、第１上側導体板２６の側面のうち、第２上側導体板４６と対向する一側面２６ｃから、第２上側導体板４６に向けて延びている。同様に、第２継手部４８は、第２下側導体板４２の側面のうち、第１下側導体板２２と対向する一側面４２ｃから、第１下側導体板２２に向けて延びている。そして、第３電力端子１６の基端部１６ｂが、第１継手部２８と第２継手部４８との間に位置しており、それらの継手部２８、４８が第３電力端子１６の基端部１６ｂを介して互いに接続されている。このような構成によると、継手構造３０を簡素に構成することができる。例えば、第１継手部２８と第２継手部４８とのそれぞれを、平坦な板状で形成することもできる。それぞれの継手部２８、４８に複雑な形状が必要とされないことから、継手構造３０を小型に構成することができ、もって半導体装置１０の小型化を図ることができる。 In the semiconductor device 10 of the present embodiment, the first upper conductor plate 26 and the second upper conductor plate 46 are arranged along the second main surface 18b of the sealing body 18, and the first lower conductor plate 22 and The second lower conductor plate 42 is arranged along the first main surface 18 a of the sealing body 18. Then, the first joint portion 28 extends toward the second upper conductor plate 46 from one side surface 26c of the side surface of the first upper conductor plate 26 that faces the second upper conductor plate 46. Similarly, the second joint portion 48 extends toward the first lower conductor plate 22 from one side face 42c of the second lower conductor plate 42 that faces the first lower conductor plate 22 among the side faces of the second lower conductor plate 42. .. And the base end part 16b of the 3rd power terminal 16 is located between the 1st joint part 28 and the 2nd joint part 48, and those joint parts 28 and 48 are the base ends of the 3rd power terminal 16. They are connected to each other via the portion 16b. With such a configuration, the joint structure 30 can be simply configured. For example, each of the first joint portion 28 and the second joint portion 48 can be formed in a flat plate shape. Since the joint portions 28 and 48 do not need to have a complicated shape, the joint structure 30 can be configured in a small size, and thus the semiconductor device 10 can be downsized.
　本実施例の半導体装置１０では、第１継手部２８の厚みが、第１上側導体板２６の厚みより小さい。同様に、第２継手部４８の厚みは、第２下側導体板４２の厚みより小さい。第１継手部２８や第２継手部４８の厚みが小さいと、半導体装置１０が動作して発熱したときに、継手構造３０で生じる熱応力を小さくすることができる。なお、第１継手部２８及び第２継手部４８の具体的な厚みは、適宜設計することができる。 In the semiconductor device 10 of this embodiment, the thickness of the first joint portion 28 is smaller than the thickness of the first upper conductor plate 26. Similarly, the thickness of the second joint portion 48 is smaller than the thickness of the second lower conductor plate 42. When the thickness of the first joint portion 28 and the second joint portion 48 is small, it is possible to reduce the thermal stress generated in the joint structure 30 when the semiconductor device 10 operates and generates heat. The specific thickness of the first joint portion 28 and the second joint portion 48 can be appropriately designed.
　本実施例の半導体装置１０では、第１電力端子１４及び第２電力端子１５が、封止体１８の第１端面１８ｃから、互いに平行に突出している。第１電力端子１４と第２電力端子１５との間では、互いに反対方向へ電流が流れる。このような二つの端子１４、１５が隣接して配置されていると、各々の端子１４、１５を流れる電流によって形成される磁界が互いに打ち消される。これにより、半導体装置１０のインダクタンスが低減される。 In the semiconductor device 10 of the present embodiment, the first power terminal 14 and the second power terminal 15 project in parallel with each other from the first end surface 18c of the sealing body 18. Between the first power terminal 14 and the second power terminal 15, currents flow in opposite directions. When such two terminals 14 and 15 are arranged adjacent to each other, the magnetic fields formed by the currents flowing through the terminals 14 and 15 cancel each other out. As a result, the inductance of the semiconductor device 10 is reduced.
　本実施例の半導体装置１０では、第３電力端子１６が、封止体１８の第１端面１８ｃとは反対側に位置する第２端面１８ｄから突出している。このような構成によると、三つの端子１４、１５、１６が封止体１８の同一の側面（例えば、第１端面１８ｃ）から突出している場合に比べて、半導体装置１０の小型化を実現しつつ、各々の端子１４、１５、１６のサイズを大きくすることができる。加えて、又は代えて、第１電力端子１４と第２電力端子１５との間の間隔を比較的自由に設計することができる。 In the semiconductor device 10 of the present embodiment, the third power terminal 16 projects from the second end surface 18d of the encapsulation body 18 located on the opposite side of the first end surface 18c. With such a configuration, the semiconductor device 10 can be made smaller than in the case where the three terminals 14, 15, 16 project from the same side surface (for example, the first end surface 18c) of the sealing body 18. At the same time, the size of each terminal 14, 15, 16 can be increased. Additionally or alternatively, the spacing between the first power terminal 14 and the second power terminal 15 can be designed relatively freely.
　本実施例の半導体装置１０では、第１下側導体板２２及び第１上側導体板２６の間に第１半導体素子２０が実装されている。但し、これに限定されず、第１下側導体板２２及び第１上側導体板２６の間に二以上の半導体素子が実装されていてもよい。同様に、第２下側導体板４２及び第２上側導体板４６の間に第２半導体素子４０が実装されている。但し、これに限定されず、第２下側導体板４２及び第２上側導体板４６の間に二以上の半導体素子が実装されていてもよい。 In the semiconductor device 10 of this embodiment, the first semiconductor element 20 is mounted between the first lower conductor plate 22 and the first upper conductor plate 26. However, the present invention is not limited to this, and two or more semiconductor elements may be mounted between the first lower conductor plate 22 and the first upper conductor plate 26. Similarly, the second semiconductor element 40 is mounted between the second lower conductor plate 42 and the second upper conductor plate 46. However, the present invention is not limited to this, and two or more semiconductor elements may be mounted between the second lower conductor plate 42 and the second upper conductor plate 46.
　ここで、図５を参照して、半導体装置１０の一使用例について説明する。図５に示すように、第３電力端子１６と第１信号端子１２と第２信号端子１３とは、Ｚ方向に曲げて外部装置に接続されてもよい。ここでいう外部装置は、例えば、半導体装置１０を制御する制御基板等のことを示す。このとき、第３電力端子１６と、第１信号端子１２及び第２信号端子１３とを曲げる位置は互いに離れているとよい。この場合において、第３電力端子１６と第１信号端子１２及び第２信号端子１３との間に空間距離が形成され、互いの絶縁性を確保することができる。 Here, an example of use of the semiconductor device 10 will be described with reference to FIG. As shown in FIG. 5, the third power terminal 16, the first signal terminal 12, and the second signal terminal 13 may be bent in the Z direction and connected to an external device. The external device mentioned here indicates, for example, a control board or the like for controlling the semiconductor device 10. At this time, the bending positions of the third power terminal 16 and the first signal terminal 12 and the second signal terminal 13 are preferably separated from each other. In this case, a spatial distance is formed between the third power terminal 16 and the first signal terminal 12 and the second signal terminal 13, so that mutual insulation can be ensured.
　継手構造３０及び第３電力端子１６の構成は、上述した実施形態に限られず、様々な実施形態によって構成することができる。他の実施形態について、以下の実施例で説明する。 The configurations of the joint structure 30 and the third power terminal 16 are not limited to the above-described embodiments, but can be configured according to various embodiments. Other embodiments will be described in the following examples.
（実施例２）図６を参照して、実施例２の半導体装置１００について説明する。図６に示すように、実施例２の半導体装置１００は、実施例１の半導体装置１０と比較して、第１上側導体板１２６、第２下側導体板１４２及び継手構造１３０の構造が変更されている。第２下側導体板１４２及び継手構造１３０以外の他の構成については、実施例１と同様に構成することができるため、ここでは重複する説明は省略する。 (Second Embodiment) A semiconductor device 100 of a second embodiment will be described with reference to FIG. As shown in FIG. 6, the semiconductor device 100 of the second embodiment is different from the semiconductor device 10 of the first embodiment in the structure of the first upper conductor plate 126, the second lower conductor plate 142, and the joint structure 130. Has been done. Since the configuration other than the second lower conductor plate 142 and the joint structure 130 can be configured in the same manner as in the first embodiment, redundant description will be omitted here.
　実施例２の半導体装置１００では、第１上側導体板１２６と第２下側導体板１４２との一方又は両方が拡大されており、第１上側導体板１２６の一部は、第２下側導体板１４２の一部と対向している。そして、継手構造１３０は、第１上側導体板１２６と第２下側導体板１４２の互いに対向する部分の間に位置している。継手構造１３０では、第３電力端子１６の基端部１６ｂが、第１継手はんだ層１２７を介して第１上側導体板１２６に接合されている。また、第３電力端子１６の基端部１６ｂは、第２継手はんだ層１４７を介して第２下側導体板１４２に接合されている。即ち、本実施例における継手構造１３０は、実施例１で説明したような第１継手部２８や第２継手部４８を有していない。 In the semiconductor device 100 of the second embodiment, one or both of the first upper conductor plate 126 and the second lower conductor plate 142 are enlarged, and a part of the first upper conductor plate 126 is the second lower conductor. It faces a part of the plate 142. The joint structure 130 is located between the portions of the first upper conductor plate 126 and the second lower conductor plate 142 that face each other. In the joint structure 130, the base end portion 16b of the third power terminal 16 is joined to the first upper conductor plate 126 via the first joint solder layer 127. The base end portion 16b of the third power terminal 16 is joined to the second lower conductor plate 142 via the second joint solder layer 147. That is, the joint structure 130 in the present embodiment does not have the first joint portion 28 and the second joint portion 48 as described in the first embodiment.
　従って、実施例２の半導体装置１００では、実施例１の半導体装置１０と同様に、継手構造１３０において、継手部材１６と第３電力端子１６とが単一の部材で構成されることができる。これにより、部品点数の削減や半導体装置１００の小型化を図ることができる。なお、第３電力端子１６の基端部１６ｂと第１上側導体板１２６との間、及び、第３電力端子１６の基端部１６ｂと第２下側導体板１４２との間の接合は、継手はんだ層１２７、１４７に限られず、導電性を有する他の種類の接合層を介して接合されてもよい。 Therefore, in the semiconductor device 100 of the second embodiment, as in the semiconductor device 10 of the first embodiment, the joint member 16 and the third power terminal 16 can be formed of a single member in the joint structure 130. As a result, the number of parts can be reduced and the semiconductor device 100 can be downsized. In addition, joining between the base end portion 16b of the third power terminal 16 and the first upper conductor plate 126, and between the base end portion 16b of the third power terminal 16 and the second lower conductor plate 142, The joint solder layers 127 and 147 are not limited to the joint solder layers 127 and 147, and the joint solder layers 127 and 147 may be joined via another kind of joint layer having conductivity.
（実施例３）図７を参照して、実施例３の半導体装置２００について説明する。図７に示すように、実施例３の半導体装置２００では、実施例１の半導体装置１０と比較して、第３電力端子２１６（即ち、継手部材２１６）の構成が変更されている。具体的には、半導体素子２０、４０の並ぶ方向（図中のＸ方向）において、第３電力端子２１６の基端部２１６ｂの寸法が、第１継手部２８及び第２継手部４８の各寸法よりも小さい。なお、本実施例においても、第３電力端子２１６の基端部２１６ｂは、第１継手部２８と第２継手部４８との間に位置しており、第１継手部２８と第２継手部４８とのそれぞれに、第１継手はんだ層２２７又は第２継手はんだ層２４７を介して接合されている。 (Third Embodiment) A semiconductor device 200 according to a third embodiment will be described with reference to FIG. As shown in FIG. 7, in the semiconductor device 200 of the third embodiment, the configuration of the third power terminal 216 (that is, the joint member 216) is changed as compared with the semiconductor device 10 of the first embodiment. Specifically, in the direction in which the semiconductor elements 20 and 40 are arranged (X direction in the drawing), the dimensions of the base end portion 216b of the third power terminal 216 are the same as the dimensions of the first joint portion 28 and the second joint portion 48. Smaller than. Also in this embodiment, the base end portion 216b of the third power terminal 216 is located between the first joint portion 28 and the second joint portion 48, and the first joint portion 28 and the second joint portion 48 and the second joint solder layer 247, respectively.
　従って、実施例３の半導体装置２００では、実施例１の半導体装置１０と同様に、継手構造３０において、継手部材２１６と第３電力端子２１６とが単一の部材で構成されることができる。これにより、部品点数の削減や半導体装置２００の小型化を図ることができる。なお、第３電力端子２１６の基端部２１６ｂと第１上側導体板２６との間、及び、第３電力端子２１６の基端部２１６ｂと第２下側導体板４２との間の接合は、継手はんだ層２２７，２４７に限られず、導電性を有する他の種類の接合層を介して接合されてもよい。 Therefore, in the semiconductor device 200 of the third embodiment, as in the semiconductor device 10 of the first embodiment, the joint member 216 and the third power terminal 216 can be formed of a single member in the joint structure 30. As a result, the number of parts can be reduced and the semiconductor device 200 can be downsized. In addition, joining between the base end portion 216b of the third power terminal 216 and the first upper conductor plate 26, and between the base end portion 216b of the third power terminal 216 and the second lower conductor plate 42, The joint solder layers 227 and 247 are not limited to the joint solder layers 227 and 247, and the joint solder layers 227 and 247 may be joined via another kind of joint layer having conductivity.
　実施例３の半導体装置２００では、第１継手部２８が、第３電力端子２１６の基端部２１６ｂに、第１継手はんだ層２２７を介して接合されている。この場合、第１継手はんだ層２２７が第１継手部２８に接触する面積は、第１継手はんだ層２２７が基端部２１６ｂに接触する面積よりも大きい。このような構成によると、第１継手はんだ層２２７が良好なフィレット形状を形成して、第１継手部２８と第３電力端子２１６の基端部２１６ｂとの間がしっかりと接合される。なお、特に限定されないが、第１継手はんだ層２２７のフィレット角度は、鋭角（即ち、９０度未満）であるとよい。同様に、第２継手部４８は、第３電力端子２１６の基端部２１６ｂに、第２継手はんだ層２４７を介して接合されている。この場合、第２継手はんだ層２４７が第２継手部４８に接触する面積は、第２継手はんだ層２４７が基端部２１６ｂに接触する面積よりも大きい。このような構成によると、第２継手はんだ層２４７が良好なフィレット形状を形成して、第２継手部４８と第３電力端子２１６の基端部２１６ｂとの間がしっかりと接合される。第２継手はんだ層２４７についても、特に限定されないが、そのフィレット角度が鋭角（即ち、９０度未満）であるとよい。 In the semiconductor device 200 of the third embodiment, the first joint portion 28 is joined to the base end portion 216b of the third power terminal 216 via the first joint solder layer 227. In this case, the area where the first joint solder layer 227 contacts the first joint portion 28 is larger than the area where the first joint solder layer 227 contacts the base end portion 216b. With such a configuration, the first joint solder layer 227 forms a good fillet shape, and the first joint portion 28 and the base end portion 216b of the third power terminal 216 are firmly joined. Although not particularly limited, the fillet angle of the first joint solder layer 227 may be an acute angle (that is, less than 90 degrees). Similarly, the second joint portion 48 is joined to the base end portion 216b of the third power terminal 216 via the second joint solder layer 247. In this case, the area in which the second joint solder layer 247 contacts the second joint portion 48 is larger than the area in which the second joint solder layer 247 contacts the base end portion 216b. With such a configuration, the second joint solder layer 247 forms a good fillet shape, and the second joint portion 48 and the base end portion 216b of the third power terminal 216 are firmly joined. The second joint solder layer 247 is also not particularly limited, but its fillet angle may be an acute angle (that is, less than 90 degrees).
（実施例４）図８、図９を参照して、実施例４の半導体装置３００について説明する。図８、図９に示すように、実施例４の半導体装置３００は、実施例１の半導体装置１０と比較して、各々が絶縁基板３３４、３３８を備える一対の積層基板３３２、３３６をさらに備えている。後述するように、一対の積層基板３３２、３３６の一部は、実施例１における各導体板２２、２６、４２、４６に対応している。さらに、実施例４では、実施例１に対して継手構造３３０、特に、継手部材３１６の構造が変更されている。ここでは、継手部材３１６は、実施例１と同様に、第３電力端子３１６と一体に形成されている。また、実施例１では、各信号端子１２、１３は例えばはんだ層といった導電性を有する接合層を介して信号電極２０ｄ、４０ｄに電気的に接続されている。これに対し、実施例４では、各信号端子３１２、３１３は、例えばボンディングワイヤといった導電部材を介して信号電極２０ｄ、４０ｄに電気的に接続されている。それに伴い、各信号端子３１２、３１３は、ボンディングワイヤに代えた分だけ長さが比較的短く形成されている。 (Embodiment 4) A semiconductor device 300 of Embodiment 4 will be described with reference to FIGS. As shown in FIGS. 8 and 9, the semiconductor device 300 of the fourth embodiment further includes a pair of laminated substrates 332 and 336 each including insulating substrates 334 and 338, as compared with the semiconductor device 10 of the first embodiment. ing. As will be described later, a part of the pair of laminated substrates 332, 336 corresponds to each conductor plate 22, 26, 42, 46 in the first embodiment. Further, in the fourth embodiment, the joint structure 330, in particular, the joint member 316 is modified from the first embodiment. Here, the joint member 316 is integrally formed with the third power terminal 316, as in the first embodiment. In addition, in the first embodiment, the signal terminals 12 and 13 are electrically connected to the signal electrodes 20d and 40d via a conductive bonding layer such as a solder layer. On the other hand, in the fourth embodiment, the signal terminals 312 and 313 are electrically connected to the signal electrodes 20d and 40d via conductive members such as bonding wires. Along with this, the signal terminals 312 and 313 are formed to be relatively short by the amount of the bonding wires.
　なお、実施例４の半導体装置３００における各積層基板３３２、３３６、継手構造３３０、第３電力端子３１６、及び各信号端子３１２、３１３以外の他の部分については、実施例１の半導体装置１０と同様に構成されることができ、重複する説明は省略する。 The semiconductor device 300 according to the fourth embodiment is similar to the semiconductor device 10 according to the first embodiment except for the laminated substrates 332 and 336, the joint structure 330, the third power terminal 316, and the signal terminals 312 and 313. It can be configured in the same manner, and redundant description will be omitted.
　半導体装置３００は、第１半導体素子２０及び第２半導体素子４０を挟んで対向する下側積層基板３３２及び上側積層基板３３６を備える。下側積層基板３３２は、下側絶縁基板３３４と、第１下側導体板２２及び第２下側導体板４２とに加え、第３下側導体板３３５を有する。下側積層基板３３２において、下側絶縁基板３３４の一方（半導体素子２０、４０側）の面上には、第１下側導体板２２及び第２下側導体板４２が設けられており、下側絶縁基板３３４の他方（反半導体素子２０、４０側）の面上には第３下側導体板３３５が設けられている。上側積層基板３３６において、上側絶縁基板３３８の一方（半導体素子２０、４０側）の面上には、第１上側導体板２６及び第２上側導体板４６が設けられており、上側絶縁基板３３８の他方（反半導体素子２０、４０側）の面上には第３上側導体板３３９が設けられている。 The semiconductor device 300 includes a lower laminated substrate 332 and an upper laminated substrate 336 facing each other with the first semiconductor element 20 and the second semiconductor element 40 interposed therebetween. The lower laminated substrate 332 includes a lower insulating substrate 334, the first lower conductor plate 22 and the second lower conductor plate 42, and a third lower conductor plate 335. In the lower laminated substrate 332, the first lower conductor plate 22 and the second lower conductor plate 42 are provided on one surface of the lower insulating substrate 334 ( semiconductor element 20, 40 side). A third lower conductor plate 335 is provided on the other surface (on the side opposite to the semiconductor elements 20 and 40) of the side insulating substrate 334. In the upper laminated substrate 336, the first upper conductor plate 26 and the second upper conductor plate 46 are provided on one surface of the upper insulating substrate 338 (on the side of the semiconductor elements 20 and 40), and the upper insulating substrate 338 has A third upper conductor plate 339 is provided on the other surface (on the side opposite to the semiconductor elements 20 and 40).
　上述したが、各積層基板３３２、３３６の一方の面上の導体板２２、２６、４２、４６は、封止体１８の内部で第１半導体素子２０又は第２半導体素子４０と電気的及び熱的に接続されている。特に限定されないが、各積層基板３３２、３３６の他方の面上の導体板３３５、３３９は、封止体１８の主表面１８ａ、１８ｂに露出している。 As described above, the conductor plates 22, 26, 42, 46 on one surface of each of the laminated substrates 332, 336 are electrically and thermally coupled to the first semiconductor element 20 or the second semiconductor element 40 inside the sealing body 18. Connected to each other. Although not particularly limited, the conductor plates 335 and 339 on the other surface of each of the laminated substrates 332 and 336 are exposed on the main surfaces 18a and 18b of the sealing body 18.
　積層基板３３２、３３６は、例えばＤＢＣ（Direct Bonded Copper）基板である。絶縁基板３３４、３３８は、例えば酸化アルミニウム、窒化シリコン、窒化アルミニウム等といった、セラミック材料を用いて構成されている。また、第３下側導体板３３５及び第３上側導体板３３９は、他の導体板２２、２６、４２、４６と同様に、銅で構成されている。但し、積層基板３３２、３３６の具体的構成は、特に限定されない。積層基板３３２、３３６は、例えばＤＢＡ（Direct Bonded Aluminum）基板、ＡＭＢ（Active Metal Brazed Copper）基板、又は他の種類の積層基板を採用していてもよい。 The laminated substrates 332 and 336 are, for example, DBC (Direct Bonded Copper) substrates. The insulating substrates 334 and 338 are made of a ceramic material such as aluminum oxide, silicon nitride, or aluminum nitride. The third lower conductor plate 335 and the third upper conductor plate 339 are made of copper similarly to the other conductor plates 22, 26, 42, 46. However, the specific configuration of the laminated substrates 332 and 336 is not particularly limited. The laminated substrates 332 and 336 may employ, for example, a DBA (Direct Bonded Aluminum) substrate, an AMB (Active Metal Brazed Copper) substrate, or another type of laminated substrate.
　継手構造３３０は、第３電力端子３１６（即ち、継手部材３１６）の基端部３１６ｂを含んでおり、第１上側導体板２６は、第２下側導体板４２に基端部３１６ｂを介して接続されている。第３電力端子３１６は、幅広の先端部３１６ａとその先端部３１６ａから延びる基端部３１６ｂを有している。一例ではあるが、先端部３１６ａと基端部３１６ｂとの間には、先端部３１６ａ及び基端部３１６ｂの幅寸法に対して、Ｘ方向の幅寸法が比較的に小さいくびれ部が設けられている。基端部３１６ｂは、一端が第１上側導体板２６と部分的に対向しており、他端が第２下側導体板４２と部分的に対向している。 The joint structure 330 includes the base end portion 316b of the third power terminal 316 (that is, the joint member 316), and the first upper conductor plate 26 is connected to the second lower conductor plate 42 via the base end portion 316b. It is connected. The third power terminal 316 has a wide front end 316a and a base end 316b extending from the front end 316a. As an example, a constricted portion having a relatively small width dimension in the X direction with respect to the width dimension of the distal end portion 316a and the proximal end portion 316b is provided between the distal end portion 316a and the proximal end portion 316b. There is. One end of the base end portion 316b partially faces the first upper conductor plate 26, and the other end thereof partially faces the second lower conductor plate 42.
　第３電力端子３１６は、基端部３１６ｂにおいて、第１上側導体板２６と第１継手はんだ層３２７を介して接合された第１接合面ＢＡ１と、第２下側導体板４２と第２継手はんだ層３４７を介して接合された第２接合面ＢＡ２とを有する。従って、実施例４における継手構造３３０には、実施例１の継手構造３０ように第１継手部２８及び第２継手部４８が含まれない。また、第３電力端子３１６は、第１接合面ＢＡ１を有する第１板状部分３１６ｂ１と、第２接合面ＢＡ２を有する第２板状部分３１６ｂ２と、第１板状部分３１６ｂ１と第２板状部分３１６ｂ２との間を延びる中間板状部分３１６ｂ３とを有している。さらに、第３電力端子３１６は、第１板状部分３１６ｂ１と中間板状部分３１６ｂ３との間の境界と、第２板状部分３１６ｂ２と中間板状部分３１６ｂ３との間の境界に、屈曲部３１６ｗを有している。一例ではあるが、第１板状部分３１６ｂ１と第２板状部分３１６ｂ２は、中間板状部分３１６ｂ３に対して互いに反対方向に屈曲している。なお、第３電力端子３１６の基端部３１６ｂと第１上側導体板２６との間、及び、第３電力端子３１６の基端部３１６ｂと第２下側導体板４２との間の接合は、継手はんだ層３２７、３４７に限られず、導電性を有する他の種類の接合層を介して接合されてもよい。 The third power terminal 316 includes a first joint surface BA1 joined to the first upper conductor plate 26 via the first joint solder layer 327 at the base end portion 316b, a second lower conductor plate 42, and a second joint. The second bonding surface BA2 is bonded via the solder layer 347. Therefore, the joint structure 330 according to the fourth embodiment does not include the first joint portion 28 and the second joint portion 48, unlike the joint structure 30 according to the first embodiment. In addition, the third power terminal 316 includes a first plate-shaped portion 316b1 having a first bonding surface BA1, a second plate-shaped portion 316b2 having a second bonding surface BA2, a first plate-shaped portion 316b1 and a second plate-shaped portion. The intermediate plate-shaped portion 316b3 extends between the portion 316b2 and the portion 316b2. Further, the third power terminal 316 has a bent portion 316w at a boundary between the first plate-shaped portion 316b1 and the intermediate plate-shaped portion 316b3 and a boundary between the second plate-shaped portion 316b2 and the intermediate plate-shaped portion 316b3. have. As an example, the first plate-shaped portion 316b1 and the second plate-shaped portion 316b2 are bent in directions opposite to each other with respect to the intermediate plate-shaped portion 316b3. In addition, joining between the base end portion 316b of the third power terminal 316 and the first upper conductor plate 26, and between the base end portion 316b of the third power terminal 316 and the second lower conductor plate 42, The joint solder layers 327 and 347 are not limited to the joint solder layers 327 and 347, and the joint solder layers 327 and 347 may be joined via another kind of joint layer having conductivity.
　実施例４における半導体装置３００では、第３電力端子３１６に屈曲部３１６ｗを設けることで、第３電力端子３１６における変形性能（外力に応じて変形する性質）を高めることができる。これにより、半導体装置３００の構成部品を組み合わせるときに、第１上側導体板２６と第２下側導体板４２との間の位置関係に応じて、第３電力端子３１６は柔軟に変形することができる。第３電力端子３１６が柔軟に変形することで、第１上側導体板２６及び第２下側導体板４２が、対向する第１下側導体板２２又は第２上側導体板４６に対して意図せず傾くことを避けることができる。また、半導体装置３００の使用時においても、半導体装置３００に生じる熱膨張に応じて、第３電力端子３１６が柔軟に変形することにより、半導体装置３００の内部に生じる応力が緩和される。 In the semiconductor device 300 according to the fourth embodiment, by providing the bent portion 316w on the third power terminal 316, it is possible to enhance the deformation performance (the property of being deformed according to an external force) of the third power terminal 316. Thereby, when the components of the semiconductor device 300 are combined, the third power terminal 316 can be flexibly deformed according to the positional relationship between the first upper conductor plate 26 and the second lower conductor plate 42. it can. By the flexible deformation of the third power terminal 316, the first upper conductor plate 26 and the second lower conductor plate 42 are intended to be opposed to the opposing first lower conductor plate 22 or second upper conductor plate 46. You can avoid leaning. Further, even when the semiconductor device 300 is used, the third power terminal 316 flexibly deforms in response to the thermal expansion of the semiconductor device 300, so that the stress generated inside the semiconductor device 300 is relieved.
　実施例４における第３電力端子３１６は、第１板状部分３１６ｂ１と中間板状部分３１６ｂ３との間の境界と、第２板状部分３１６ｂ２と中間板状部分３１６ｂ３との間の境界との少なくとも一方に、屈曲部３１６ｗを有していてもよい。但し、第３電力端子３１６の具体的な構成は、特に限定されず、第１上側導体板２６と第２下側導体板４２との位置関係に応じて、適宜変更し設計することができる。 At least the boundary between the first plate-shaped portion 316b1 and the intermediate plate-shaped portion 316b3 and the boundary between the second plate-shaped portion 316b2 and the intermediate plate-shaped portion 316b3 is included in the third power terminal 316 in the fourth embodiment. On the other hand, the bent portion 316w may be included. However, the specific configuration of the third power terminal 316 is not particularly limited, and can be appropriately modified and designed according to the positional relationship between the first upper conductor plate 26 and the second lower conductor plate 42.
　図１０－１７を参照して、第３電力端子３１６（特に基端部３１６ｂ）における様々な変形例について説明する。図１０、図１１に示すように、第３電力端子３１６は、第１板状部分３１６ｂ１と中間板状部分３１６ｂ３との間の境界と、第２板状部分３１６ｂ２と中間板状部分３１６ｂ３との間の境界とに加え、中間板状部分３１６ｂ３にも少なくとも一つの（ここでは、二つの）屈曲部３１６ｗを有していてもよい。この場合に、中間板状部分３１６ｂ３の先端部３１６ａと基端部３１６ｂとの間において、両端にそれぞれくびれ部が設けられていてもよい。あるいは、図１２、１３に示すように、中間板状部分３１６ｂ３の先端部３１６ａと基端部３１６ｂとの間において、くびれ部が設けられていなくてもよい。即ち、先端部３１６ａから基端部３１６ｂに亘って、第３電力端子３１６の幅寸法が略一定に設けられていてよい。 Various modifications of the third power terminal 316 (particularly the base end portion 316b) will be described with reference to FIGS. As shown in FIGS. 10 and 11, the third power terminal 316 includes a boundary between the first plate-shaped portion 316b1 and the intermediate plate-shaped portion 316b3, a second plate-shaped portion 316b2, and an intermediate plate-shaped portion 316b3. In addition to the boundary between them, the intermediate plate-shaped portion 316b3 may also have at least one (here, two) bent portion 316w. In this case, constrictions may be provided at both ends between the tip end portion 316a and the base end portion 316b of the intermediate plate-shaped portion 316b3. Alternatively, as shown in FIGS. 12 and 13, the constricted portion may not be provided between the tip end portion 316a and the base end portion 316b of the intermediate plate-shaped portion 316b3. That is, the width dimension of the third power terminal 316 may be provided substantially constant from the tip end portion 316a to the base end portion 316b.
　また、実施例４における第３電力端子３１６は、基端部３１６ｂにおいて、第１板状部分３１６ｂ１と第２板状部分３１６ｂ２は、中間板状部分３１６ｂ３に対して互いに反対方向に屈曲している。第３電力端子３１６は、この形状に限定されず、図１４、１５に示すように、第１板状部分３１６ｂ１と第２板状部分３１６ｂ２は、中間板状部分３１６ｂ３に対して同じ方向に屈曲していてもよい。 Further, in the third power terminal 316 according to the fourth embodiment, at the base end portion 316b, the first plate-shaped portion 316b1 and the second plate-shaped portion 316b2 are bent in opposite directions to the intermediate plate-shaped portion 316b3. .. The third power terminal 316 is not limited to this shape, and as shown in FIGS. 14 and 15, the first plate-shaped portion 316b1 and the second plate-shaped portion 316b2 are bent in the same direction with respect to the intermediate plate-shaped portion 316b3. You may have.
　あるいは、図１６、１７に示すように、第３電力端子３１６は、中間板状部分３１６ｂ３を有していなくてもよい。この場合、第１板状部分３１６ｂ１と第２板状部分３１６ｂ２は、封止体１８の内部であって、各導体板２２、２６、４２、４６に対向しない領域において接続される。 Alternatively, as shown in FIGS. 16 and 17, the third power terminal 316 may not have the intermediate plate-shaped portion 316b3. In this case, the first plate-shaped portion 316b1 and the second plate-shaped portion 316b2 are connected inside the sealing body 18 in a region that does not face the conductor plates 22, 26, 42, 46.
　実施例４における半導体装置３００では、第１下側導体板２２及び第２下側導体板４２が共通の絶縁基板３３４に設けられており、第１上側導体板２６及び第２上側導体板４６が共通の絶縁基板３３８に設けられている。これに限定されず、各導体板２２、２６、４２、４６がそれぞれ異なる絶縁基板上に設けられていてもよいし、複数の導体板２２、２６、４２、４６のうちの少なくとも一つが絶縁基板上に設けられていてもよい。 In the semiconductor device 300 according to the fourth embodiment, the first lower conductor plate 22 and the second lower conductor plate 42 are provided on the common insulating substrate 334, and the first upper conductor plate 26 and the second upper conductor plate 46 are provided. It is provided on the common insulating substrate 338. However, the conductor plates 22, 26, 42, 46 may be provided on different insulating substrates, and at least one of the plurality of conductor plates 22, 26, 42, 46 may be an insulating substrate. It may be provided above.
　実施例４における半導体装置３００では、第３電力端子３１６は、第１半導体素子２０の厚み方向（即ち、Ｚ方向）における平面視において、第１接合面ＢＡ１と第２接合面ＢＡ２とのそれぞれは、第１半導体素子２０及び第２半導体素子４０の各中心を通過する直線ＳＬを跨いで広がっている。このような構成によると、第３電力端子３１６から各半導体素子２０、４０への距離を比較的に短くすることができ、電流経路におけるインダクタンスを低減することができる。 In the semiconductor device 300 according to the fourth embodiment, the third power terminal 316 has the first bonding surface BA1 and the second bonding surface BA2 in plan view in the thickness direction of the first semiconductor element 20 (that is, the Z direction). , The first semiconductor element 20 and the second semiconductor element 40 extend across a straight line SL passing through the respective centers. With such a configuration, the distance from the third power terminal 316 to each of the semiconductor elements 20 and 40 can be relatively short, and the inductance in the current path can be reduced.
　また、実施例４の半導体装置３００では、実施例１の半導体装置１０と同様に、継手部材３１６が第３電力端子３１６と一体に形成されている。即ち、継手構造３３０において、継手部材３１６と第３電力端子３１６とが単一の部材で構成されることができる。これにより、部品点数の削減や半導体装置３００の小型化を図ることができる。 Further, in the semiconductor device 300 of the fourth embodiment, the joint member 316 is integrally formed with the third power terminal 316, as in the semiconductor device 10 of the first embodiment. That is, in the joint structure 330, the joint member 316 and the third power terminal 316 can be configured by a single member. As a result, the number of parts can be reduced and the semiconductor device 300 can be downsized.
　先の実施例１－４で説明した継手構造３０、１３０、３３０を備える半導体装置１０、１００、２００、３００では、継手構造３０、１３０、３３０が存在する分だけ、半導体装置１０、１００、２００、３００を構成する部品点数が増加し、これによって工数が増加するといった製造工程の煩雑化に繋がるおそれがある。 In the semiconductor devices 10, 100, 200, 300 including the joint structures 30, 130, 330 described in the above-mentioned first to fourth embodiments, the semiconductor devices 10, 100, 200 have the joint structures 30, 130, 330. , 300 may increase the number of parts, which may increase the number of steps and complicate the manufacturing process.
　上記課題に対して、本実施例における半導体装置１０、１００、２００、３００は、第１半導体素子２０及び第２半導体素子４０と、第１半導体素子２０及び第２半導体素子４０を封止する封止体１８とを備える。半導体装置１０、１００、２００、３００は、第１下側導体板２２、第１上側導体板２６、１２６、第２下側導体板４２、１４２及び第２上側導体板４６を備える。第１下側導体板２２及び第１上側導体板２６、１２６は、第１半導体素子２０を挟んで対向するとともに、各々が封止体１８の内部で第１半導体素子２０へ電気的に接続されている。第２下側導体板４２、１４２及び第２上側導体板４６は、第２半導体素子４０を挟んで対向するとともに、各々が封止体１８の内部で第２半導体素子４０へ電気的に接続されている。また、半導体装置１０は、封止体１８の内部で第１上側導体板２６、１２６と第２下側導体板４２、１４２とを互いに電気的に接続する継手構造３０、１３０、３３０を備えており、その継手構造３０は、少なくとも一つの継手部材１６、２１６、３１６（即ち、第３電力端子１６、２１６、３１６）を含み、該継手部材１６、２１６、３１６の一部は封止体１８の外部に位置する。 With respect to the above problem, the semiconductor devices 10, 100, 200, and 300 according to the present embodiment are configured to seal the first semiconductor element 20 and the second semiconductor element 40, and the first semiconductor element 20 and the second semiconductor element 40. And a stopper 18. The semiconductor devices 10, 100, 200, 300 include a first lower conductor plate 22, first upper conductor plates 26, 126, second lower conductor plates 42, 142, and a second upper conductor plate 46. The first lower conductor plate 22 and the first upper conductor plates 26, 126 face each other with the first semiconductor element 20 in between, and are electrically connected to the first semiconductor element 20 inside the sealing body 18. ing. The second lower conductor plates 42 and 142 and the second upper conductor plate 46 face each other with the second semiconductor element 40 interposed therebetween, and are electrically connected to the second semiconductor element 40 inside the sealing body 18. ing. Further, the semiconductor device 10 includes joint structures 30, 130, 330 that electrically connect the first upper conductor plates 26, 126 and the second lower conductor plates 42, 142 to each other inside the sealing body 18. And the joint structure 30 includes at least one joint member 16, 216, 316 (i.e., the third power terminal 16, 216, 316), a portion of which is a sealing body 18. Located outside of.
　このような構成によると、封止体１８を形成する封止工程において、継手部材１６、２１６、３１６を封止体１８の外部から支持することができ、封止構造を精度よく形成しやすい。また、特に限定されないが、継手部材１６、２１６、３１６を、封止体１８の外部に位置する他の構成部材（例えば電力端子１４、１５や信号端子１２、１３、３１２、３１３等）とともに、一つの部材（いわゆるリードフレーム）として用意することができる。これにより、半導体装置１０、１００、２００、３００の製造工程が煩雑化することを抑制する。 With such a configuration, the joint members 16, 216, 316 can be supported from the outside of the sealing body 18 in the sealing step of forming the sealing body 18, and the sealing structure can be easily formed with high accuracy. In addition, although not particularly limited, the joint members 16, 216, 316 together with other constituent members (for example, the power terminals 14, 15 and the signal terminals 12, 13, 312, 313, etc.) located outside the sealing body 18, It can be prepared as one member (so-called lead frame). This prevents the manufacturing process of the semiconductor devices 10, 100, 200, 300 from becoming complicated.
（実施例５）図１８を参照して、実施例５の半導体装置４００について説明する。図１８に示すように、実施例５の半導体装置４００は、第１継手部２８、第２継手部４８と継手部材４１７とを含む継手構造４３０を備える。継手部材４１７は、第３電力端子４１６とは別個の部材で形成されており、この点において前述した他の実施例における半導体装置１０、１００、２００、３００とは異なる。従って、継手構造４３０は、第３電力端子４１６を含まない。それに伴って、第３電力端子４１６の構造も変更されており、第３電力端子４１６は、封止体１８の内部において、第２下側導体板４２に接続されており、第１電力端子１４及び第２電力端子１５と同様に、封止体１８の第１端面１８ｃから突出する。 (Embodiment 5) A semiconductor device 400 of Embodiment 5 will be described with reference to FIG. As shown in FIG. 18, the semiconductor device 400 of the fifth embodiment includes a joint structure 430 including the first joint portion 28, the second joint portion 48, and the joint member 417. The joint member 417 is formed as a member separate from the third power terminal 416, and this point is different from the semiconductor devices 10, 100, 200, 300 in the other embodiments described above. Therefore, the joint structure 430 does not include the third power terminal 416. Along with that, the structure of the third power terminal 416 is also changed, and the third power terminal 416 is connected to the second lower conductor plate 42 inside the sealing body 18, and the first power terminal 14 Also, like the second power terminal 15, it projects from the first end surface 18 c of the sealing body 18.
　実施例５の半導体装置４００における継手構造４３０及び第３電力端子４１６以外の他の構成について、実施例１、４に基づいて適宜構成されることができ、重複する説明は省略する。なお、図示していないが、継手部材４１７と第１継手部２８との間、及び、継手部材４１７と第２継手部４８との間は、例えばはんだ層といった導電性を有する接合層を介して接合されていてよい。 The configurations other than the joint structure 430 and the third power terminal 416 in the semiconductor device 400 of the fifth embodiment can be appropriately configured based on the first and fourth embodiments, and the duplicate description will be omitted. Although not shown, a space between the joint member 417 and the first joint portion 28 and between the joint member 417 and the second joint portion 48 are provided with a conductive joint layer such as a solder layer. It may be joined.
　継手部材４１７は、封止体１８の内部において、第１上側導体板２６及び第２下側導体板４２を接続する。それとともに、継手部材４１７の一部は、封止体１８の外部に位置する。一例ではあるが、継手部材４１７の一部は、封止体１８の第２端面１８ｄから突出している。但し、継手部材４１７の一部は、突出している必要はなく、封止体１８（本実施例では第２端面１８ｄ）から露出していればよい。本実施例における継手部材４１７は、封止体１８の外部において、端子として機能する必要はない。 The joint member 417 connects the first upper conductor plate 26 and the second lower conductor plate 42 inside the sealing body 18. At the same time, a part of the joint member 417 is located outside the sealing body 18. As an example, a part of the joint member 417 projects from the second end surface 18d of the sealing body 18. However, a part of the joint member 417 does not need to project, and may be exposed from the sealing body 18 (the second end surface 18d in this embodiment). The joint member 417 in this embodiment does not have to function as a terminal outside the sealing body 18.
　このような構成であっても、封止体１８を形成する封止工程において、継手部材４１７を封止体１８の外部から支持することができ、封止構造を精度よく形成しやすい。また、特に限定されないが、継手部材４１７を、封止体１８の外部に位置する他の構成部材（例えば電力端子１４、１５、４１６や信号端子３１２、３１３等）とともに、一つの部材（いわゆるリードフレーム）として用意することができる。これにより、半導体装置４００の製造工程が煩雑化することを抑制する。 Even with such a configuration, the joint member 417 can be supported from the outside of the sealing body 18 in the sealing step of forming the sealing body 18, and the sealing structure can be easily formed with high accuracy. In addition, although not particularly limited, the joint member 417 is provided as one member (so-called lead) together with other constituent members (for example, the power terminals 14, 15, 416, the signal terminals 312, 313, etc.) located outside the sealing body 18. It can be prepared as a frame). This prevents the manufacturing process of the semiconductor device 400 from becoming complicated.
　以上、いくつかの具体例を詳細に説明したが、これらは例示に過ぎず、請求の範囲を限定するものではない。請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。本明細書又は図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものである。 Above, some specific examples have been described in detail, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in the present specification or the drawings exert technical utility alone or in various combinations.
１０、１００、２００、３００、４００：半導体装置
１２、１３、３１２、３１３：信号端子
１４：第１電力端子
１５：第２電力端子
１６、２１６、３１６、４１６：第３電力端子
１６ａ、３１６ａ：先端部
１６ｂ、２１６ｂ、３１６ｂ：基端部
１８：封止体
１８ａ：第１主表面
１８ｂ：第２主表面
１８ｃ：第１端面
１８ｄ：第２端面
２０、４０：半導体素子
２０ａ、４０ａ：半導体基板
２０ｂ、４０ｂ：第１主電極
２０ｃ、４０ｃ：第２主電極
２０ｄ、４０ｄ：信号電極
２０ｅ、４０ｅ：ＩＧＢＴ構造
２０ｆ、４０ｆ：ダイオード構造
２１、２３、２５、４１、４３、４５：はんだ層
２２：第１下側導体板
２４、４４：導体スペーサ
２６、１２６：第１上側導体板
２６ｃ：側面
２７、１２７、２２７、３２７：第１継手はんだ層
２８：第１継手部
３０、１３０、３３０、４３０：継手構造
４２、１４２：第２下側導体板
４２ｃ：側面
４６：第２上側導体板
４８：第２継手部
３１６ｂ１：第１板状部分
３１６ｂ２：第２板状部分
３１６ｂ３：中間板状部分
３１６ｗ：屈曲部
３３２、３３６：積層基板
３３４、３３８：絶縁基板
４７、１４７、２４７、３４７：第２継手はんだ層
４１７：継手部材
ＢＡ１、ＢＡ２：接合部 10, 100, 200, 300, 400: semiconductor device 12, 13, 312, 313: signal terminal 14: first power terminal 15: second power terminal 16, 216, 316, 416: third power terminal 16a, 316a: Tip part 16b, 216b, 316b: Base end part 18: Sealing body 18a: First main surface 18b: Second main surface 18c: First end surface 18d: Second end surface 20, 40: Semiconductor elements 20a, 40a: Semiconductor substrate 20b, 40b: 1st main electrode 20c, 40c: 2nd main electrode 20d, 40d: Signal electrode 20e, 40e: IGBT structure 20f, 40f: Diode structure 21, 23, 25, 41, 43, 45: Solder layer 22: First lower conductor plate 24, 44: Conductor spacer 26, 126: First upper conductor plate 26c: Side face 27, 127, 227, 327: First joint solder layer 28: First joint portion 30, 130, 330, 430 : Joint structure 42, 142: Second lower conductor plate 42c: Side surface 46: Second upper conductor plate 48: Second joint portion 316b1: First plate portion 316b2: Second plate portion 316b3: Intermediate plate portion 316w : Bent portions 332, 336: Laminated substrates 334, 338: Insulating substrates 47, 147, 247, 347: Second joint solder layer 417: Joint members BA1, BA2: Joint portions

Claims (25)

  1. 　第１半導体素子及び第２半導体素子と、
    　前記第１半導体素子及び前記第２半導体素子を封止する封止体と、
    　前記第１半導体素子を挟んで対向するとともに、各々が前記封止体の内部で前記第１半導体素子へ電気的に接続された第１導体板及び第２導体板と、
    　前記第２半導体素子を挟んで対向するとともに、各々が前記封止体の内部で前記第２半導体素子へ電気的に接続された第３導体板及び第４導体板と、
    　前記封止体の内部で前記第２導体板と前記第３導体板とを互いに電気的に接続する継手構造と、を備え、
    　前記継手構造は、少なくとも一つの継手部材を含み、前記継手部材の一部は前記封止体の外部に位置する、
    　半導体装置。     A first semiconductor element and a second semiconductor element;
    A sealing body that seals the first semiconductor element and the second semiconductor element;
    A first conductor plate and a second conductor plate that are opposed to each other with the first semiconductor element interposed therebetween and are electrically connected to the first semiconductor element inside the sealing body;
    A third conductor plate and a fourth conductor plate that face each other with the second semiconductor element interposed therebetween and are electrically connected to the second semiconductor element inside the sealing body;
    A joint structure for electrically connecting the second conductor plate and the third conductor plate to each other inside the sealing body,
    The joint structure includes at least one joint member, and a part of the joint member is located outside the sealing body.
    Semiconductor device.
  2. 　前記封止体の外部に位置する前記継手部材の前記一部は、前記第１半導体素子又は前記第２半導体素子を外部の回路へ電気的に接続するための電力端子として機能する、請求項１に記載の半導体装置。 The part of the joint member located outside the sealing body functions as a power terminal for electrically connecting the first semiconductor element or the second semiconductor element to an external circuit. The semiconductor device according to.
  3. 　前記継手部材は、前記封止体の内部で前記第２導体板に接合された第１接合面と、前記封止体の内部で前記第３導体板に接合された第２接合面とを有する、請求項１又は２に記載の半導体装置。 The joint member has a first joint surface that is joined to the second conductor plate inside the sealing body, and a second joint surface that is joined to the third conductor plate inside the sealing body. The semiconductor device according to claim 1 or 2.
  4. 　前記継手部材は、前記第１接合面を有する第１板状部分と、前記第２接合面を有する第２板状部分と、前記第１板状部分と前記第２板状部分との間を延びる中間板状部分とを有する、請求項３に記載の半導体装置。 The joint member includes a first plate-shaped portion having the first joint surface, a second plate-shaped portion having the second joint surface, and a portion between the first plate-shaped portion and the second plate-shaped portion. The semiconductor device according to claim 3, further comprising an intermediate plate-shaped portion that extends.
  5. 　前記継手部材は、前記第１板状部分と前記中間板状部分との間の境界と、前記第２板状部分と前記中間板状部分との間の境界との少なくとも一方に、屈曲部を有する、請求項４に記載の半導体装置。 The joint member has a bent portion on at least one of a boundary between the first plate-shaped portion and the intermediate plate-shaped portion and a boundary between the second plate-shaped portion and the intermediate plate-shaped portion. The semiconductor device according to claim 4, which has.
  6. 　前記第１板状部分と前記第２板状部分は、前記中間板状部分に対して同じ方向に屈曲している、請求項５に記載の半導体装置。 The semiconductor device according to claim 5, wherein the first plate-shaped portion and the second plate-shaped portion are bent in the same direction with respect to the intermediate plate-shaped portion.
  7. 　前記第１板状部分と前記第２板状部分は、前記中間板状部分に対して互いに反対方向へ屈曲している、請求項５に記載の半導体装置。 The semiconductor device according to claim 5, wherein the first plate-shaped portion and the second plate-shaped portion are bent in mutually opposite directions with respect to the intermediate plate-shaped portion.
  8. 　前記継手部材は、前記中間板状部分に少なくとも一つの屈曲部を有する、請求項６又は７に記載の半導体装置。 The semiconductor device according to claim 6 or 7, wherein the joint member has at least one bent portion in the intermediate plate-shaped portion.
  9. 　前記継手部材は、前記第１接合面を一方側に有するとともに前記第２接合面を他方側に有する共通板状部分を有する、請求項３に記載の半導体装置。 The semiconductor device according to claim 3, wherein the joint member has a common plate-shaped portion having the first joint surface on one side and the second joint surface on the other side.
  10. 　前記第１半導体素子の厚み方向における平面視において、前記第１接合面と前記第２接合面とのそれぞれは、前記第１半導体素子及び前記第２半導体素子の各中心を通過する直線を跨いで広がる、請求項３から９のいずれか一項に記載の半導体装置。 In a plan view in the thickness direction of the first semiconductor element, each of the first bonding surface and the second bonding surface straddles a straight line passing through each center of the first semiconductor element and the second semiconductor element. The semiconductor device according to claim 3, wherein the semiconductor device spreads.
  11. 　前記封止体の内部で前記第１導体板に接続されているとともに、前記封止体から突出する第１電力端子と、
    　前記封止体の内部で前記第４導体板に接続されているとともに、前記封止体から突出する第２電力端子と、
    　前記封止体の内部で前記第２導体板及び前記第３導体板に接続された第３電力端子と、
    　をさらに備え、
    　前記継手部材は、前記第３電力端子の基端部に一体に形成されている、請求項１に記載の半導体装置。     A first power terminal that is connected to the first conductor plate inside the sealing body and projects from the sealing body;
    A second power terminal connected to the fourth conductor plate inside the sealing body and protruding from the sealing body;
    A third power terminal connected to the second conductor plate and the third conductor plate inside the sealing body;
    Further equipped with,
    The semiconductor device according to claim 1, wherein the joint member is integrally formed with a base end portion of the third power terminal.
  12. 　前記第１導体板と前記第３導体板は、第１の平面に沿って配置され、
    　前記第２導体板と前記第４導体板は、前記第１の平面に平行な第２の平面に沿って配置されている、
    　請求項１１に記載の半導体装置。     The first conductor plate and the third conductor plate are arranged along a first plane,
    The second conductor plate and the fourth conductor plate are arranged along a second plane parallel to the first plane.
    The semiconductor device according to claim 11.
  13. 　前記継手構造は、
    　前記第２導体板に設けられており、前記第２導体板から前記第４導体板に向かって延びる第１継手部と、
    　前記第３導体板に設けられており、前記第３導体板から前記第１導体板に向かって延びる第２継手部と、
    　を含み、
    　前記第１継手部は、前記第２継手部に少なくとも部分的に対向しており、
    　前記第３電力端子の前記基端部は、前記第１継手部と前記第２継手部との間において、前記第１継手部と前記第２継手部とのそれぞれに接続されている、
    　請求項１１又は１２に記載の半導体装置。     The joint structure is
    A first joint portion provided on the second conductor plate and extending from the second conductor plate toward the fourth conductor plate;
    A second joint portion provided on the third conductor plate and extending from the third conductor plate toward the first conductor plate;
    Including
    The first joint portion at least partially opposes the second joint portion,
    The base end portion of the third power terminal is connected to each of the first joint portion and the second joint portion between the first joint portion and the second joint portion,
    The semiconductor device according to claim 11.
  14. 　前記第１継手部は、前記第２導体板の前記第４導体板と対向する一側面から延びており、
    　前記第２継手部は、前記第３導体板の前記第１導体板と対向する一側面から延びている、請求項１３に記載の半導体装置。     The first joint portion extends from one side surface of the second conductor plate facing the fourth conductor plate,
    The semiconductor device according to claim 13, wherein the second joint portion extends from one side surface of the third conductor plate that faces the first conductor plate.
  15. 　前記第１継手部の厚みは、前記第２導体板の厚みより小さい、請求項１３又は１４に記載の半導体装置。 The semiconductor device according to claim 13 or 14, wherein the thickness of the first joint portion is smaller than the thickness of the second conductor plate.
  16. 　前記第２継手部の厚みは、前記第３導体板の厚みより小さい、請求項１３から１５のいずれか一項に記載の半導体装置。 The semiconductor device according to any one of claims 13 to 15, wherein a thickness of the second joint portion is smaller than a thickness of the third conductor plate.
  17. 　前記第１継手部は、前記第３電力端子の前記基端部に第１継手接合層を介して接合されており、
    　前記第１継手接合層が前記第１継手部に接触する面積は、前記第１継手接合層が前記基端部に接触する面積よりも大きい、請求項１３から１６のいずれか一項に記載の半導体装置。     The first joint portion is joined to the base end portion of the third power terminal via a first joint joining layer,
    The area in which the first joint bonding layer is in contact with the first joint portion is larger than the area in which the first joint joint layer is in contact with the base end portion. Semiconductor device.
  18. 　前記第２継手部は、前記第３電力端子の前記基端部に第２継手接合層を介して接合されており、
    　前記第２継手接合層が前記第２継手部に接触する面積は、前記第２継手接合層が前記基端部に接触する面積よりも大きい、請求項１３から１７のいずれか一項に記載の半導体装置。     The second joint portion is joined to the base end portion of the third power terminal via a second joint joining layer,
    The area in which the second joint bonding layer is in contact with the second joint portion is larger than the area in which the second joint joint layer is in contact with the base end portion. Semiconductor device.
  19. 　前記第１電力端子及び前記第２電力端子は、前記封止体の第１端面から、互いに平行に突出している、請求項１１から１８のいずれか一項に記載の半導体装置。 The semiconductor device according to any one of claims 11 to 18, wherein the first power terminal and the second power terminal project from the first end surface of the sealing body in parallel with each other.
  20. 　前記第３電力端子は、前記封止体の前記第１端面とは反対側に位置する第２端面から突出している、請求項１９に記載の半導体装置。 20. The semiconductor device according to claim 19, wherein the third power terminal projects from a second end surface of the sealing body, which is located on a side opposite to the first end surface.
  21. 　前記封止体は、互いに反対側に位置するとともに前記第１端面と前記第２端面との間に延びている第１主表面及び第２主表面を有し、
    　前記第１主表面は前記第１導体板及び前記第３導体板を露出し、
    　前記第２主表面は前記第２導体板及び前記第４導体板を露出する、請求項２０に記載の半導体装置。     The sealing body has a first main surface and a second main surface that are located on opposite sides and extend between the first end surface and the second end surface,
    The first major surface exposes the first conductor plate and the third conductor plate,
    The semiconductor device according to claim 20, wherein the second main surface exposes the second conductor plate and the fourth conductor plate.
  22. 　絶縁基板をさらに備え、
    　前記第１導体板、前記第２導体板、前記第３導体板及び前記第４導体板の少なくとも一つは、前記絶縁基板上に設けられている、請求項１から２０のいずれか一項に記載の半導体装置。     Further comprising an insulating substrate,
    21. At least one of the first conductor plate, the second conductor plate, the third conductor plate, and the fourth conductor plate is provided on the insulating substrate, according to claim 1. The semiconductor device described.
  23. 　前記第１半導体素子と前記第２半導体素子とのそれぞれは、スイッチング素子である、請求項１から２２のいずれか一項に記載の半導体装置。 23. The semiconductor device according to claim 1, wherein each of the first semiconductor element and the second semiconductor element is a switching element.
  24. 　前記第１半導体素子と前記第２半導体素子とのそれぞれは、ＩＧＢＴ（Insulated Gate Bipolar Transistor）構造を有し、
    　前記第１半導体素子の前記ＩＧＢＴ構造は、前記第１導体板に接続されたコレクタと、前記第２導体板に接続されたエミッタとを有し、
    　前記第２半導体素子の前記ＩＧＢＴ構造は、前記第３導体板に接続されたコレクタと、前記第４導体板に接続されたエミッタとを有する、請求項１から２３のいずれか一項に記載の半導体装置。     Each of the first semiconductor element and the second semiconductor element has an IGBT (Insulated Gate Bipolar Transistor) structure,
    The IGBT structure of the first semiconductor element has a collector connected to the first conductor plate and an emitter connected to the second conductor plate,
    24. The IGBT structure of the second semiconductor element according to claim 1, wherein the IGBT structure includes a collector connected to the third conductor plate and an emitter connected to the fourth conductor plate. Semiconductor device.
  25. 　前記第１半導体素子と前記第２半導体素子とのそれぞれは、ＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Field-Effect Transistor）構造を有し、
    　前記第１半導体素子の前記ＭＯＳＦＥＴ構造は、前記第１導体板に接続されたドレインと、前記第２導体板に接続されたソースとを有し、
    　前記第２半導体素子の前記ＭＯＳＦＥＴ構造は、前記第３導体板に接続されたドレインと、前記第４導体板に接続されたソースとを有する、請求項１から２３のいずれか一項に記載の半導体装置。     Each of the first semiconductor element and the second semiconductor element has a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) structure,
    The MOSFET structure of the first semiconductor element has a drain connected to the first conductor plate and a source connected to the second conductor plate,
    24. The MOSFET structure of the second semiconductor element according to claim 1, wherein the MOSFET structure has a drain connected to the third conductor plate and a source connected to the fourth conductor plate. Semiconductor device.
PCT/JP2019/040223 2019-01-08 2019-10-11 Semiconductor device WO2020144907A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2020565583A JP7192886B2 (en) 2019-01-08 2019-10-11 semiconductor equipment

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019001443 2019-01-08
JP2019-001443 2019-01-08

Publications (1)

Publication Number Publication Date
WO2020144907A1 true WO2020144907A1 (en) 2020-07-16

Family

ID=71520337

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2019/040223 WO2020144907A1 (en) 2019-01-08 2019-10-11 Semiconductor device

Country Status (2)

Country Link
JP (1) JP7192886B2 (en)
WO (1) WO2020144907A1 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004241734A (en) * 2003-02-10 2004-08-26 Toyota Industries Corp Semiconductor module
JP2006080153A (en) * 2004-09-07 2006-03-23 Toshiba Corp Semiconductor device
JP2010287737A (en) * 2009-06-11 2010-12-24 Renesas Electronics Corp Semiconductor device
JP2013101993A (en) * 2011-11-07 2013-05-23 Denso Corp Semiconductor device
JP2017063136A (en) * 2015-09-25 2017-03-30 トヨタ自動車株式会社 Semiconductor device
JP2018117048A (en) * 2017-01-18 2018-07-26 株式会社デンソー Semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004241734A (en) * 2003-02-10 2004-08-26 Toyota Industries Corp Semiconductor module
JP2006080153A (en) * 2004-09-07 2006-03-23 Toshiba Corp Semiconductor device
JP2010287737A (en) * 2009-06-11 2010-12-24 Renesas Electronics Corp Semiconductor device
JP2013101993A (en) * 2011-11-07 2013-05-23 Denso Corp Semiconductor device
JP2017063136A (en) * 2015-09-25 2017-03-30 トヨタ自動車株式会社 Semiconductor device
JP2018117048A (en) * 2017-01-18 2018-07-26 株式会社デンソー Semiconductor device

Also Published As

Publication number Publication date
JPWO2020144907A1 (en) 2021-11-11
JP7192886B2 (en) 2022-12-20

Similar Documents

Publication Publication Date Title
CN109599384B (en) Semiconductor device with a plurality of transistors
JP7069787B2 (en) Semiconductor device
CN110364520B (en) Semiconductor device with a semiconductor device having a plurality of semiconductor chips
US20220199578A1 (en) Semiconductor device
KR20190095144A (en) Semiconductor device
CN110600457A (en) Semiconductor device with a plurality of semiconductor chips
US10566295B2 (en) Semiconductor device
CN111354710A (en) Semiconductor device and method for manufacturing the same
WO2020144907A1 (en) Semiconductor device
JP7077893B2 (en) Semiconductor device
JP7147186B2 (en) semiconductor equipment
JP7103533B2 (en) Semiconductor equipment
JP7147187B2 (en) semiconductor equipment
JP7159609B2 (en) semiconductor equipment
WO2020189065A1 (en) Semiconductor device
WO2022264833A1 (en) Semiconductor device
JP7106891B2 (en) semiconductor equipment
US20200266130A1 (en) Semiconductor device
WO2020025994A1 (en) Semiconductor device
JP2019140364A (en) Semiconductor device
JP2021111719A (en) Semiconductor device
JP2020188172A (en) Semiconductor device
JP2020188169A (en) Semiconductor device
JP2019153751A (en) Semiconductor device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19908832

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2020565583

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19908832

Country of ref document: EP

Kind code of ref document: A1