JP3450803B2 - Resin-sealed semiconductor device - Google Patents

Resin-sealed semiconductor device

Info

Publication number
JP3450803B2
JP3450803B2 JP2000188191A JP2000188191A JP3450803B2 JP 3450803 B2 JP3450803 B2 JP 3450803B2 JP 2000188191 A JP2000188191 A JP 2000188191A JP 2000188191 A JP2000188191 A JP 2000188191A JP 3450803 B2 JP3450803 B2 JP 3450803B2
Authority
JP
Japan
Prior art keywords
electrode terminal
resin
semiconductor device
semiconductor chip
source electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000188191A
Other languages
Japanese (ja)
Other versions
JP2002009219A (en
Inventor
木 健 之 鈴
田 辰 雄 米
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2000188191A priority Critical patent/JP3450803B2/en
Publication of JP2002009219A publication Critical patent/JP2002009219A/en
Application granted granted Critical
Publication of JP3450803B2 publication Critical patent/JP3450803B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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  • Engineering & Computer Science (AREA)
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  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】この発明は樹脂封止型半導体
装置に係り、特に、パワーMOSFET等の樹脂封止型半導体
装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device, and more particularly to a resin-sealed semiconductor device such as a power MOSFET.

【０００２】[0002]

【従来の技術および発明が解決しようとする課題】パワ
ーMOSFET等の樹脂封止型半導体装置１０は図５、図６に
示すようにプリント基板１１に取り付けられ、ノート型
パソコン、その他の電子機器のDC-DCコンバータ等に使
用するようになっている。2. Description of the Related Art A resin-encapsulated semiconductor device 10 such as a power MOSFET is mounted on a printed circuit board 11 as shown in FIGS. 5 and 6, and is used in notebook computers and other electronic equipment. It is designed to be used in DC-DC converters.

【０００３】この樹脂封止型半導体装置１０にはパワー
MOSFET等の半導体チップ１２が備えられ、これを平板状
のフレーム基板１３に搭載するようになっている。この
フレーム基板１３の下側には図示するように半導体チッ
プ１２の複数のドレイン電極端子１４が並列に設けら
れ、入力電流を受けるようになっている。The resin-encapsulated semiconductor device 10 has a power
A semiconductor chip 12 such as a MOSFET is provided and mounted on a flat frame substrate 13. A plurality of drain electrode terminals 14 of the semiconductor chip 12 are provided in parallel on the lower side of the frame substrate 13 so as to receive an input current.

【０００４】半導体チップ１２の上側には図示するよう
にCu等の複数のボンデングワイヤ１５を介してソース基
板１６が接続され、これに複数のソース電極端子１７を
複数のドレイン電極端子１４に対向して並列に設けこれ
から出力電流を出力するようになっている。A source substrate 16 is connected to the upper side of the semiconductor chip 12 via a plurality of bonding wires 15 such as Cu, and a plurality of source electrode terminals 17 are opposed to the plurality of drain electrode terminals 14 to this. They are arranged in parallel and the output current is output from this.

【０００５】半導体チップ１２の図示左側部にはゲート
ワイヤ用パッド１８が備えられ、これにCu等のボンデン
グワイヤ１９を接続するようになっている。このボンデ
ングワイヤ１９にはゲート電極端子２０が接続され、制
御電圧を受けるようになっている。A gate wire pad 18 is provided on the left side of the semiconductor chip 12 in the drawing, and a bonding wire 19 such as Cu is connected to the pad 18. A gate electrode terminal 20 is connected to the bonding wire 19 so as to receive a control voltage.

【０００６】これら半導体チップ１２、フレーム基板１
３の外周全面には一部のドレイン電極端子１４、ソース
電極端子１７、ゲート電極端子２０等とともに樹脂２１
で封止され、半導体チップ１２等を覆い小型・薄型の実
装外囲器（Small-Outline-Packeage「一般にSOP」と言
う）の樹脂封止型半導体装置１０を形成するようになっ
ている。These semiconductor chip 12 and frame substrate 1
A part of the drain electrode terminal 14, source electrode terminal 17, gate electrode terminal 20, etc.
The resin-encapsulated semiconductor device 10 which is a small-sized and thin mounting envelope (generally referred to as SOP) that is encapsulated with the semiconductor chip 12 and covers the semiconductor chip 12 is formed.

【０００７】この樹脂封止型半導体装置１０はプリント
基板１１の金属配線１１Aに接続するように取り付けら
れ、DC-DCコンバータ等に使用されるようになってい
る。The resin-encapsulated semiconductor device 10 is attached so as to be connected to the metal wiring 11A of the printed board 11, and is used for a DC-DC converter or the like.

【０００８】このようにして製造した樹脂封止型半導体
装置１０の半導体チップ１２は一般に高入力インピーダ
ンスに形成され、ドライブ回路等の簡素化を図るように
している。The semiconductor chip 12 of the resin-sealed semiconductor device 10 thus manufactured is generally formed to have a high input impedance, so that the drive circuit and the like can be simplified.

【０００９】この樹脂封止型半導体装置１０はゲート電
極端子２０の制御電圧によりON-OFFされ、ドレイン電極
端子１４からソース電極端子１７に流れる出力電流を制
御する。この出力電流効率は導体チップ１２のON時のロ
ス（定常ロス）とそのON-OFF時のロス（スイッチングロ
ス）とにより決まる。The resin-sealed semiconductor device 10 is turned on / off by the control voltage of the gate electrode terminal 20, and controls the output current flowing from the drain electrode terminal 14 to the source electrode terminal 17. This output current efficiency is determined by the loss when the conductor chip 12 is ON (steady loss) and the loss when the conductor chip 12 is ON-OFF (switching loss).

【００１０】そのため、この樹脂封止型半導体装置１０
の特性を改善するには半導体チップ１２のON時の抵抗を
含むインピーダンスを小さくすることやスイッチングス
ピード、すなわち、動作周波数を向上するようにしてい
る。Therefore, the resin-sealed semiconductor device 10
In order to improve the characteristic (1), the impedance including the resistance when the semiconductor chip 12 is turned on is reduced and the switching speed, that is, the operating frequency is improved.

【００１１】そこでこの種の樹脂封止型半導体装置１０
では下式で示す半導体チップ１２のON時のインピーダン
スを１／１０Ω〜１／１５Ω程度に小さくし動作周波数
を１００KHz〜３００KHz以上にしている。 １／Z＝１／r＋１／２πfL ただしZL＝２πfL ここでZは半導体チップ１２のインピーダンス、rは半導
体チップ１２の抵抗、Lはドレイン電極端子１４、ソー
ス電極端子１７、ボンデングワイヤ１５、１９等のイン
ダクタンス。Therefore, this type of resin-sealed semiconductor device 10 is provided.
Then, the impedance when the semiconductor chip 12 shown in the following formula is ON is reduced to about 1 / 10Ω to 1 / 15Ω and the operating frequency is set to 100 KHz to 300 KHz or more. 1 / Z = 1 / r + 1 / 2πfL where ZL = 2πfL where Z is the impedance of the semiconductor chip 12, r is the resistance of the semiconductor chip 12, L is the drain electrode terminal 14, the source electrode terminal 17, the bonding wires 15, 19 and the like. Inductance of.

【００１２】しかし、最近の樹脂封止型半導体装置１０
では動作周波数が非常に高くななってきたのでインピー
ダンスの低減やスイッチングスピードの向上に限界が生
じるようになってきた。これは高周波動作におけるイン
ピーダンスの増加によるものとこれによる半導体チップ
の発熱が高くなるためであると考えられる。そのため、
このような樹脂封止型半導体装置１０ではゲート電極端
子２０からの制御電圧による影響を受け不要なノイズを
発生させると言う問題があった。また、このような樹脂
封止型半導体装置１０を単にプリント基板１１に取り付
けたものでは放熱が不十分となりこれを高温にさせてし
まうと言う問題があった。However, the recent resin-sealed semiconductor device 10
Since the operating frequency has become extremely high, there are limits to reducing impedance and improving switching speed. It is considered that this is because the impedance of the semiconductor chip is increased during high-frequency operation and the heat generated by the semiconductor chip is increased. for that reason,
Such a resin-sealed semiconductor device 10 has a problem that unnecessary noise is generated due to the influence of the control voltage from the gate electrode terminal 20. In addition, there is a problem that heat radiation is insufficient and the temperature is raised to a high degree when the resin-encapsulated semiconductor device 10 is simply attached to the printed circuit board 11.

【００１３】そこで本発明は動作周波数が向上してもイ
ンピーダンスが高くならないようにするとともにそのイ
ンピーダンスによる発熱を抑えるようにした樹脂封止型
半導体装置を提供することを目的とするものである。Therefore, an object of the present invention is to provide a resin-sealed semiconductor device in which the impedance does not become high even if the operating frequency is improved and the heat generation due to the impedance is suppressed.

【００１４】[0014]

【課題を解決するための手段】請求項１の発明は半導体
チップを搭載するフレーム基板と、このフレーム基板に
取り付ける半導体チップのドレイン電極端子、ソース電
極端子、ゲート電極端子と、前記フレーム基板に取り付
ける半導体チップのグランド端子と、これら半導体チッ
プ、フレーム基板、一部のドレイン電極端子、ソース電
極端子、ゲート電極端子およびグランド端子を封止する
樹脂と、この樹脂により封止した半導体チップ、フレー
ム基板、ドレイン電極端子、ソース電極端子、ゲート電
極端子およびグランド端子を取付けるプリント基板とを
備え、前記グランド端子はゲート電極端子とソース電極
端子との間に形成するようにして、高周波動作運転時に
おける半導体装置のノイズを低減するようにしたもので
ある。According to a first aspect of the present invention, a frame substrate on which a semiconductor chip is mounted, a drain electrode terminal, a source electrode terminal, and a gate electrode terminal of the semiconductor chip mounted on the frame substrate, and the frame substrate are mounted on the frame substrate. A resin for sealing the ground terminal of the semiconductor chip, the semiconductor chip, the frame substrate, a part of the drain electrode terminal, the source electrode terminal, the gate electrode terminal and the ground terminal, and the semiconductor chip sealed by the resin, the frame substrate, A semiconductor device at the time of high-frequency operation operation, comprising a printed circuit board on which a drain electrode terminal, a source electrode terminal, a gate electrode terminal and a ground terminal are mounted, the ground terminal being formed between the gate electrode terminal and the source electrode terminal. The noise of is reduced.

【００１５】また、請求項２、の発明はグランド端子は
ソース電極端子を分離して形成し、ノイズの低減を容易
に行うようにしたものである。According to the second aspect of the present invention, the ground terminal is formed by separating the source electrode terminal so that noise can be easily reduced.

【００１６】さらに、請求項３，４、５の発明は半導体
チップとソース電極端子、ゲート電極端子およびグラン
ド端子とをAuの低インピーダンスのボンデングワイヤあ
るいは金属板により接続するようにしたから半導体装置
のインピーダンスを低減することができる。Further, according to the present invention, the semiconductor chip and the source electrode terminal, the gate electrode terminal and the ground terminal are connected by a low impedance bonding wire of Au or a metal plate. The impedance of can be reduced.

【００１７】さらに、請求項６，７の発明はフレーム基
板の裏面がプリント基板の上面に直接に接するように樹
脂を封止あるいはフレーム基板、各電極端子の裏面がプ
リント基板の上面に直接に接するように樹脂を封止した
から半導体装置の放熱を高めることができる。Further, in the invention of claims 6 and 7, resin is sealed so that the back surface of the frame substrate directly contacts the upper surface of the printed circuit board, or the back surface of the frame substrate and each electrode terminal directly contacts the upper surface of the printed circuit board. Since the resin is sealed as described above, heat dissipation of the semiconductor device can be enhanced.

【００１８】[0018]

【発明の実施の形態】以下本発明樹脂封止型半導体装置
の第１の実施の形態を図１、図２を用いて説明する。こ
の本発明樹脂封止型半導体装置３０は基本的には従来の
樹脂封止型半導体装置１０とほぼ同様であるからこの樹
脂封止型半導体装置１０と同一部分は同一符号を付して
本発明樹脂封止型半導体装置３０を説明する。BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment of a resin-encapsulated semiconductor device of the present invention will be described below with reference to FIGS. Since the resin-encapsulated semiconductor device 30 of the present invention is basically similar to the conventional resin-encapsulated semiconductor device 10, the same parts as those of the resin-encapsulated semiconductor device 10 are designated by the same reference numerals. The resin-sealed semiconductor device 30 will be described.

【００１９】この樹脂封止型半導体装置３０には半導体
チップ１２が備えられ、その裏面にはPb-Sb系の半田を
用いて平板状のフレーム基板１３に固着するようになっ
ている。The resin-encapsulated semiconductor device 30 is provided with a semiconductor chip 12, and the back surface of the semiconductor chip 12 is fixed to a flat frame substrate 13 using Pb-Sb type solder.

【００２０】フレーム基板１３の下側部には直線的に延
びる複数のドレイン電極端子３１が並列に取り付けら
れ、これを半導体チップ１２の図示しないドレイン部に
接続するようになっている。A plurality of linearly extending drain electrode terminals 31 are mounted in parallel on the lower side of the frame substrate 13, and are connected to a drain portion (not shown) of the semiconductor chip 12.

【００２１】半導体チップ１２のソース部に接続するの
上側部のフレーム基板１３にはAu等のインピーダンスが
小さい複数のボンデングワイヤ３２が接続され、これを
右部のソース基板１６に接続するようになっている。こ
のソース基板１６には直線的に延びる複数のソース電極
端子３３がドレイン電極端子３１に対向するように並列
に接続され、出力電流を出力するようになっている。A plurality of bonding wires 32 having a small impedance such as Au are connected to the upper frame substrate 13 connected to the source portion of the semiconductor chip 12, and are connected to the source substrate 16 on the right portion. Has become. A plurality of linearly extending source electrode terminals 33 are connected in parallel to the source substrate 16 so as to face the drain electrode terminals 31 and output an output current.

【００２２】半導体チップ１２にはゲートワイヤ用パッ
ド１８が備えられ、これにAu等のインピーダンスの小さ
いボンデングワイヤ３４を接続するようになっている。
このボンデングワイヤ３４には左部の直線的に延びるゲ
ート電極端子３５が接続され、半導体チップ１２に制御
電圧を加えるようになっている。The semiconductor chip 12 is provided with a gate wire pad 18, to which a bonding wire 34 having a small impedance such as Au is connected.
A left-side linearly extending gate electrode terminal 35 is connected to the bonding wire 34, and a control voltage is applied to the semiconductor chip 12.

【００２３】半導体チップ１２にはAu等のインピーダン
スの小さいボンデングワイヤ３６が接続され、これをゲ
ート電極端子３５とソース電極端子３３bとの間にシャ
ーシ等の接地部に接続するグランド端子３７を設けるよ
うになっている。このグランド端子３７によりゲート電
極端子３５の制御電圧がドレイン電極端子３１とソース
電極端子３３とを流れる出力電流に影響しないようにな
り、半導体チップ１２にノイズを発生しないようにす
る。A bonding wire 36 having a low impedance such as Au is connected to the semiconductor chip 12, and a ground terminal 37 is provided between the gate electrode terminal 35 and the source electrode terminal 33b for connecting the bonding wire 36 to a ground portion such as a chassis. It is like this. The ground terminal 37 prevents the control voltage of the gate electrode terminal 35 from affecting the output current flowing through the drain electrode terminal 31 and the source electrode terminal 33, and prevents the semiconductor chip 12 from generating noise.

【００２４】これら半導体チップ１２、フレーム基板１
３および一部のドレイン電極端子３１、ソース電極端子
３３、ゲート電極端子３５、グランド端子３７等にはフ
レーム基板１３等の裏面、ドレイン電極端子３１、ソー
ス電極端子３３、ゲート電極端子３５、グランド端子３
７の裏面を覆わないように、すなわち、露出するように
樹脂３８が被覆され、半導体チップ１２等の封止すると
ともにこれらを小型・薄型の実装外囲器（Small-Outlin
e-Packeageと言う）を構成した樹脂封止型半導体装置３
０を形成するようになっている。These semiconductor chip 12 and frame substrate 1
3 and a part of the drain electrode terminal 31, the source electrode terminal 33, the gate electrode terminal 35, the ground terminal 37, etc., the back surface of the frame substrate 13, etc., the drain electrode terminal 31, the source electrode terminal 33, the gate electrode terminal 35, the ground terminal. Three
The resin 38 is coated so as not to cover the back surface of the semiconductor chip 7, that is, to expose the semiconductor chip 12 and the like, and these are mounted in a small and thin mounting envelope (Small-Outlin
e-Packeage) resin-sealed semiconductor device 3
It is designed to form 0.

【００２５】この樹脂封止型半導体装置３０はプリント
基板１１の金属配線１１Aの上面に直接に接続して取り
付けられ、半導体チップ１２等の熱をフレーム基板１
３、ドレイン電極端子３１、ソース電極端子３３、ゲー
ト電極端子３５からプリント基板１１を介し外部に放熱
する。This resin-encapsulated semiconductor device 30 is directly connected and attached to the upper surface of the metal wiring 11A of the printed circuit board 11, and heat of the semiconductor chip 12 and the like is transferred to the frame substrate 1.
Heat is radiated from the drain electrode terminal 31, the source electrode terminal 33, and the gate electrode terminal 35 to the outside through the printed circuit board 11.

【００２６】また、この樹脂封止型半導体装置３０はソ
ース電極端子３３とゲート電極端子３５との間にグラン
ド端子３７を取り付けたからゲート電極端子３５からの
制御電圧をドレイ電極端子３１とソース電極端子３３の
間を流れる出力電流に悪影響を与えなくなり半導体チッ
プ１２に生じるノイズが小さくする。そのため、この樹
脂封止型半導体装置３０の特性を改善することができ
る。Since the resin-sealed semiconductor device 30 has the ground terminal 37 mounted between the source electrode terminal 33 and the gate electrode terminal 35, the control voltage from the gate electrode terminal 35 is applied to the drain electrode terminal 31 and the source electrode terminal 35. The output current flowing between 33 is not adversely affected and the noise generated in the semiconductor chip 12 is reduced. Therefore, the characteristics of the resin-sealed semiconductor device 30 can be improved.

【００２７】つぎに、図３、図４を用いて本発明樹脂封
止型半導体装置４０の第２の実施の形態を説明する。こ
の第２の実施の樹脂封止型半導体装置４０は第１の実施
の形態の樹脂封止型半導体装置３０とほぼ同様であるか
ら本発明樹脂封止型半導体装置３０と同一部分は同一符
号を付して第２の実施の形態の樹脂封止型半導体装置４
０を説明する。Next, a second embodiment of the resin-sealed semiconductor device 40 of the present invention will be described with reference to FIGS. Since the resin-encapsulated semiconductor device 40 of the second embodiment is substantially the same as the resin-encapsulated semiconductor device 30 of the first embodiment, the same parts as those of the resin-encapsulated semiconductor device 30 of the present invention are designated by the same reference numerals. The resin-encapsulated semiconductor device 4 according to the second embodiment
0 will be described.

【００２８】この半導体装置４０にはボンデングワイヤ
３２の代わりに半導体チップ１２とソース基板１６との
間にはCu等の金属板４１が取り付けられ、半導体チップ
１２とソース基板１６との間のインピーダンスを小さく
するようになっている。In this semiconductor device 40, a metal plate 41 such as Cu is attached between the semiconductor chip 12 and the source substrate 16 instead of the bonding wire 32, and the impedance between the semiconductor chip 12 and the source substrate 16 is increased. Is designed to be small.

【００２９】このように形成した半導体装置４０はソー
ス電極端子３３とドレイン電極端子３１との間に金属板
４１を取り付けたからソース電極端子３３とドレイン電
極端子３１との間のインピーダンスが低くなり半導体チ
ップ１２の温度を下げその特性を改善することができ
る。In the semiconductor device 40 thus formed, since the metal plate 41 is attached between the source electrode terminal 33 and the drain electrode terminal 31, the impedance between the source electrode terminal 33 and the drain electrode terminal 31 becomes low and the semiconductor chip It is possible to reduce the temperature of 12 and improve its characteristics.

【００３０】そのうえ、フレームベッド１３を含む半導
体装置４０の裏面を直接にプリント基板１１の金属配線
１１Aに取り付けたから半導体装置４０の熱がプリント
基板１１の金属配線１１aを介して外部に放出しこれを
高温にすることがない。そのため、この種の半導体装置
４０を長期に亘り安定して使用することができる。Moreover, since the back surface of the semiconductor device 40 including the frame bed 13 is directly attached to the metal wiring 11A of the printed circuit board 11, the heat of the semiconductor device 40 is radiated to the outside via the metal wiring 11a of the printed circuit board 11. It never heats up. Therefore, this type of semiconductor device 40 can be stably used for a long period of time.

【００３１】本発明ではソース電極端子３３とゲート電
極端子３５との間にグランド端子３７を設けたが、ソー
ス支持板１６の左端部を切断しソース電極１７の一部を
分離しこれをグランド端子としてもよい。In the present invention, the ground terminal 37 is provided between the source electrode terminal 33 and the gate electrode terminal 35. However, the left end portion of the source support plate 16 is cut and a part of the source electrode 17 is separated and this is ground terminal. May be

【００３２】[0032]

【発明の効果】本発明は半導体チップを搭載するフレー
ム基板と、このフレーム基板に取り付ける半導体チップ
のドレイン電極端子、ソース電極端子、ゲート電極端子
と、前記フレーム基板に取り付ける半導体チップのグラ
ンド端子と、これら半導体チップ、フレーム基板、一部
のドレイン電極端子、ソース電極端子、ゲート電極端子
およびグランド端子を封止する樹脂と、この樹脂により
封止した半導体チップ、フレーム基板、ドレイン電極端
子、ソース電極端子、ゲート電極端子およびグランド端
子を取付けるプリント基板とを備え、グランド端子はゲ
ート電極端子とソース電極端子との間に形成するように
したので、高周波動作運転時における半導体装置のノイ
ズを低減することができる。According to the present invention, a frame substrate on which a semiconductor chip is mounted, a drain electrode terminal, a source electrode terminal and a gate electrode terminal of the semiconductor chip mounted on the frame substrate, and a ground terminal of the semiconductor chip mounted on the frame substrate, Resin for sealing these semiconductor chips, frame substrate, some drain electrode terminals, source electrode terminals, gate electrode terminals and ground terminals, and semiconductor chips, frame substrates, drain electrode terminals, source electrode terminals sealed with this resin Since the ground terminal is formed between the gate electrode terminal and the source electrode terminal, the noise of the semiconductor device during high frequency operation can be reduced. it can.

【００３３】また、本発明はグランド端子はソース電極
端子を分離して形成したので、ノイズを容易に低減する
ことができる。Further, in the present invention, since the ground terminal is formed separately from the source electrode terminal, noise can be easily reduced.

【００３４】さらに、本発明は半導体チップとソース電
極端子、ゲート電極端子およびグランド端子とをAuの低
インピーダンスのボンデングワイヤあるいは金属板によ
り接続するようにしたから半導体装置のインピーダンス
を低減することができる。Further, according to the present invention, the semiconductor chip and the source electrode terminal, the gate electrode terminal and the ground terminal are connected by a low impedance bonding wire of Au or a metal plate, so that the impedance of the semiconductor device can be reduced. it can.

【００３５】さらに、本発明はフレーム基板の裏面がプ
リント基板の上面に直接に接するように樹脂を封止ある
いはフレーム基板、各電極端子の裏面がプリント基板の
上面に直接に接するように樹脂を封止したから半導体装
置の放熱を高めることができる。Further, according to the present invention, the resin is sealed so that the back surface of the frame substrate directly contacts the upper surface of the printed circuit board, or the resin is sealed so that the back surface of the frame substrate and each electrode terminal directly contacts the upper surface of the printed circuit board. Since it is stopped, heat dissipation of the semiconductor device can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明樹脂封止型半導体装置の概要を示す平面
図。FIG. 1 is a plan view showing an outline of a resin-sealed semiconductor device of the present invention.

【図２】図１の右側面図。FIG. 2 is a right side view of FIG.

【図３】本発明樹脂封止型半導体装置の他の概要を示す
平面図。FIG. 3 is a plan view showing another outline of the resin-encapsulated semiconductor device of the present invention.

【図４】図３の右側面図。FIG. 4 is a right side view of FIG.

【図５】従来の樹脂封止型半導体装置の概要を示す平面
図。FIG. 5 is a plan view showing an outline of a conventional resin-sealed semiconductor device.

【図６】図５の右側面図。6 is a right side view of FIG.

【符号の説明】[Explanation of symbols]

１０、３０、４０ 樹脂封止型半導体装置 １１ プリント基板 １２ 半導体チップ １３ フレーム基板 １４、３１ ドレイン電極端子 １５、１９、３２、３４ ボンデングワイヤ １７、３３ ソース電極端子 ２０、３５ ゲート電極端子 ２０、３８ 樹脂 ３７ グランド端子 ４１ 金属板 10, 30, 40 Resin-sealed semiconductor device 11 printed circuit boards 12 semiconductor chips 13 frame board 14, 31 Drain electrode terminal 15, 19, 32, 34 Bonding wire 17, 33 Source electrode terminal 20, 35 Gate electrode terminal 20, 38 resin 37 Ground terminal 41 metal plate

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平８−51179（ＪＰ，Ａ) 特開 昭56−115542（ＪＰ，Ａ) 特開 平７−86489（ＪＰ，Ａ) 特開 平７−193182（ＪＰ，Ａ) 特開 平７−86328（ＪＰ，Ａ) 特開 平11−176856（ＪＰ，Ａ) 実開 平１−174941（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/28,23/48 - 23/50 H01L 21/60 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-8-51179 (JP, A) JP-A-56-115542 (JP, A) JP-A-7-86489 (JP, A) JP-A-7- 193182 (JP, A) JP-A-7-86328 (JP, A) JP-A-11-176856 (JP, A) Practical example 1-174941 (JP, U) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 23 / 28,23 / 48-23/50 H01L 21/60

Claims (7)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】半導体チップを搭載するフレーム基板と、 このフレーム基板に取り付ける半導体チップのドレイン
電極端子、ソース電極端子、ゲート電極端子と、 前記フレーム基板に取り付ける半導体チップのグランド
端子と、 これら半導体チップ、フレーム基板、一部のドレイン電
極端子、ソース電極端子、ゲート電極端子およびグラン
ド端子を封止する樹脂と、 この樹脂により封止した半導体チップ、フレーム基板、
ドレイン電極端子、ソース電極端子、ゲート電極端子お
よびグランド端子を取付けるプリント基板と、を備え 前記グランド端子はゲート電極端子とソース電極端子と
の間に形成するものであることを特徴とする樹脂封止型
半導体装置。1. A frame substrate on which a semiconductor chip is mounted, a drain electrode terminal, a source electrode terminal, and a gate electrode terminal of the semiconductor chip attached to the frame substrate, a ground terminal of the semiconductor chip attached to the frame substrate, and these semiconductor chips. A resin for sealing the frame substrate, a part of the drain electrode terminal, the source electrode terminal, the gate electrode terminal and the ground terminal, and a semiconductor chip sealed by the resin, the frame substrate,
A printed circuit board on which a drain electrode terminal, a source electrode terminal, a gate electrode terminal and a ground terminal are mounted, and the ground terminal is formed between the gate electrode terminal and the source electrode terminal. Type semiconductor device. 【請求項２】前記グランド端子はソース電極端子を分離
して形成するものであることを特徴とする請求項１に記
載の樹脂封止型半導体装置。2. The resin-encapsulated semiconductor device according to claim 1, wherein the ground terminal is formed separately from the source electrode terminal. 【請求項３】半導体チップとソース電極端子、ゲート電
極端子およびグランド端子とを低インピーダンスの金ボ
ンデングワイヤにより接続したことを特徴とする請求項
１に記載の樹脂封止型半導体装置。3. The resin-sealed semiconductor device according to claim 1, wherein the semiconductor chip and the source electrode terminal, the gate electrode terminal and the ground terminal are connected by a low impedance gold bonding wire. 【請求項４】半導体チップと少なくともソース電極端子
とを金属板により接続するようにしたことを特徴とする
請求項１に記載の樹脂封止型半導体装置。4. The resin-sealed semiconductor device according to claim 1, wherein the semiconductor chip and at least the source electrode terminal are connected by a metal plate. 【請求項５】前記金属板は銅板であることを特徴とする
請求項４に記載の樹脂封止型半導体装置。5. The resin-sealed semiconductor device according to claim 4, wherein the metal plate is a copper plate. 【請求項６】フレーム基板の裏面がプリント基板の上面
に直接に接するように樹脂を封止したことを特徴とする
請求項１ないし５のいずれかに記載の樹脂封止型半導体
装置。6. The resin-encapsulated semiconductor device according to claim 1, wherein the resin is encapsulated so that the back surface of the frame substrate is in direct contact with the upper surface of the printed circuit board. 【請求項７】フレーム基板、各電極端子の裏面がプリン
ト基板の上面に直接に接するように樹脂を封止したこと
を特徴とする請求項１ないし６のいずれかに記載の樹脂
封止型半導体装置。7. The resin-encapsulated semiconductor according to claim 1, wherein the resin is encapsulated so that the back surfaces of the frame substrate and the respective electrode terminals are in direct contact with the upper surface of the printed circuit board. apparatus.
JP2000188191A 2000-06-22 2000-06-22 Resin-sealed semiconductor device Expired - Fee Related JP3450803B2 (en)

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JP4115882B2 (en) * 2003-05-14 2008-07-09 株式会社ルネサステクノロジ Semiconductor device
JP4246598B2 (en) * 2003-10-22 2009-04-02 三菱電機株式会社 Power semiconductor device
JP4515218B2 (en) * 2004-10-22 2010-07-28 ソニー株式会社 Memory card
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