JP2004054935A - マスク可能な内容照合メモリにおけるビットエラーの検出方法および装置 - Google Patents

マスク可能な内容照合メモリにおけるビットエラーの検出方法および装置 Download PDF

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JP2004054935A
JP2004054935A JP2003183660A JP2003183660A JP2004054935A JP 2004054935 A JP2004054935 A JP 2004054935A JP 2003183660 A JP2003183660 A JP 2003183660A JP 2003183660 A JP2003183660 A JP 2003183660A JP 2004054935 A JP2004054935 A JP 2004054935A
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Japan
Prior art keywords
parity
cam
ram
mask
data
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Pending
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JP2003183660A
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English (en)
Japanese (ja)
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JP2004054935A5 (enExample
Inventor
Benjamin J Patella
ベンジャミン・ジェイ・パテラ
Lee Arnold Ronney
ロニー・リー・アーノルド
Cameron B Mcnairy
キャメロン・ビー・マクネアリー
Kevin David Safford
ケヴィン・デイヴィッド・サフォード
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HP Inc
Intel Corp
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Intel Corp
Hewlett Packard Co
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Application filed by Intel Corp, Hewlett Packard Co filed Critical Intel Corp
Publication of JP2004054935A publication Critical patent/JP2004054935A/ja
Publication of JP2004054935A5 publication Critical patent/JP2004054935A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1064—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in cache or content addressable memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
JP2003183660A 2002-07-16 2003-06-27 マスク可能な内容照合メモリにおけるビットエラーの検出方法および装置 Pending JP2004054935A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/196,763 US7100097B2 (en) 2002-07-16 2002-07-16 Detection of bit errors in maskable content addressable memories

Publications (2)

Publication Number Publication Date
JP2004054935A true JP2004054935A (ja) 2004-02-19
JP2004054935A5 JP2004054935A5 (enExample) 2006-08-03

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JP2003183660A Pending JP2004054935A (ja) 2002-07-16 2003-06-27 マスク可能な内容照合メモリにおけるビットエラーの検出方法および装置

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US (1) US7100097B2 (enExample)
JP (1) JP2004054935A (enExample)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7260673B1 (en) 2001-07-20 2007-08-21 Cisco Technology, Inc. Method and apparatus for verifying the integrity of a content-addressable memory result
CN100421106C (zh) * 2002-08-10 2008-09-24 思科技术公司 具有增强能力的关联存储器
US7065609B2 (en) * 2002-08-10 2006-06-20 Cisco Technology, Inc. Performing lookup operations using associative memories optionally including selectively determining which associative memory blocks to use in identifying a result and possibly propagating error indications
US7441074B1 (en) 2002-08-10 2008-10-21 Cisco Technology, Inc. Methods and apparatus for distributing entries among lookup units and selectively enabling less than all of the lookup units when performing a lookup operation
US7152140B2 (en) * 2003-06-18 2006-12-19 Intel Corporation Masking parity information associated with a ternary content addressable memory
US7080195B2 (en) * 2003-10-22 2006-07-18 Cisco Technology, Inc. Merging indications of matching items of multiple groups and possibly associated with skip conditions to identify winning entries of particular use for implementing access control lists
US7305519B1 (en) 2004-03-29 2007-12-04 Cisco Technology, Inc. Error protection for associative memory entries and lookup operations performed thereon
US7290083B2 (en) * 2004-06-29 2007-10-30 Cisco Technology, Inc. Error protection for lookup operations in content-addressable memory entries
DE102004041657A1 (de) * 2004-08-27 2006-03-09 Infineon Technologies Ag Schaltungsanordnung und Verfahren zum Betrieb einer solchen
US7350131B2 (en) * 2005-01-22 2008-03-25 Cisco Technology, Inc. Error protecting groups of data words
US7409524B2 (en) * 2005-08-17 2008-08-05 Hewlett-Packard Development Company, L.P. System and method for responding to TLB misses
US7757152B2 (en) * 2005-08-18 2010-07-13 Hewlett-Packard Development Company, L.P. Data corruption scrubbing for content addressable memory and ternary content addressable memory
US7761774B2 (en) * 2005-10-28 2010-07-20 Qualcomm Incorporated High speed CAM lookup using stored encoded key
US7802156B2 (en) * 2006-05-31 2010-09-21 Lsi Corporation Identification circuit with repeatable output code
US7689889B2 (en) * 2006-08-24 2010-03-30 Cisco Technology, Inc. Content addressable memory entry coding for error detection and correction
KR100855979B1 (ko) 2007-02-13 2008-09-02 삼성전자주식회사 바이트 마스킹 동작을 위한 반도체 메모리 장치 및 패리티데이터 생성 방법
TWI382423B (zh) * 2008-04-18 2013-01-11 Realtek Semiconductor Corp 記憶裝置及其測試方法
US8199547B2 (en) * 2010-02-10 2012-06-12 Freescale Semiconductor, Inc. Error detection in a content addressable memory (CAM)
US8533578B2 (en) 2010-06-11 2013-09-10 Freescale Semiconductor, Inc. Error detection in a content addressable memory (CAM) and method of operation
CN103729260B (zh) * 2012-10-12 2017-07-21 联发科技股份有限公司 数据管理/检查方法及相关内容寻址存储器系统
US9311181B2 (en) 2012-11-15 2016-04-12 Samsung Electronics Co., Ltd. Memory controller changing partial data in memory device and method for changing partial data thereof
CN104182292A (zh) * 2013-05-21 2014-12-03 华为技术有限公司 一种数据存储方法及装置
US9678828B2 (en) * 2013-10-09 2017-06-13 QUAULCOMM Incorporated Error detection capability over CCIe protocol
US9690725B2 (en) 2014-01-14 2017-06-27 Qualcomm Incorporated Camera control interface extension with in-band interrupt
US10353837B2 (en) 2013-09-09 2019-07-16 Qualcomm Incorporated Method and apparatus to enable multiple masters to operate in a single master bus architecture
US9996488B2 (en) 2013-09-09 2018-06-12 Qualcomm Incorporated I3C high data rate (HDR) always-on image sensor 8-bit operation indicator and buffer over threshold indicator
US9684624B2 (en) 2014-01-14 2017-06-20 Qualcomm Incorporated Receive clock calibration for a serial bus
US10176040B2 (en) 2016-04-05 2019-01-08 Micron Technology, Inc. Error correction code (ECC) operations in memory
US10312567B2 (en) 2016-10-26 2019-06-04 At&T Intellectual Property I, L.P. Launcher with planar strip antenna and methods for use therewith
US10042702B2 (en) * 2016-11-07 2018-08-07 SK Hynix Inc. Memory device transferring data between master and slave device and semiconductor package including the same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4065756A (en) * 1976-03-15 1977-12-27 Burroughs Corporation Associative memory with neighboring recirculated paths offset by one bit
US4996666A (en) * 1988-08-12 1991-02-26 Duluk Jr Jerome F Content-addressable memory system capable of fully parallel magnitude comparisons
US5453999A (en) * 1994-04-26 1995-09-26 Unisys Corporation Address verification system using parity for transmitting and receiving circuits
US6067656A (en) * 1997-12-05 2000-05-23 Intel Corporation Method and apparatus for detecting soft errors in content addressable memory arrays
US6430073B1 (en) * 2000-12-06 2002-08-06 International Business Machines Corporation Dram CAM cell with hidden refresh
US6718494B1 (en) * 2000-12-22 2004-04-06 Intel Corporation Method and apparatus for preventing and recovering from TLB corruption by soft error
US6700827B2 (en) * 2001-02-08 2004-03-02 Integrated Device Technology, Inc. Cam circuit with error correction
JP3860436B2 (ja) * 2001-07-09 2006-12-20 富士通株式会社 半導体記憶装置
US6657878B2 (en) * 2002-02-27 2003-12-02 Integrated Device Technology, Inc. Content addressable memory (CAM) devices having reliable column redundancy characteristics and methods of operating same

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US20040015752A1 (en) 2004-01-22
US7100097B2 (en) 2006-08-29

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