JP2004031813A - Multilayer wiring board and its manufacturing method - Google Patents

Multilayer wiring board and its manufacturing method Download PDF

Info

Publication number
JP2004031813A
JP2004031813A JP2002188454A JP2002188454A JP2004031813A JP 2004031813 A JP2004031813 A JP 2004031813A JP 2002188454 A JP2002188454 A JP 2002188454A JP 2002188454 A JP2002188454 A JP 2002188454A JP 2004031813 A JP2004031813 A JP 2004031813A
Authority
JP
Japan
Prior art keywords
conductor layer
wiring conductor
layer
wiring
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002188454A
Other languages
Japanese (ja)
Other versions
JP4022105B2 (en
Inventor
Genshitarou Kawamura
川村 原子太郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2002188454A priority Critical patent/JP4022105B2/en
Publication of JP2004031813A publication Critical patent/JP2004031813A/en
Application granted granted Critical
Publication of JP4022105B2 publication Critical patent/JP4022105B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a deterioration in insulation between wiring conductor layers in a multilayer wiring board wherein the wiring conductor layers are formed on a surface of a substrate and resin insulation layers are so formed as to cover the wiring conductor layers. <P>SOLUTION: The multilayer wiring board is such that the wiring conductor layers 2 are formed on the surface of the substrate 1 and the resin insulation layers 3 are so formed as to cover the wiring conductor layers 2. In the multilayer wiring board, a wiring conductor non-formation region 4 on the surface of the substrate 1 is recessed with respect to a region immediately beneath the wiring conductor layers 2. Due to this structure, passway between the wiring conductor layers 2 becomes longer, preventing a deterioration in insulation between the wiring conductor layers 2 and realizing a multilayer wiring board with a superior environment resistant reliability. <P>COPYRIGHT: (C)2004,JPO

Description

【0001】
【発明の属する技術分野】
本発明は混成集積回路や半導体素子を収納する半導体素子収納用パッケージ等に使用される多層配線基板およびその製造方法に関するものである。
【0002】
【従来の技術】
近年、電子機器の小型化・多機能化に伴い、これに使用される半導体集積回路素子等の半導体デバイスは高集積化するとともに入出力端子数が増加している。こうした半導体デバイスが搭載される配線基板やそのデバイスを試験するために使用される配線基板に対しては、回路の高集積化の要求は当然のことながら、熱膨張率のミスマッチにより発生する入出力端子部のストレスや、試験時にプローブにより配線基板に負荷されるコンタクト圧力等、配線基板に加わるストレスが半導体デバイスの入出力端子数の増加に伴って増加しており、そのストレスが配線基板におけるクラックの発生や変形の原因となるため、半導体デバイスの入出力端子や試験用のプローブ等を支持するための支持体として十分な強度を有するよう、高強度化の要求がなされている。このため、きわめて細線な配線パターンを有する高強度な多層配線基板が求められている。
【0003】
このような多層配線基板に対する高集積化・高強度化の要求から、多層プリント配線基板やビルドアップ方式の多層配線基板に代わり、セラミックスから成る基板上に薄膜の絶縁層と配線導体層とから成る薄膜多層配線部を形成したセラミック薄膜混成多層配線基板が注目されている。
【0004】
かかるセラミック薄膜混成多層配線基板は、モリブデンやタングステン等から成るメタライズ配線層と酸化アルミニウム質焼結体等のセラミック絶縁層とから成るセラミック多層配線基板の上面に、銅やアルミニウム等の金属から成り、めっき法や蒸着法等の薄膜形成技術およびフォトリソグラフィー技術を採用することによって形成される配線導体層と、スピンコート法および熱硬化処理等によって形成されるポリイミド樹脂等から成る薄膜の樹脂絶縁層とを交互に多層に積層させた薄膜多層配線部を有しており、高強度な支持体としての機能を持つとともにきわめて微細な配線パターンにより回路の高集積化に優れた多層配線基板として期待されている。
【0005】
このような薄膜多層配線部について、スピンコート法および熱硬化処理等によってポリイミド樹脂等から成る樹脂絶縁層を形成する場合においては、所望の厚みに樹脂絶縁層を形成するには多数回に分けてポリイミド樹脂の前駆体を塗布し、その後にポリイミド樹脂の前駆体をポリイミド化させるキュア工程を経て樹脂絶縁層が形成される。
【0006】
しかしながら、かかる樹脂絶縁層の形成法は製造工程が長くなるという問題点があるため、この形成法に代えて、ポリイミド樹脂等から成る複数の絶縁フィルム層を間にビスマレイミドトリアジン樹脂等から成る絶縁性接着剤層を介して積層して成る樹脂絶縁層の形成法が採用されてきている。
【0007】
【発明が解決しようとする課題】
しかしながら、このようなセラミック薄膜混成多層配線基板では、配線導体層と基板の表面とが、化学結合による接合と、配線導体層が基板の表面の凹凸に食い込むことによって生じるアンカー効果による接合とにより強固に接合されているため、基板の表面のうち配線導体層の非形成領域に余分に形成された導体層をエッチング等により除去した際に、その配線導体層の非形成領域に導体層成分の残さが生じやすく、そのままの状態で配線導体層およびその非形成領域の上に樹脂絶縁層を形成して積層すると、配線導体間の絶縁性が低下しやすいという問題点があった。
【0008】
本発明は以上のような従来の技術における問題点に鑑みてなされたものであり、その目的は、基板の表面に形成された配線導体層間の絶縁性の低下を簡易な方法で有効に防止した、耐環境信頼性の優れた多層配線基板を提供することにある。
【0009】
また、本発明の他の目的は、基板の表面に形成された配線導体層間の絶縁性の低下を簡易な方法で有効に防止した、耐環境信頼性の優れた多層配線基板を得ることができる多層配線基板の製造方法を提供することにある。
【0010】
【課題を解決するための手段】
本発明の多層配線基板は、基板の表面に、配線導体層が形成されるとともに、この配線導体層を覆って樹脂絶縁層が形成された多層配線基板において、前記基板の表面のうち前記配線導体層の非形成領域が、前記配線導体層の直下の領域に対して凹んでいることを特徴とするものである。
【0011】
また、本発明の多層配線基板は、上記構成において、前記非形成領域が、前記配線導体層の直下の領域に対して0.1乃至10μmの深さで凹んでいることを特徴とするものである。
【0012】
本発明の第1の多層配線基板の製造方法は、基板の表面に下地導体層を形成する工程と、この下地導体層上に配線導体層のパターンの開口を有するレジスト層を形成する工程と、前記開口から露出した前記下地導体層上に主導体層を形成する工程と、前記レジスト層を除去する工程と、前記主導体層から露出した前記下地導体層を除去して配線導体層を形成するとともに、前記基板の表面のうち前記配線導体層の非形成領域を一部除去して前記配線導体層の直下の領域に対して凹ませる工程と、しかる後、前記基板の表面に前記配線導体層を覆って樹脂絶縁層を形成する工程とを具備することを特徴とするものである。
【0013】
また、本発明の第2の多層配線基板の製造方法は、基板の表面に下地導体層を形成する工程と、この下地導体層上に主導体層を形成する工程と、この主導体層上に配線導体層のパターンのレジスト層を形成する工程と、このレジスト層から露出した前記主導体層および前記下地導体層を除去して配線導体層を形成するとともに、前記基板の表面のうち前記配線導体層の非形成領域を一部除去して前記配線導体層の直下の領域に対して凹ませる工程と、前記レジスト層を除去する工程と、しかる後、前記基板の表面に前記配線導体層を覆って樹脂絶縁層を形成する工程とを具備することを特徴とするものである。
【0014】
本発明の多層配線基板によれば、基板の表面のうち配線導体層の非形成領域を配線導体層の直下の領域に対して凹ませてあるため、隣接する配線導体層間の経路が長くなることにより、配線導体層間の絶縁性が低下することがなくなり、耐環境信頼性の優れた多層配線基板を実現することができる。
【0015】
また、本発明の多層配線基板によれば、配線導体層の非形成領域が、配線導体層の直下の領域に対して0.1乃至10μmの深さで凹んでいるときには、隣接する配線導体層間の経路を必要な長さに長くできることにより配線導体層間の絶縁性が低下することがなくなるとともに、基板の表面に配線導体層を覆って配線導体層の非形成領域にかけて樹脂絶縁層を形成した際の樹脂絶縁層の平坦性を良好なものとすることができ、耐環境信頼性の優れた、かつこの多層配線基板に搭載される半導体デバイスの入出力端子等との接続信頼性にも優れた多層配線基板を実現することができる。
【0016】
本発明の第1の多層配線基板の製造方法によれば、基板の表面に下地導体層を形成する工程と、この下地導体層上に配線導体層のパターンの開口を有するレジスト層を形成する工程と、レジスト層の開口から露出した下地導体層上に主導体層を形成する工程と、レジスト層を除去する工程と、主導体層から露出した下地導体層を除去して開口のパターンに対応した形状の配線導体層を形成するとともに、前記基板の表面のうち配線導体層の非形成領域を一部除去してこの配線導体層の非形成領域を配線導体層の直下の領域に対して凹ませる工程と、しかる後、配線導体層を覆って配線導体層の非形成領域の上にかけて樹脂絶縁層を形成する工程とを具備することから、基板の表面のうち配線導体層の非形成領域を表面側から一部除去することによって、その配線導体層の非形成領域の基板の表面に発生した配線導体層成分の残さが確実に除去されるとともに、配線導体層の直下の領域に対して配線導体層の非形成領域に凹みが形成されて隣接する配線導体層間の経路が長くなることにより、配線導体層間の絶縁性が低下することがなくなり、耐環境信頼性の優れた多層配線基板を簡易な方法で実現することができる多層配線基板の製造方法を提供できる。
【0017】
本発明の第2の多層配線基板の製造方法によれば、基板の表面に下地導体層を形成する工程と、この下地導体層上に主導体層を形成する工程と、この主導体層上に配線導体層のパターンのレジスト層を形成する工程と、このレジスト層から露出した主導体層および下地導体層を除去して配線導体層を形成するとともに、基板の表面のうち配線導体層の非形成領域を一部除去してこの配線導体層の非形成領域を配線導体層の直下の領域に対して凹ませる工程と、レジスト層を除去する工程と、しかる後、基板の表面に配線導体層を覆って樹脂絶縁層を形成する工程とを具備することから、第1の製造方法と同様に、基板の表面のうち配線導体層の非形成領域を表面側から一部除去することによって、その配線導体層の非形成領域の基板の表面に発生した配線導体層成分の残さが確実に除去されるとともに、配線導体層の直下の領域に対して配線導体層の非形成領域に凹みが形成されて隣接する配線導体層間の経路が長くなることにより、配線導体層間の絶縁性が低下することがなくなり、さらに、隣接する配線導体層間の絶縁性の低下を防止する配線導体層の非形成領域の凹みを第1の製造方法よりも少ない工数で形成できる、耐環境信頼性の優れた多層配線基板の製造方法を提供できる。
【0018】
【発明の実施の形態】
以下、図面に基づいて本発明を詳細に説明する。
【0019】
図1は本発明の多層配線基板の実施の形態の一例を示す断面図であり、図2はその多層配線基板における配線導体層の非形成領域の凹みを示す要部拡大断面図である。
【0020】
これらの図において、1は基板、2は配線導体層、3は樹脂絶縁層、4は配線導体層の非形成領域、5は凹み、6は配線導体層2の一部としての下地導体層、7は配線導体層2の一部としての主導体層、8は樹脂絶縁層3の一部としての絶縁性接着剤層、9は樹脂絶縁層3の一部としての絶縁フィルム層、10は多層配線部、11は貫通孔、12は貫通導体である。
【0021】
基板1は、その表面、この例では上面に配線導体層2と樹脂絶縁層3とを交互に多層に積層した多層配線部10が配設されており、この多層配線部10を支持する支持部材として機能する。
【0022】
基板1は、例えば、酸化アルミニウム質焼結体,ムライト質焼結体,ガラスセラミックス等の酸化物系セラミックス、あるいは表面に酸化物膜を有する窒化アルミニウム質焼結体,炭化珪素質焼結体等の非酸化物系セラミックス、あるいはガラスセラミックス等の電気絶縁材料で形成されている。また、エポキシ樹脂やビスマレイミドトリアジン樹脂,熱硬化性ポリフェニレンエーテル樹脂,フェノール樹脂等の熱硬化性樹脂や、ポリイミド樹脂,フッ素樹脂,ポリフェニレンエーテル樹脂,液晶ポリマー樹脂,アラミド樹脂,ポリエチレンテレフタレート等の熱可塑性樹脂等の各種の有機絶縁性樹脂材料や、有機絶縁性樹脂でセラミックス等の無機絶縁体粉末を結合して成る複合材料や、ガラス,石英,サファイア等の電気絶縁材料で形成してもよい。
【0023】
例えば、酸化アルミニウム質焼結体で形成されている場合には、アルミナ,シリカ,カルシア,マグネシア等の原料粉末に適当な有機溶剤,溶媒を添加混合して泥漿状となすとともに、これより従来周知のドクターブレード法やカレンダーロール法を採用することによってセラミックグリーンシート(セラミック生シート)を形成し、しかる後、このセラミックグリーンシートに適当な打ち抜き加工を施し所定形状となすとともに、必要に応じて配線導体と成る導体パターンを印刷形成し所定枚数を積層した後、高温(約1600℃)で焼成することによって製作される。あるいは、アルミナ等の原料粉末に適当な有機溶剤,溶媒を添加混合して原料粉末を調製するとともに、この原料粉末をプレス成形機によって所定形状に成形し、最後にこの成形体を高温(約1600℃)で焼成することによって製作される。
【0024】
また、基板1がガラスセラミックスで形成されている場合には、ガラスと無機質フィラー(無機絶縁体粉末)との混合物に有機バインダ,可塑剤,溶剤等を加えてスラリーとし、ドクターブレード法等によりガラスセラミックグリーンシートを成形した後、Cu,Ag,Au等の低抵抗金属の粉末を含有する導体ペーストをこのガラスセラミックグリーンシート上に印刷することにより導体パターンを形成し、その後、導体パターンを形成した複数枚のガラスセラミックグリーンシートを積層して800〜1000℃の温度で焼成することによって製作される。
【0025】
ガラスセラミックグリーンシートは、ガラス粉末,無機質フィラー(セラミック粉末),さらに有機バインダ,可塑剤,有機溶剤等を混合したものが用いられる。
【0026】
ガラス成分としては、例えばSiO−B系,SiO−B−Al系,SiO−B−Al−MO系(但し、MはCa,Sr,Mg,BaまたはZnを示す),SiO−Al−MO−MO系(但し、MおよびMは同一または異なってCa,Sr,Mg,BaまたはZnを示す),SiO−B−Al−MO−MO系(但し、MおよびMは前記と同じである),SiO−B−M O系(但し、MはLi,NaまたはKを示す),SiO−B−Al−M O系(但し、Mは前記と同じである),Pb系ガラス,Bi系ガラス等が挙げられる。
【0027】
また、無機質フィラーとしては、例えばAl,SiO,ZrOとアルカリ土類金属酸化物との複合酸化物,TiOとアルカリ土類金属酸化物との複合酸化物,AlおよびSiOから選ばれる少なくとも1種を含む複合酸化物(例えばスピネル,ムライト,コージェライト)等が挙げられる。
【0028】
本発明の多層配線基板においては、基板1の表面に、配線導体層2が形成されるとともに、この配線導体層2を覆って樹脂絶縁層3が形成された多層配線基板において、基板1の表面のうち配線導体層の非形成領域4が、配線導体層2の直下の領域の基板1の表面に対して凹んでいることが重要である。
【0029】
これにより、隣接する配線導体層2間の基板1の表面を経由する経路が長くなることにより、配線導体層2間の絶縁性が低下することがなくなり、耐環境信頼性の優れた多層配線基板を実現できるためである。
【0030】
これに対し、基板1の表面のうち配線導体層の非形成領域4が、配線導体層2の直下の領域の基板1の表面に対して凹んでいない場合には、隣接する配線導体層2間の経路が最短距離となって短くなることから、配線導体層2間の絶縁性が低下しやすくなる傾向がある。
【0031】
多層配線部10において、基板1の表面に形成される配線導体層2は、例えば以下のように形成すればよい。
【0032】
基板1の表面に、その表面との接合の役目を果たすTi,CrあるいはMo等の活性金属と主導体層7としてのCuとを含む下地導体層6を真空成膜法または電解もしくは無電解めっき法により形成し、次いで、下地導体層6の上に配線導体層2のパターンの開口を有するレジスト層を形成し、このレジスト層の開口から露出した下地導体層6上に真空成膜法または電解もしくは無電解めっき法によって、例えば電解Cuめっきにより主導体層7を所望の厚みまで形成する。その後、剥離液等を用いてレジスト層を除去し、主導体層7からはみ出して露出した下地導体層6をエッチングやブラスト,研磨等により除去してレジスト層の開口のパターンに対応した形状の配線導体層2を形成するとともに、基板1の表面のうち配線導体層の非形成領域4を同じくエッチングやブラスト,研磨等により表面側から一部除去して凹み5を形成する。これにより、配線導体層の非形成領域4に発生した配線導体層2の残さ、より具体的には下地導体層6の残さを基板1の表面から確実に除去できるとともに、配線導体層の非形成領域4に凹みが形成されて隣接する配線導体層2間の基板1の表面を経由する経路が長くなることにより、配線導体層2間の絶縁性が低下することがなく、所望のパターンを有する高密度に配設された配線導体層2を形成することができる。
【0033】
このとき、基板1としてガラスセラミックスを採用すると、誘電率が低いガラスセラミックスで絶縁層を構成できるとともに、Cu等の低抵抗金属で配線導体層2を構成できるため高周波特性が良好となり、電気特性に優れた支持体として機能するものとできるため好都合なものとなる。特に、比誘電率を7以下とすると、優れた高周波特性が得られ、より好都合である。
【0034】
また、配線導体層の非形成領域4の凹み5の配線導体層2の直下の領域に対する深さを0.1μm乃至10μmとすると、この基板1の表面に配線導体層2を覆って配線導体層の非形成領域4にかけて樹脂絶縁層3を形成した際に樹脂絶縁層3の表面の平坦性を損なうことなく配線導体層の非形成領域4に発生した配線導体層2の残さを除去でき、また隣接する配線導体層2間の配線導体層の非形成領域4を経由する経路を必要な長さに長くすることができるため配線導体層2間の絶縁性の低下を防止できるものとするのに効果的である。
【0035】
凹み5の深さが0.1μmを下回ると配線導体層の非形成領域4に発生した配線導体層2成分の残さの除去効果が薄れる傾向にあり、また10μmを超えるとその上に形成される樹脂絶縁層3の表面の平坦性が低化する傾向にある。なお、この場合の凹み5の深さは、基板1の表面を表面側から一部除去する際に、例えばフッ酸と硝酸との混合水溶液をエッチング液として用いることにより容易に制御できる。
【0036】
また、本発明の第2の多層配線基板の製造方法における凹み5の形成法としては、基板1の表面に、その表面との接合の役目を果たすTi,CrあるいはMo等の活性金属と主導体層7としてのCuとを含む下地導体層6と、主導体層7としてのCu層とを、真空成膜法により形成する。または、基板1の表面を燐酸やフッ酸を含むエッチング液により粗化した後、Pdを含む活性液で表面処理を行ない、無電解Cuめっきにより下地導体層6を形成して、次いで、電解Cuめっきにて主導体層7を形成する。次に、主導体層7の上面に配線導体層2のパターンのレジスト層を形成し、このレジスト層からはみ出して露出した主導体層7および下地導体層6をエッチング等の方法により除去してレジスト層のパターンの形状に配線導体層2を形成するとともに、基板1の表面のうち配線導体層の非形成領域4を例えば燐酸やフッ酸を含むエッチング液によりエッチングする等の方法によって表面側から一部除去して、配線導体層の非形成領域4を配線導体層2の直下の領域の基板1の表面に対して凹ませると、配線導体層の非形成領域4に発生した配線導体層2、主として下地導体層6の成分の残さを基板1の表面の一部とともに確実に除去でき、所望のパターンを有し配線導体層2間の絶縁性の低下を防止できる高密度配線が可能な配線導体層2を少ない工数で形成することができる。
【0037】
多層配線部10の樹脂絶縁層3は絶縁フィルム層9と絶縁性接着剤層8とから構成され、絶縁フィルム層9はポリイミド樹脂,ポリフェニレンサルファイド樹脂,全芳香族ポリエステル樹脂,フッ素樹脂等から成る。また、絶縁性接着剤層8はポリアミドイミド樹脂,ポリイミドシロキサン樹脂,ビスマレイミドトリアジン樹脂,エポキシ樹脂等から成る。
【0038】
樹脂絶縁層3は、まず厚みが12.5〜50μm程度の絶縁フィルムに絶縁性接着剤をドクターブレード法等を用いて乾燥厚みで5〜20μm程度に塗布し乾燥させたものを準備し、この絶縁フィルム層9を基板1や下層の樹脂絶縁層3の上面に間に絶縁性接着剤層8が配されるように積み重ね、これを加熱プレス装置を用いて加熱加圧し接着することによって形成される。
【0039】
樹脂絶縁層3には所定位置に絶縁フィルム層9および絶縁性接着剤層8を貫通する貫通孔11が形成されており、この貫通孔11内に貫通導体12が被着形成されることにより、樹脂絶縁層3を挟んで上下に位置する配線導体層2の各々を電気的に接続する接続路が形成される。
【0040】
貫通孔11は、例えばレーザを使い絶縁フィルム層9および絶縁性接着剤層8の一部を除去することにより形成される。特に、貫通孔11の開口径が小さな場合は、貫通孔11の内壁面の角度をコントロールすることが容易で貫通孔11の内壁面が滑らかに加工される紫外線レーザで形成することが望ましい。
【0041】
貫通導体12は各樹脂絶縁層3の上面に配設される配線導体層2と別々に形成してもよいが、これらは同時に形成した方が工程数を少なくできるとともに両者の電気的な接続信頼性の点でも良好である。
【0042】
また、各樹脂絶縁層3の上面に配設される配線導体層2と貫通導体11とを一体形成する場合には、それぞれに所望の厚みのめっき膜を調整して形成することができるように、主として電解めっき法を用いて形成しておくのがよい。
【0043】
各樹脂絶縁層3の上面に配設される配線導体層2および貫通導体11の形成方法は、例えば以下のようにすればよい。まず、樹脂絶縁層3との接合の役目を果たすTi,Cr,Mo等の活性金属と主導体としてのCuとを含む下地導体層6を真空成膜法またはめっき法により形成し、次いで、下地導体層6の上に配線導体層2のパターンの開口を有するレジスト層を形成し、レジスト層の開口から露出した下地導体層6上に例えば電解Cuめっきにより主導体層7を所望の厚みまで形成する。その後、剥離液を用いること等によってレジスト層を除去し、主導体層7からはみ出して露出した下地導体層6をエッチング等により除去してレジスト層の開口のパターンに対応した形状の配線導体層2を形成する。
【0044】
なお、多層配線部10の表面となる樹脂絶縁層3の最上層の表面に形成された配線導体層2には、搭載される半導体デバイスやチップ部品等の実装性および耐環境性の点から、主導体層7がCu層から成る場合にはその上にNi層やAu層を形成しておくとよい。
【0045】
かくして、本発明の多層配線基板によれば、基板1の表面に配設された多層配線部10の上に半導体素子を始めとする半導体デバイスや容量素子,抵抗器といったチップ部品等の電子部品を搭載実装し、それら半導体デバイスや電子部品の各電極を配線導体層2に電気的に接続することによって、半導体装置や混成集積回路装置等となる。
【0046】
なお、本発明は上記の実施の形態の例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能である。
【0047】
例えば、上述の実施の形態の例では、配線導体層の非形成領域4の凹み5の深さを、エッチング液を用いて制御する方法を示したが、ガスを用いて制御する方法、例えば反応性イオンエッチング等を用いてもよく、サンドブラストやウェットブラスト、あるいは研磨や擦り取り等の機械的な除去手段によってその除去量を制御する方法等を用いてもよい。
【0048】
また、本発明の多層配線基板は、混成集積回路装置等を構成するモジュール基板等に適用できることはもとより、半導体素子を収容する半導体素子収納用パッケージに適用してもよいものである。
【0049】
【発明の効果】
以上のように、本発明の多層配線基板によれば、基板の表面のうち配線導体層の非形成領域を配線導体層の直下の領域に対して凹ませてあるため、隣接する配線導体層間の経路が長くなることにより、配線導体層間の絶縁性の低下を招くことがなくなり、耐環境信頼性の優れた多層配線基板を実現することができた。
【0050】
また、本発明の多層配線基板によれば、配線導体層の非形成領域が、配線導体層の直下の領域に対して0.1乃至10μmの深さで凹んでいるときには、隣接する配線導体層間の経路を必要な長さに長くできることにより配線導体層間の絶縁性が低下することがなくなるとともに、基板の表面に配線導体層を覆って配線導体層の非形成領域にかけて樹脂絶縁層を形成した際の樹脂絶縁層の平坦性を良好なものとすることができ、耐環境信頼性の優れた、かつこの多層配線基板に搭載される半導体デバイスの入出力端子等との接続信頼性にも優れた多層配線基板を実現することができた。
【0051】
本発明の第1の多層配線基板の製造方法によれば、基板の表面に下地導体層を形成する工程と、この下地導体層上に配線導体層のパターンの開口を有するレジスト層を形成する工程と、レジスト層の開口から露出した下地導体層上に主導体層を形成する工程と、レジスト層を除去する工程と、主導体層から露出した下地導体層を除去して開口のパターンに対応した形状の配線導体層を形成するとともに、前記基板の表面のうち配線導体層の非形成領域を一部除去してこの配線導体層の非形成領域を配線導体層の直下の領域に対して凹ませる工程と、しかる後、配線導体層を覆って配線導体層の非形成領域の上にかけて樹脂絶縁層を形成する工程とを具備することから、基板の表面のうち配線導体層の非形成領域を表面側から一部除去することによって、その配線導体層の非形成領域の基板の表面に発生した配線導体層成分の残さが確実に除去されるとともに、配線導体層の直下の領域に対して配線導体層の非形成領域に凹みが形成されて隣接する配線導体層間の経路が長くなることにより、配線導体層間の絶縁性が低下することがなくなり、耐環境信頼性の優れた多層配線基板を簡易な方法で実現することができる多層配線基板の製造方法を提供できた。
【0052】
本発明の第2の多層配線基板の製造方法によれば、基板の表面に下地導体層を形成する工程と、この下地導体層上に主導体層を形成する工程と、この主導体層上に配線導体層のパターンのレジスト層を形成する工程と、このレジスト層から露出した主導体層および下地導体層を除去して配線導体層を形成するとともに、基板の表面のうち配線導体層の非形成領域を一部除去してこの配線導体層の非形成領域を配線導体層の直下の領域に対して凹ませる工程と、レジスト層を除去する工程と、しかる後、基板の表面に配線導体層を覆って樹脂絶縁層を形成する工程とを具備することから、第1の製造方法と同様に、基板の表面のうち配線導体層の非形成領域を表面側から一部除去することによって、その配線導体層の非形成領域の基板の表面に発生した配線導体層成分の残さが確実に除去されるとともに、配線導体層の直下の領域に対して配線導体層の非形成領域に凹みが形成されて隣接する配線導体層間の経路が長くなることにより、配線導体層間の絶縁性が低下することがなくなり、さらに、隣接する配線導体層間の絶縁性の低下を防止する配線導体層の非形成領域の凹みを第1の製造方法よりも少ない工数で形成できる、耐環境信頼性の優れた多層配線基板の製造方法を提供できた。
【図面の簡単な説明】
【図1】本発明の多層配線基板の実施の形態の一例を示す断面図である。
【図2】図1に示す多層配線基板における配線導体層の非形成領域の凹みを示す要部拡大断面図である。
【符号の説明】
1・・・・基板
2・・・・配線導体層
3・・・・樹脂絶縁層
4・・・・配線導体層の非形成領域
5・・・・凹み
6・・・・下地導体層
7・・・・主導体層
8・・・・絶縁性接着剤層
9・・・・絶縁フィルム層
10・・・・多層配線部
11・・・・貫通孔
12・・・・貫通導体
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a multilayer wiring board used for a package for accommodating a semiconductor element for accommodating a hybrid integrated circuit or a semiconductor element, and a method for manufacturing the same.
[0002]
[Prior art]
2. Description of the Related Art In recent years, with the miniaturization and multifunctionality of electronic devices, semiconductor devices such as semiconductor integrated circuit elements used therein have been highly integrated and the number of input / output terminals has been increasing. For a wiring board on which such a semiconductor device is mounted and a wiring board used for testing the device, it is a matter of course that a high integration of a circuit is required, and an input / output caused by a mismatch of a thermal expansion coefficient is required. The stress applied to the wiring board, such as the stress on the terminal section and the contact pressure applied to the wiring board by the probe during the test, increases with the increase in the number of input / output terminals of the semiconductor device. Therefore, there is a demand for high strength so as to have sufficient strength as a support for supporting input / output terminals of a semiconductor device, a probe for testing, and the like. Therefore, a high-strength multilayer wiring board having an extremely fine wiring pattern is required.
[0003]
Due to the demand for higher integration and higher strength for such multilayer wiring boards, instead of multilayer printed wiring boards and build-up type multilayer wiring boards, the multilayer wiring boards consist of a thin insulating layer and a wiring conductor layer on a substrate made of ceramics. Attention has been focused on a ceramic thin-film hybrid multilayer wiring board having a thin-film multilayer wiring section formed thereon.
[0004]
Such a ceramic thin film hybrid multilayer wiring board is formed of a metal such as copper or aluminum on the upper surface of a ceramic multilayer wiring board including a metallized wiring layer made of molybdenum or tungsten and a ceramic insulating layer such as an aluminum oxide sintered body, Wiring conductor layer formed by adopting thin film forming technology such as plating method and vapor deposition method and photolithography technology, and resin insulating layer of thin film made of polyimide resin etc. formed by spin coating method and thermosetting treatment It is expected to be used as a multilayer wiring board that has a function as a high-strength support and has excellent circuit integration due to an extremely fine wiring pattern. I have.
[0005]
In the case where a resin insulating layer made of a polyimide resin or the like is formed by a spin coating method, a thermosetting treatment, or the like for such a thin-film multilayer wiring portion, it is necessary to divide the resin insulating layer into a desired thickness in a number of times. A resin insulating layer is formed by applying a precursor of a polyimide resin, and then performing a curing step of converting the precursor of the polyimide resin into a polyimide.
[0006]
However, such a method of forming a resin insulating layer has a problem that the manufacturing process is lengthened. Therefore, instead of this forming method, a plurality of insulating film layers made of a polyimide resin or the like are interposed between insulating films made of a bismaleimide triazine resin or the like. A method of forming a resin insulating layer formed by laminating via a conductive adhesive layer has been adopted.
[0007]
[Problems to be solved by the invention]
However, in such a ceramic thin-film hybrid multilayer wiring board, the wiring conductor layer and the surface of the substrate are more strongly bonded to each other by a chemical bond and a bonding by an anchor effect caused by the wiring conductor layer cutting into the unevenness of the substrate surface. When the conductor layer formed in the non-formation area of the wiring conductor layer on the surface of the substrate is removed by etching or the like, the residue of the conductor layer component remains in the non-formation area of the wiring conductor layer. When a resin insulating layer is formed and laminated on the wiring conductor layer and the region where the wiring conductor layer is not formed as it is, there is a problem that the insulation between the wiring conductors is apt to decrease.
[0008]
The present invention has been made in view of the above problems in the related art, and an object of the present invention is to effectively prevent a decrease in insulation between wiring conductor layers formed on the surface of a substrate by a simple method. Another object of the present invention is to provide a multilayer wiring board having excellent environmental resistance.
[0009]
Further, another object of the present invention is to provide a multilayer wiring board excellent in environmental resistance and reliability in which a decrease in insulation between wiring conductor layers formed on the surface of the board is effectively prevented by a simple method. An object of the present invention is to provide a method for manufacturing a multilayer wiring board.
[0010]
[Means for Solving the Problems]
The multilayer wiring board of the present invention is a multilayer wiring board in which a wiring conductor layer is formed on a surface of the substrate and a resin insulating layer is formed to cover the wiring conductor layer. The region where no layer is formed is recessed with respect to the region immediately below the wiring conductor layer.
[0011]
Further, in the multilayer wiring board of the present invention, in the above structure, the non-formation region is recessed at a depth of 0.1 to 10 μm with respect to a region immediately below the wiring conductor layer. is there.
[0012]
The first method for manufacturing a multilayer wiring board according to the present invention includes a step of forming a base conductor layer on the surface of the substrate, and a step of forming a resist layer having an opening of a pattern of the wiring conductor layer on the base conductor layer; Forming a main conductor layer on the underlying conductor layer exposed from the opening, removing the resist layer, and removing the underlying conductor layer exposed from the main conductor layer to form a wiring conductor layer A step of partially removing a region where the wiring conductor layer is not formed on the surface of the substrate so as to be depressed with respect to a region immediately below the wiring conductor layer; and thereafter, forming the wiring conductor layer on the surface of the substrate. And forming a resin insulating layer over the substrate.
[0013]
Further, according to a second method of manufacturing a multilayer wiring board of the present invention, a step of forming a base conductor layer on a surface of a substrate; a step of forming a main conductor layer on the base conductor layer; Forming a resist layer having a pattern of a wiring conductor layer, removing the main conductor layer and the base conductor layer exposed from the resist layer to form a wiring conductor layer, and forming the wiring conductor on the surface of the substrate. A step of partially removing the non-forming region of the layer to depress the region immediately below the wiring conductor layer, a step of removing the resist layer, and then covering the wiring conductor layer on the surface of the substrate. And forming a resin insulating layer by using the above method.
[0014]
According to the multilayer wiring board of the present invention, since the region where the wiring conductor layer is not formed on the surface of the substrate is recessed with respect to the region immediately below the wiring conductor layer, the path between the adjacent wiring conductor layers becomes longer. Thereby, the insulation between the wiring conductor layers does not decrease, and a multilayer wiring board having excellent environmental resistance and reliability can be realized.
[0015]
Further, according to the multilayer wiring board of the present invention, when the region where the wiring conductor layer is not formed is recessed at a depth of 0.1 to 10 μm with respect to the region immediately below the wiring conductor layer, the adjacent wiring conductor layer When the resin insulating layer is formed on the surface of the substrate over the non-formation area of the wiring conductor layer while the insulation property between the wiring conductor layers is not reduced by increasing the length of the path to a required length. The flatness of the resin insulation layer can be improved, the environmental resistance is excellent, and the connection reliability with the input / output terminals of the semiconductor device mounted on this multilayer wiring board is also excellent. A multilayer wiring board can be realized.
[0016]
According to the first method for manufacturing a multilayer wiring board of the present invention, a step of forming a base conductor layer on a surface of a substrate and a step of forming a resist layer having an opening of a pattern of the wiring conductor layer on the base conductor layer And forming a main conductor layer on the underlying conductor layer exposed from the opening of the resist layer, removing the resist layer, and removing the underlying conductor layer exposed from the main conductor layer to correspond to the pattern of the opening. A wiring conductor layer having a shape is formed, and a region where the wiring conductor layer is not formed is partially removed from the surface of the substrate so that the region where the wiring conductor layer is not formed is depressed with respect to a region immediately below the wiring conductor layer. A step of forming a resin insulating layer over the non-formation area of the wiring conductor layer by covering the wiring conductor layer after that, so that the non-formation area of the wiring conductor layer in the surface of the substrate is Partly removed from the side Therefore, the residue of the wiring conductor layer component generated on the surface of the substrate in the region where the wiring conductor layer is not formed is reliably removed, and the region immediately below the wiring conductor layer is recessed in the region where the wiring conductor layer is not formed. Is formed and the path between the adjacent wiring conductor layers is lengthened, whereby the insulation between the wiring conductor layers is not reduced, and a multilayer wiring board having excellent environmental resistance and reliability can be realized by a simple method. A method for manufacturing a multilayer wiring board can be provided.
[0017]
According to the second method for manufacturing a multilayer wiring board of the present invention, a step of forming a base conductor layer on a surface of a substrate, a step of forming a main conductor layer on the base conductor layer, and a step of forming a main conductor layer on the base conductor layer Forming a resist layer of a pattern of the wiring conductor layer, removing the main conductor layer and the base conductor layer exposed from the resist layer to form a wiring conductor layer, and forming a wiring conductor layer on the surface of the substrate; A step of partially removing the region to depress the non-formed area of the wiring conductor layer with respect to the area immediately below the wiring conductor layer, and a step of removing the resist layer, and thereafter, the wiring conductor layer is formed on the surface of the substrate. And forming a resin insulating layer over the wiring board by removing a part of the surface of the substrate where the wiring conductor layer is not formed from the front side, as in the first manufacturing method. On the surface of the substrate where the conductive layer is not formed The generated wiring conductor layer component is reliably removed, and a recess is formed in a region where the wiring conductor layer is not formed with respect to a region immediately below the wiring conductor layer, so that a path between the adjacent wiring conductor layers becomes longer. Thereby, the insulation between the wiring conductor layers does not decrease, and the dent in the non-formation region of the wiring conductor layer for preventing the insulation between the adjacent wiring conductor layers from decreasing is reduced by a smaller number of steps than the first manufacturing method. A method of manufacturing a multilayer wiring board which can be formed and has excellent environmental resistance can be provided.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the drawings.
[0019]
FIG. 1 is a sectional view showing an example of an embodiment of a multilayer wiring board according to the present invention, and FIG. 2 is an enlarged sectional view of a main part showing a recess in a region where a wiring conductor layer is not formed in the multilayer wiring board.
[0020]
In these figures, 1 is a substrate, 2 is a wiring conductor layer, 3 is a resin insulating layer, 4 is a region where no wiring conductor layer is formed, 5 is a recess, 6 is a base conductor layer as a part of the wiring conductor layer 2, 7 is a main conductor layer as a part of the wiring conductor layer 2, 8 is an insulating adhesive layer as a part of the resin insulation layer 3, 9 is an insulating film layer as a part of the resin insulation layer 3, and 10 is a multilayer. The wiring portion, 11 is a through hole, and 12 is a through conductor.
[0021]
The substrate 1, on the surface of which, in this example, the upper surface, is provided with a multilayer wiring portion 10 in which wiring conductor layers 2 and resin insulating layers 3 are alternately laminated in multiple layers, and a support member for supporting the multilayer wiring portion 10 is provided. Function as
[0022]
The substrate 1 is made of, for example, an aluminum oxide sintered body, a mullite sintered body, an oxide ceramic such as a glass ceramic, an aluminum nitride sintered body having an oxide film on its surface, a silicon carbide sintered body, or the like. Formed of an electrically insulating material such as non-oxide ceramics or glass ceramics. Thermosetting resins such as epoxy resin, bismaleimide triazine resin, thermosetting polyphenylene ether resin, and phenol resin; and thermoplastic resins such as polyimide resin, fluorine resin, polyphenylene ether resin, liquid crystal polymer resin, aramid resin, and polyethylene terephthalate. It may be formed of various organic insulating resin materials such as resin, a composite material obtained by combining inorganic insulating powder such as ceramics with an organic insulating resin, or an electric insulating material such as glass, quartz, and sapphire.
[0023]
For example, when it is formed of an aluminum oxide sintered body, a raw material powder such as alumina, silica, calcia, and magnesia is mixed with an appropriate organic solvent and a solvent to form a slurry, which is conventionally well known. A ceramic green sheet (ceramic green sheet) is formed by adopting the doctor blade method or the calendar roll method, and then the ceramic green sheet is subjected to an appropriate punching process to form a predetermined shape and, if necessary, a wiring. It is manufactured by printing and forming a conductor pattern serving as a conductor, laminating a predetermined number of layers, and firing at a high temperature (about 1600 ° C.). Alternatively, a raw material powder is prepared by adding and mixing an appropriate organic solvent and a solvent to a raw material powder such as alumina, and the raw material powder is formed into a predetermined shape by a press molding machine. C).
[0024]
When the substrate 1 is formed of glass ceramics, an organic binder, a plasticizer, a solvent, and the like are added to a mixture of glass and an inorganic filler (inorganic insulating powder) to form a slurry, and the glass is formed by a doctor blade method or the like. After forming the ceramic green sheet, a conductor pattern containing a powder of a low-resistance metal such as Cu, Ag, or Au was printed on the glass ceramic green sheet to form a conductor pattern, and then the conductor pattern was formed. It is manufactured by laminating a plurality of glass ceramic green sheets and firing at a temperature of 800 to 1000 ° C.
[0025]
As the glass ceramic green sheet, a mixture of a glass powder, an inorganic filler (ceramic powder), an organic binder, a plasticizer, an organic solvent, and the like is used.
[0026]
As the glass component, for example, SiO 22-B2O3System, SiO2-B2O3-Al2O3System, SiO2-B2O3-Al2O3-MO system (where M represents Ca, Sr, Mg, Ba or Zn), SiO2-Al2O3-M1OM2O type (however, M1And M2Represent the same or different Ca, Sr, Mg, Ba or Zn), SiO2-B2O3-Al2O3-M1OM2O type (however, M1And M2Is the same as above), SiO2-B2O3-M3 2O type (however, M3Represents Li, Na or K), SiO2-B2O3-Al2O3-M3 2O type (however, M3Is the same as described above), Pb-based glass, Bi-based glass and the like.
[0027]
As the inorganic filler, for example, Al2O3, SiO2, ZrO2Oxide of TiO2 and alkaline earth metal oxide, TiO2Oxide of aluminum and alkaline earth metal oxide, Al2O3And SiO2And complex oxides containing at least one selected from the group consisting of spinel, mullite, cordierite, and the like.
[0028]
In the multilayer wiring board of the present invention, a wiring conductor layer 2 is formed on the surface of the substrate 1 and a resin insulating layer 3 is formed to cover the wiring conductor layer 2. Of these, it is important that the non-formed region 4 of the wiring conductor layer is depressed with respect to the surface of the substrate 1 in a region immediately below the wiring conductor layer 2.
[0029]
As a result, the length of the route between the adjacent wiring conductor layers 2 passing through the surface of the substrate 1 becomes longer, so that the insulation between the wiring conductor layers 2 does not decrease, and the multilayer wiring board having excellent environmental resistance and reliability. This is because it can be realized.
[0030]
On the other hand, when the region 4 where the wiring conductor layer is not formed on the surface of the substrate 1 is not depressed with respect to the surface of the substrate 1 just below the wiring conductor layer 2, the area between the adjacent wiring conductor layers 2 Path becomes the shortest distance and becomes short, so that the insulation between the wiring conductor layers 2 tends to be easily reduced.
[0031]
In the multilayer wiring section 10, the wiring conductor layer 2 formed on the surface of the substrate 1 may be formed, for example, as follows.
[0032]
A base conductor layer 6 containing an active metal such as Ti, Cr or Mo, which plays a role of bonding with the surface, and Cu as a main conductor layer 7 is formed on the surface of the substrate 1 by a vacuum film forming method or electrolytic or electroless plating. Then, a resist layer having an opening of the pattern of the wiring conductor layer 2 is formed on the underlying conductor layer 6, and a vacuum film forming method or an electrolytic method is performed on the underlying conductor layer 6 exposed from the opening of the resist layer. Alternatively, the main conductor layer 7 is formed to a desired thickness by electroless plating, for example, by electrolytic Cu plating. After that, the resist layer is removed by using a stripping solution or the like, and the underlying conductive layer 6 which is protruded from the main conductive layer 7 and is exposed is removed by etching, blasting, polishing, or the like to form a wiring having a shape corresponding to the pattern of the opening of the resist layer. The conductor layer 2 is formed, and the region 4 where the wiring conductor layer is not formed in the surface of the substrate 1 is partially removed from the surface side by etching, blasting, polishing or the like to form a recess 5. Thereby, the residue of the wiring conductor layer 2, more specifically, the residue of the base conductor layer 6 generated in the non-forming region 4 of the wiring conductor layer can be reliably removed from the surface of the substrate 1, and the formation of the wiring conductor layer can be prevented. A recess is formed in the region 4 and a path between the adjacent wiring conductor layers 2 passing through the surface of the substrate 1 becomes longer, so that insulation between the wiring conductor layers 2 does not decrease and a desired pattern is provided. The wiring conductor layers 2 arranged at high density can be formed.
[0033]
At this time, if glass ceramics is adopted as the substrate 1, the insulating layer can be composed of glass ceramics having a low dielectric constant, and the wiring conductor layer 2 can be composed of a low-resistance metal such as Cu. This is advantageous because it can function as an excellent support. In particular, when the relative dielectric constant is 7 or less, excellent high-frequency characteristics can be obtained, which is more convenient.
[0034]
Further, assuming that the depth of the recess 5 in the region 4 where the wiring conductor layer is not formed and the region immediately below the wiring conductor layer 2 is 0.1 μm to 10 μm, the surface of the substrate 1 covers the wiring conductor layer 2 and When the resin insulation layer 3 is formed over the non-formation region 4, the residue of the wiring conductor layer 2 generated in the non-formation region 4 of the wiring conductor layer can be removed without impairing the flatness of the surface of the resin insulation layer 3. Since the length of the route between the adjacent wiring conductor layers 2 via the non-forming region 4 of the wiring conductor layer can be increased to a required length, it is possible to prevent a decrease in insulation between the wiring conductor layers 2. It is effective.
[0035]
When the depth of the recess 5 is less than 0.1 μm, the effect of removing the residue of the wiring conductor layer 2 component generated in the region 4 where the wiring conductor layer is not formed tends to be weak, and when the depth exceeds 10 μm, it is formed thereon. The flatness of the surface of the resin insulating layer 3 tends to decrease. In this case, the depth of the recess 5 can be easily controlled by using, for example, a mixed aqueous solution of hydrofluoric acid and nitric acid as an etchant when partially removing the surface of the substrate 1 from the surface side.
[0036]
The method for forming the recess 5 in the second method of manufacturing a multilayer wiring board according to the present invention is as follows. An active metal such as Ti, Cr or Mo serving as a joint with the surface and a main conductor are formed on the surface of the substrate 1. The underlying conductor layer 6 containing Cu as the layer 7 and the Cu layer as the main conductor layer 7 are formed by a vacuum film forming method. Alternatively, after the surface of the substrate 1 is roughened with an etching solution containing phosphoric acid or hydrofluoric acid, a surface treatment is performed with an active solution containing Pd, and the underlying conductor layer 6 is formed by electroless Cu plating. The main conductor layer 7 is formed by plating. Next, a resist layer having a pattern of the wiring conductor layer 2 is formed on the upper surface of the main conductor layer 7, and the main conductor layer 7 and the underlying conductor layer 6 which are protruded from the resist layer and exposed are removed by a method such as etching. The wiring conductor layer 2 is formed in the shape of the layer pattern, and the region 4 where the wiring conductor layer is not formed on the surface of the substrate 1 is etched from the surface side by a method such as etching with an etching solution containing phosphoric acid or hydrofluoric acid. When the area where the wiring conductor layer is not formed is recessed with respect to the surface of the substrate 1 in the area immediately below the wiring conductor layer 2, the wiring conductor layer 2 generated in the area where the wiring conductor layer is not formed, A wiring conductor capable of providing high-density wiring, which has a desired pattern and is capable of preventing a decrease in insulation between the wiring conductor layers 2, which can reliably remove mainly the residual components of the base conductor layer 6 together with part of the surface of the substrate 1. Layer 2 It can be formed with no steps.
[0037]
The resin insulating layer 3 of the multilayer wiring portion 10 is composed of an insulating film layer 9 and an insulating adhesive layer 8, and the insulating film layer 9 is made of a polyimide resin, a polyphenylene sulfide resin, a wholly aromatic polyester resin, a fluororesin, or the like. The insulating adhesive layer 8 is made of a polyamide imide resin, a polyimide siloxane resin, a bismaleimide triazine resin, an epoxy resin, or the like.
[0038]
The resin insulating layer 3 is prepared by first applying an insulating adhesive to an insulating film having a thickness of about 12.5 to 50 μm to a dry thickness of about 5 to 20 μm using a doctor blade method or the like, and drying the resin. The insulating film layer 9 is formed by stacking the insulating adhesive layer 8 on the upper surface of the substrate 1 or the lower resin insulating layer 3 so that the insulating adhesive layer 8 is disposed therebetween, and applying heat and pressure using a heating press device to bond the insulating film. You.
[0039]
In the resin insulating layer 3, a through hole 11 is formed at a predetermined position, penetrating the insulating film layer 9 and the insulating adhesive layer 8, and a through conductor 12 is formed in the through hole 11 by being formed. A connection path for electrically connecting each of the wiring conductor layers 2 positioned above and below the resin insulating layer 3 is formed.
[0040]
The through hole 11 is formed by removing a part of the insulating film layer 9 and the insulating adhesive layer 8 using a laser, for example. In particular, when the opening diameter of the through-hole 11 is small, it is desirable to form the through-hole 11 with an ultraviolet laser that can easily control the angle of the inner wall surface and smoothly process the inner wall surface of the through-hole 11.
[0041]
The through conductor 12 may be formed separately from the wiring conductor layer 2 disposed on the upper surface of each resin insulating layer 3. However, when these are formed at the same time, the number of steps can be reduced and the electrical connection reliability between the two can be reduced. It is also good in terms of properties.
[0042]
When the wiring conductor layer 2 and the through conductor 11 provided on the upper surface of each resin insulating layer 3 are integrally formed, a plating film having a desired thickness can be adjusted and formed respectively. It is preferable to form them mainly using an electrolytic plating method.
[0043]
The method of forming the wiring conductor layer 2 and the through conductor 11 disposed on the upper surface of each resin insulating layer 3 may be, for example, as follows. First, a base conductor layer 6 containing an active metal such as Ti, Cr, Mo or the like which plays a role of bonding with the resin insulating layer 3 and Cu as a main conductor is formed by a vacuum film forming method or a plating method. A resist layer having an opening of the pattern of the wiring conductor layer 2 is formed on the conductor layer 6, and a main conductor layer 7 is formed to a desired thickness by, for example, electrolytic Cu plating on the underlying conductor layer 6 exposed from the opening of the resist layer. I do. After that, the resist layer is removed by using a stripping solution or the like, and the underlying conductor layer 6 which is protruded from the main conductor layer 7 and is exposed is removed by etching or the like, and the wiring conductor layer 2 having a shape corresponding to the pattern of the opening in the resist layer is removed. To form
[0044]
The wiring conductor layer 2 formed on the surface of the uppermost layer of the resin insulating layer 3 which is the surface of the multilayer wiring section 10 has the following problems in terms of the mountability and environmental resistance of semiconductor devices and chip components to be mounted. When the main conductor layer 7 is made of a Cu layer, a Ni layer or an Au layer may be formed thereon.
[0045]
Thus, according to the multilayer wiring board of the present invention, electronic components such as semiconductor devices including semiconductor elements, chip components such as capacitance elements and resistors are mounted on the multilayer wiring portion 10 provided on the surface of the substrate 1. By mounting and mounting, and electrically connecting the respective electrodes of the semiconductor devices and electronic components to the wiring conductor layer 2, a semiconductor device, a hybrid integrated circuit device, or the like is obtained.
[0046]
The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention.
[0047]
For example, in the example of the above-described embodiment, the method of controlling the depth of the recess 5 in the non-forming region 4 of the wiring conductor layer by using the etching liquid has been described. Alternatively, a method of controlling the removal amount by sand blasting, wet blasting, or mechanical removal means such as polishing or rubbing may be used.
[0048]
The multilayer wiring board of the present invention can be applied not only to a module board or the like constituting a hybrid integrated circuit device or the like but also to a semiconductor element housing package for housing a semiconductor element.
[0049]
【The invention's effect】
As described above, according to the multilayer wiring board of the present invention, since the region where the wiring conductor layer is not formed on the surface of the substrate is recessed with respect to the region immediately below the wiring conductor layer, the area between the adjacent wiring conductor layers is reduced. By increasing the length of the path, the insulation between the wiring conductor layers was not reduced, and a multilayer wiring board having excellent environmental resistance and reliability could be realized.
[0050]
Further, according to the multilayer wiring board of the present invention, when the region where the wiring conductor layer is not formed is recessed at a depth of 0.1 to 10 μm with respect to the region immediately below the wiring conductor layer, the adjacent wiring conductor layer When the resin insulating layer is formed on the surface of the substrate over the non-formation area of the wiring conductor layer while the insulation between the wiring conductor layers is not reduced by increasing the length of the path to the required length. The flatness of the resin insulation layer can be improved, the environmental resistance is excellent, and the connection reliability with the input / output terminals of the semiconductor device mounted on this multilayer wiring board is also excellent. A multilayer wiring board was realized.
[0051]
According to the first method for manufacturing a multilayer wiring board of the present invention, a step of forming a base conductor layer on a surface of a substrate and a step of forming a resist layer having an opening of a pattern of the wiring conductor layer on the base conductor layer And forming a main conductor layer on the underlying conductor layer exposed from the opening of the resist layer, removing the resist layer, and removing the underlying conductor layer exposed from the main conductor layer to correspond to the pattern of the opening. A wiring conductor layer having a shape is formed, and a region where the wiring conductor layer is not formed is partially removed from the surface of the substrate so that the region where the wiring conductor layer is not formed is depressed with respect to a region immediately below the wiring conductor layer. A step of forming a resin insulating layer over the non-formation area of the wiring conductor layer by covering the wiring conductor layer after that, so that the non-formation area of the wiring conductor layer in the surface of the substrate is Partly removed from the side Therefore, the residue of the wiring conductor layer component generated on the surface of the substrate in the region where the wiring conductor layer is not formed is reliably removed, and the region immediately below the wiring conductor layer is recessed in the region where the wiring conductor layer is not formed. Is formed and the path between the adjacent wiring conductor layers is lengthened, whereby the insulation between the wiring conductor layers is not reduced, and a multilayer wiring board having excellent environmental resistance and reliability can be realized by a simple method. A method for manufacturing a multilayer wiring board can be provided.
[0052]
According to the second method for manufacturing a multilayer wiring board of the present invention, a step of forming a base conductor layer on a surface of a substrate, a step of forming a main conductor layer on the base conductor layer, and a step of forming a main conductor layer on the base conductor layer Forming a resist layer of a pattern of the wiring conductor layer, removing the main conductor layer and the base conductor layer exposed from the resist layer to form a wiring conductor layer, and forming a wiring conductor layer on the surface of the substrate; A step of partially removing the region to depress the non-formed area of the wiring conductor layer with respect to the area immediately below the wiring conductor layer, and a step of removing the resist layer, and thereafter, the wiring conductor layer is formed on the surface of the substrate. And forming a resin insulating layer over the wiring board by removing a part of the surface of the substrate where the wiring conductor layer is not formed from the front side, as in the first manufacturing method. On the surface of the substrate where the conductive layer is not formed The generated wiring conductor layer components are reliably removed, and a dent is formed in a region where the wiring conductor layer is not formed with respect to a region immediately below the wiring conductor layer, so that a path between the adjacent wiring conductor layers becomes longer. Thereby, the insulation between the wiring conductor layers does not decrease, and the dent in the non-formation region of the wiring conductor layer for preventing the insulation between the adjacent wiring conductor layers from decreasing is reduced by a smaller number of steps than the first manufacturing method. A method of manufacturing a multilayer wiring board which can be formed and has excellent environmental resistance can be provided.
[Brief description of the drawings]
FIG. 1 is a sectional view showing an example of an embodiment of a multilayer wiring board of the present invention.
FIG. 2 is an enlarged sectional view of a main part showing a recess in a region where a wiring conductor layer is not formed in the multilayer wiring board shown in FIG. 1;
[Explanation of symbols]
1 ... substrate
2. Wiring conductor layer
3 ... Resin insulation layer
4... Area where no wiring conductor layer is formed
5 ... dent
6 Underlay conductor layer
7 ... Main conductor layer
8 ... Insulating adhesive layer
9 ... Insulating film layer
10 Multilayer wiring section
11 ... Through-hole
12 ... Through conductor

Claims (4)

基板の表面に、配線導体層が形成されるとともに、該配線導体層を覆って樹脂絶縁層が形成された多層配線基板において、前記基板の表面のうち前記配線導体層の非形成領域が、前記配線導体層の直下の領域に対して凹んでいることを特徴とする多層配線基板。On a surface of the substrate, a wiring conductor layer is formed, and in a multilayer wiring board in which a resin insulating layer is formed so as to cover the wiring conductor layer, an area where the wiring conductor layer is not formed on the surface of the substrate is A multilayer wiring board which is depressed with respect to a region immediately below a wiring conductor layer. 前記非形成領域が、前記配線導体層の直下の領域に対して0.1乃至10μmの深さで凹んでいることを特徴とする請求項1記載の多層配線基板。2. The multilayer wiring board according to claim 1, wherein the non-forming region is recessed at a depth of 0.1 to 10 [mu] m from a region immediately below the wiring conductor layer. 基板の表面に下地導体層を形成する工程と、該下地導体層上に配線導体層のパターンの開口を有するレジスト層を形成する工程と、前記開口から露出した前記下地導体層上に主導体層を形成する工程と、前記レジスト層を除去する工程と、前記主導体層から露出した前記下地導体層を除去して配線導体層を形成するとともに、前記基板の表面のうち前記配線導体層の非形成領域を一部除去して前記配線導体層の直下の領域に対して凹ませる工程と、しかる後、前記基板の表面に前記配線導体層を覆って樹脂絶縁層を形成する工程とを具備することを特徴とする多層配線基板の製造方法。Forming a base conductor layer on the surface of the substrate, forming a resist layer having an opening of the wiring conductor layer pattern on the base conductor layer, and forming a main conductor layer on the base conductor layer exposed from the opening Forming the resist layer, removing the base conductor layer exposed from the main conductor layer to form a wiring conductor layer, and forming a wiring conductor layer on the surface of the substrate. A step of forming a resin insulating layer on the surface of the substrate by covering the wiring conductor layer on the surface of the substrate, after which a part of the formation region is partially removed to make the area directly below the wiring conductor layer concave. A method for manufacturing a multilayer wiring board, comprising: 基板の表面に下地導体層を形成する工程と、該下地導体層上に主導体層を形成する工程と、該主導体層上に配線導体層のパターンのレジスト層を形成する工程と、該レジスト層から露出した前記主導体層および前記下地導体層を除去して配線導体層を形成するとともに、前記基板の表面のうち前記配線導体層の非形成領域を一部除去して前記配線導体層の直下の領域に対して凹ませる工程と、前記レジスト層を除去する工程と、しかる後、前記基板の表面に前記配線導体層を覆って樹脂絶縁層を形成する工程とを具備することを特徴とする多層配線基板の製造方法。Forming a base conductor layer on the surface of the substrate, forming a main conductor layer on the base conductor layer, forming a resist layer having a pattern of a wiring conductor layer on the main conductor layer; The main conductor layer and the base conductor layer exposed from the layer are removed to form a wiring conductor layer, and a part of the surface of the substrate where the wiring conductor layer is not formed is partially removed to remove the wiring conductor layer. A step of forming a resin insulating layer covering the wiring conductor layer on the surface of the substrate, and a step of recessing the area immediately below, removing the resist layer, and thereafter. Of manufacturing a multilayer wiring board.
JP2002188454A 2002-06-27 2002-06-27 Manufacturing method of multilayer wiring board Expired - Fee Related JP4022105B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002188454A JP4022105B2 (en) 2002-06-27 2002-06-27 Manufacturing method of multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002188454A JP4022105B2 (en) 2002-06-27 2002-06-27 Manufacturing method of multilayer wiring board

Publications (2)

Publication Number Publication Date
JP2004031813A true JP2004031813A (en) 2004-01-29
JP4022105B2 JP4022105B2 (en) 2007-12-12

Family

ID=31183198

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002188454A Expired - Fee Related JP4022105B2 (en) 2002-06-27 2002-06-27 Manufacturing method of multilayer wiring board

Country Status (1)

Country Link
JP (1) JP4022105B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010027832A (en) * 2008-07-18 2010-02-04 Tdk Corp Semiconductor-embedded module and its manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010027832A (en) * 2008-07-18 2010-02-04 Tdk Corp Semiconductor-embedded module and its manufacturing method
US8742589B2 (en) 2008-07-18 2014-06-03 Tdk Corporation Semiconductor embedded module and method for producing the same

Also Published As

Publication number Publication date
JP4022105B2 (en) 2007-12-12

Similar Documents

Publication Publication Date Title
US7139176B2 (en) Circuit substrate and method for fabricating the same
US20150136449A1 (en) Multilayered wiring substrate
JPH11112142A (en) Multilayered wiring board
JP4578254B2 (en) Multilayer wiring board
JP2004031813A (en) Multilayer wiring board and its manufacturing method
JP2005268259A (en) Multilayer wiring board
JP2005101377A (en) Multilayer wiring board
JP4467341B2 (en) Manufacturing method of multilayer wiring board
JP2014049589A (en) Multilayer wiring board and probe card using the same
JPH06164146A (en) Multilayer interconnection board
JP2006147932A (en) Multilayer wiring board and its manufacturing method
JP3688844B2 (en) Multilayer wiring board
JP2005268517A (en) Multilayer wiring board
JPH10322029A (en) Multilayered wiring board
JP3798965B2 (en) Multilayer wiring board
JPH114080A (en) Multilayered wiring board
JPH10163634A (en) Multilayer wiring board
JPH09312479A (en) Multi-layer circuit board
JPH06164144A (en) Multilayer interconnection board
JP2000133506A (en) Manufacture of wiring board having resistor
JP3872339B2 (en) Multilayer wiring board
JP2003069224A (en) Multilayer interconnection board
JP2006196832A (en) Multi layer wiring board
JP2002252457A (en) Multilayer wiring board
JP2003282779A (en) Multilayer wiring board

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20041203

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060621

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060627

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060823

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060919

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070309

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070426

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070904

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070928

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101005

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4022105

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101005

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111005

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121005

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131005

Year of fee payment: 6

LAPS Cancellation because of no payment of annual fees