JP2004029952A - Semiconductor integrated circuit and image processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of recovering from a hang-up state by itself without depending on a method such as software reset. <P>SOLUTION: A read timing signal RTIM and a write timing signal WTIM outputted from flip flops 212C and 212D configuring a state machine are inputted to an AND circuit 212G, therby the start of the state of the state machine is detected. A counter 212H starts a count by using the output signal of the AND circuit 212G as a trigger. This count value CNT is compared with a predetermined value TMAX by a comparator 212J, and when the count value CNT reaches the predetermined value TMAX, a hang-up flag HFLG is outputted. Then, OR circuits 212A and 212B forcibly reset the flop flops 212C and 212D based on the hang-up flag HFLG. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit and an image processing apparatus, and more particularly to a technique for generating an effect image and sound effects in a game machine such as a pachinko machine in accordance with a game development situation.
[0002]
[Prior art]
Conventionally, gaming machines such as pachinko machines have a control device for controlling the progress of the game, an image processing device for generating images such as symbols according to the progress of the game, or a device for generating a sound effect. A sound control device and the like are built in. This type of device is configured as a so-called state machine, and the next operation state is determined according to the current operation state.
By the way, since there are many noise sources such as a motor for hitting the ball and a driving circuit for lighting decoration inside the gaming machine, a semiconductor integrated circuit in each device configured as a state machine malfunctions, and It may fall into a hang-up state. Therefore, conventionally, this type of device is provided with a function for returning from a hang-up state.
[0003]
Here, as a conventional technique for returning from the hang-up state, there is a method of resetting a circuit state by a so-called software process (hereinafter, referred to as software reset). According to this software reset, a command for resetting the operation of an LSI (Large Scale Integration) that has fallen into a hang-up state is issued from a CPU (Central Processing Unit) constituting the device, and an internal circuit of the LSI (for example, Reset the state machine formed by flip-flops and registers. Software reset methods include a method using a watchdog timer and a method of resetting when a hang-up is detected by reading a flag indicating that a hang-up has occurred.
[0004]
[Problems to be solved by the invention]
However, according to the above-described software reset, if a circuit that cannot be reset partially exists, there is a problem that the entire circuit may not be reset and the device may not be able to return from the hang-up state. Further, since the CPU needs to detect that the internal circuit of the LSI has fallen into a hang-up state, the load on the CPU increases. Further, when the interface circuit of the CPU falls into a hang-up state, the CPU cannot not only detect a hang-up of the LSI, but also cannot issue a command for resetting.
[0005]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor integrated circuit and an image processing apparatus capable of returning from a hang-up state by itself without using a method such as software reset.
[0006]
[Means for Solving the Problems]
In order to solve the above problems, the present invention has the following configurations.
That is, according to the first aspect of the present invention, in a semiconductor integrated circuit configured to function as a state machine, a detecting means for detecting a state of the state machine (for example, a component corresponding to an AND circuit 212G described later) ), Time counting means for counting the stay time of the state detected by the detection means (for example, a component corresponding to a counter 212H described later), and the state machine being in a hang-up state based on the stay time counted by the time counting means. (E.g., a component corresponding to a comparator 212J described later) and a reset unit (e.g., a reset unit that resets the state machine when the determination result of the determination unit indicates a hang-up state). For example, constituent elements corresponding to OR circuits 212A and 212B described later), Characterized by comprising.
[0007]
According to the configuration of the present invention, when the state machine falls into a hang-up state, the hang-up state is grasped from the stay time of the same state by utilizing the fact that the stay time of the same state becomes longer. That is, the staying time of the same state is counted by the timer, and whether or not the state machine is in a hang-up state is determined by the determining unit based on the counted staying time. If it is determined that the state machine is in the hang-up state, the state machine is reset by reset means. In other words, according to this configuration, the state machine is reset on condition that the current state of the state machine does not shift to the next state within the scheduled time. Therefore, the state machine can be returned from the hang-up state without an external operation such as a software reset.
[0008]
According to a second aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the timing means detects a start of a state of the state machine by a logic circuit (for example, an AND circuit 212G described later). And a counter (for example, a component corresponding to a counter 212H to be described later) that starts counting by using an output signal of the logic circuit as a trigger, wherein the determination unit determines the count value of the counter, A comparator (for example, a component corresponding to a comparator 212J to be described later) for comparing a maximum value of the stay time with a predetermined value set in advance is provided.
[0009]
According to this configuration, the start of the state is detected by the logic circuit constituting the timekeeping means, for example, based on a combination of the logic signals in the state machine. When the start of the state is detected, the counting is started by the counter, and the counting of the stay time of the state is started. The count value of the counter is compared with a predetermined value by a comparator constituting the determination means. Here, since the predetermined value is the maximum value of the stay time of the state, the fact that the count value of the counter reaches the predetermined value means that the state has not transitioned to the next state within the scheduled time. Therefore, when the count value of the counter reaches a predetermined value, the output signal of the comparator indicates the result of the determination that the current state is in the hang-up state.
[0010]
An image processing apparatus according to a third aspect of the present invention provides a first storage unit (for example, a component corresponding to a memory 80 described later) for storing image data, and a second storage unit for temporarily storing the image data. (For example, a component corresponding to a memory 230 described later), and an image data generator (for example, an image data generator described later) that generates display image data from the image data stored in the second storage unit. By reading the image data stored in the first storage unit and writing the image data in the second storage unit, the image data stored in the first storage unit A data transfer unit (for example, a component corresponding to a data transfer module 210 to be described later) that transfers the image data to the second storage unit, and the data transfer unit reads image data from the first storage unit After the completion, the time is measured by the time measuring means (for example, a component corresponding to an AND circuit 212G and a counter 212H to be described later) for measuring the time during which the image data is being written to the second storage unit, and the time is measured by the time measuring means. Determining means (e.g., a component corresponding to a comparator 212J described later) for determining whether or not the data transfer unit is in a hang-up state based on the time elapsed. Reset means (for example, constituent elements corresponding to OR circuits 212A and 212B to be described later) for resetting the data transfer unit in such a case.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a configuration example of a control circuit system used in a game machine such as a pachinko machine to which the semiconductor integrated circuit according to this embodiment is applied. In the figure, a CPU (Central Processing Unit) 10 controls the progress of a series of games, and according to the development of the games, for example, the probability that an attacker of a pachinko machine is fixed in an open state for a predetermined time or a big hit occurs. It has a function to determine the probability of performing. The CPU 10 is connected with an image processing unit 20 that controls a display device (CRT) 30 and a sound source 40 that drives a speaker 50.
[0012]
The CPU 10 is connected to a ROM (Read Only Memory) 60 that stores a program related to game control. A RAM (Random Access Memory) 70 for storing temporary data generated in the course of game control is connected to the bus connecting the CPU 10, the image processing unit 20, and the sound source 40. . Further, the image processing unit 20 is connected to a ROM 80 for storing material data (image data) of a symbol to be displayed in accordance with the progress of the game and control data for display such as symbol enlargement / reduction processing. The image processing unit 20 and the ROM 80 constitute an image processing device according to the present invention. Here, the image processing unit 20 generates image data of each frame in accordance with, for example, the NTSC (National Television Systems Committee) standard, and constitutes a semiconductor integrated circuit according to the present invention. The sound source 40 complies with the MIDI (Musical Instrument Digital Interface) standard, and generates an audio signal for producing a game under the control of the CPU 10.
[0013]
FIG. 2 shows the configuration of the image processing unit 20.
As shown in FIG. 1, the image processing unit 20 functions as a state machine, and includes a CPU interface 21 including a data transfer module 210, a CRT controller 22, and an image data generation unit including a memory (RAM) 230. 23, a pattern memory interface 26, an image memory (SDRAM) 27, and a color conversion unit 28, which are connected via a bus 29. The data transfer module 210 is connected to the memory 80 via the control bus 29A and the pattern memory interface 26 and a ROM interface 800 described later, and is connected to the memory 230 via the control bus 29B and a RAM interface 231 described later. . Further, a memory (SDRAM) 25 is connected to the image data generation unit 23 via a decompression processing unit 24. The above-described CPU 10 is connected to the CPU interface 21, the display device 30 is connected to the CRT controller 22, and the memory 80 is connected to the pattern memory interface 26.
[0014]
Here, the operation of the image processing unit 20 will be briefly described. When displaying an image, the data transfer module 210 reads out image control data (program data) and compressed image data from the external memory 80 via the pattern memory interface 26 under the control of the external CPU 10. To the memory 230. That is, the control data and the image data are transferred from the memory 80 to the memory 230. The image data is decompressed (decompressed) by the decompression processing unit 24 and stored in the memory 25.
[0015]
The image data generating unit 23 reads out the image data from the memory 25, performs processing in accordance with the control data stored in the memory 230, generates one frame of display image data, and transfers this to the image memory 27 via the bus 29. Write to. The display image data written in the image memory 27 is color-converted by the color conversion unit 28 into RGB image signals and output to the display device 30. As described above, the image processing unit 20 functions as a state machine under the control of the CPU 10 to sequentially execute the read operation and the write operation, and causes the display device 30 to display an image.
[0016]
Next, FIG. 3 shows a configuration of the data transfer module 210. The data transfer module 210 is for transferring data read from the memory 80 to the memory 230 in the image data generating unit 23 at an appropriate timing, and includes a FIFO 211, a FIFO controller 212, address counters 213, 215, It comprises comparators 214 and 216. The data transfer module 210 is connected to the above-described memory 80 via the ROM interface 800, and is connected to the above-described memory 230 via the RAM interface 231. In FIG. 3, the pattern memory interface 26 shown in FIG. 2 existing between the data transfer module 210 and the ROM interface 800 is omitted.
[0017]
Here, the read data RDAT is input from the ROM interface 800 to the FIFO 211, and the write data WDAT is output from the FIFO 211 to the RAM interface 231. The read data RDAT is control data or image data read from the memory 80. The write data WDAT has the same contents as the read data RDAT, and is control data or image data transferred by the data transfer module 210 and written into the memory 230. A read request signal RREQ is output from the FIFO controller 212 to the ROM interface 800, and a read data timing signal RDTIM is input to the FIFO controller 212 from the ROM interface. On the other hand, a write request signal WREQ is output from the FIFO controller 212 to the RAM interface 231, and a write acknowledge signal WACK is input from the RAM interface 231 to the FIFO controller 212.
[0018]
A read acknowledge signal RACK is input from the ROM interface 800 to the address counter 213, and a read address signal RADR is output from the address counter 213 to the ROM interface 800. The above-described read address RADR is input to the comparator 214, and the read-end signal REND is output from the comparator 214 to the ROM interface 800. On the other hand, the above-mentioned write acknowledge signal WACK is input to the address counter 215, and the write address signal WADR is output from the address counter 215 to the RAM interface 231. The above-described write address WADR is input to the comparator 216, and the comparator 216 outputs a write end signal WEND to the RAM interface 231.
[0019]
Here, the operation of the data transfer module 210 will be described.
When transferring data (image data / control data), the FIFO controller 212 outputs a read request signal RREQ to the ROM interface 800. In response to this, the ROM interface 800 outputs a read acknowledge signal RACK to the address counter 213, and the address counter 213 sequentially generates the read address RADR using this as a trigger. At this time, the read data timing signal RDTIM is output from the ROM interface 800 in response to the read acknowledge signal RACK, and the read data RDAT is written to the FIFO 211 at the timing specified by the read data timing signal RDTIM. Thus, the read operation is performed, and the data is transferred from the memory 80 to the FIFO 211 via the ROM interface 800 as the read data RDAT. The comparator 214 sequentially compares the read address RADR and the read end address REA, and when they match, outputs a read end signal REND. Then, when the read address RADR matches the read end address REA and all data is transferred to the FIFO 211, a series of read operations ends.
[0020]
On the other hand, the FIFO controller 212 outputs a write request signal WREQ to the RAM interface 231. In response to this, the RAM interface 231 outputs a write acknowledge signal WACK, and using this as a trigger, the address counter 215 outputs a write address signal WADR, and then increments. As a result, a write operation is performed, and data is transferred as write data WDAT from the FIFO 211 to the memory 230 via the RAM interface 231. The comparator 216 successively compares the write address signal WADR and the write end address WEA, and when the write address signal WADR matches the write end address WEA, outputs a write end signal WEND and ends a series of write operations.
[0021]
Next, the FIFO controller 212 will be described.
FIG. 4 shows a part of the configuration of the FIFO controller 212. In this configuration, portions related to the present invention are extracted, and as shown in the figure, OR circuits 212A and 212B, RS flip-flops (FF) 212C, 212D and 212K, and a signal generator 212E. , 212F, an AND circuit 212G, a counter 212H, and a comparator 212J.
[0022]
This will be specifically described. The above-described read end signal REND and write end signal WEND are input to the OR circuits 212A and 212B, respectively, and a hang-up flag HFLG described later is commonly input to these OR circuits. Output signals of the OR circuits 212A and 212B are respectively input to reset terminals of the flip-flops 212C and 212D, and a start signal STR supplied from the CPU 10 is commonly input to each set terminal.
The output signal of the flip-flop 212C is supplied to the signal generation unit 212E as a read timing signal RTIM, and the output signal of the flip-flop 212D is supplied to the signal generation unit 212F as a write timing signal WTIM. Here, the signal generation unit 212E generates the read request signal RREQ according to the read timing signal RTIM and the presence or absence of an empty area in the FIFO 211 or the ratio of the area where data is written, and the signal generation unit 212F A write request signal WREQ is generated according to the write timing signal WTIM and the presence or absence of data in the above-described FIFO 211 or the ratio of the area where data is written.
[0023]
The AND circuit 212G has a negative logic input terminal and a positive logic input terminal. The read timing signal RTIM is input to the negative logic input terminal, and the write timing signal WTIM is input to the positive logic terminal. In this embodiment, the AND circuit 212G functions as a decoder, and functions as detecting means for detecting a state from the end of the read operation of the memory 80 to the end of the write operation of the memory 230. .
The output signal of the AND circuit 212G is commonly input to the carry-in terminal (Ci) and the negative reset terminal (RN) of the counter 212H. The counter 212H is configured to start counting when a logical value “1” is input as an output signal of the AND circuit 212G, and to reset the count value when a logical value “0” is input. In this embodiment, the counter 212H functions as a clock unit that counts the stay time of the state detected by the AND circuit 212G.
[0024]
An output signal (count value CNT) of the counter 212H is provided to one input terminal of a comparator 212J, and a predetermined value TMAX is supplied to the other input terminal of the comparator 212J. The predetermined value TMAX is the maximum time of the state from the end of the read operation from the memory 80 to the end of the write to the memory 230, and is a value preset as the maximum value of the stay time of such a state. It is. The comparator 212J outputs a signal of a logical value “1” as the hang-up flag HFLG when the count value CNT reaches a predetermined value TMAX. As a result, the comparator 212J functions as a judging means for judging whether or not the vehicle is in the hang-up state from the stay time measured by the counter 212H, and the result of the judgment is output as the hang-up flag HFLG.
[0025]
The hang-up flag HFLG output from the comparator 212J is provided to the above-mentioned OR circuits 212A and 212B. In this embodiment, the OR circuits 212A and 212B function as reset means for resetting the state machine when the hang-up flag HFLG output from the comparator 212J indicates that the hang-up state is established. The hang-up flag HFLG is provided to a set terminal of the RS flip-flop 212K, and a reset signal from the CPU 10 is provided to its reset terminal. The output signal of the flip-flop 212K is supplied to the CPU 10 as an error flag EFLG.
[0026]
Hereinafter, the operation of this embodiment will be described along the flow chart shown in FIG. 6 with reference to the waveform chart shown in FIG.
In the initial state, the image processing unit 20 is in an idle state, and keeps the idle state until an event occurs (step S1; NO). From this idle state, an event occurs in accordance with the progress of the game, and when a series of operations is started under the control of the CPU 10 (step S2; YES), the data transfer module 210 in the image processing unit 20 returns to FIG. The flip-flops 212C and 212D shown are set by the start signal STR from the CPU 10, and as shown in FIG. 5, both the read timing signal RTIM and the write timing signal WTIM are set to the logical value "1".
[0027]
Subsequently, the signal generation unit 212E sets the logical value “1” as the read request signal RREQ if an empty area exists in the FIFO 211 and the condition that the read timing signal RTIM is the logical value “1” is satisfied. Output. On the other hand, if data exists in the FIFO 211 and the condition that the write timing signal WTIM is a logical value “1” is satisfied, the signal generation unit 212F outputs a logical value “1” as the write request signal WREQ. . In response to this, the ROM interface 800 and the RAM interface 231 output the read acknowledge signal RACK and the write acknowledge signal WACK, respectively, and the read operation of the memory 80 and the write operation of the memory 230 start (step S3).
[0028]
Subsequently, the logical value “1” is output from the comparator 214 as the read end signal REND, and when the operation of reading the control data from the memory 80 ends (step S4; YES), only the write operation to the memory 230 continues. (Step S5). Here, when the logical value “1” is input to the OR circuit 212A shown in FIG. 4 as the read end signal REND, the flip-flop 212C is reset by the output signal of the OR circuit 212A, and the logical value is read as the read timing signal RTIM. The value "0" is output. At this time, since the logical value “0” is held as the write end signal WEND and the flip-flop 212D is not reset, the flip-flop 212D keeps the set state, and the logical value “1” is kept as the write timing signal WTIM. . Therefore, the logical product circuit 212G outputs a logical value “1” as an output signal, thereby detecting that the current state of the state machine is a state where the read operation has been completed and the write operation has not been completed. Is done.
[0029]
When a logical value “1” is output as an output signal of the logical product circuit 212G, the counter 212H starts a count operation by using this as a trigger, and starts measuring the stay time in the current state. Here, under normal circumstances, the write operation also ends within a predetermined time after the end of the above-described read operation, and a logical value “1” is output as the write end signal WEND. As a result, the flip-flop 212D is reset and outputs a logical value “0” as the write timing signal WTIM, and the signal processing unit 212F that receives the output outputs a logical value “0” as the write request signal WREQ. Further, the AND circuit 212G outputs a logical value “0”, and the counter 212H stops counting. Thus, a series of write operations is completed, and the state machine shifts to the next state.
[0030]
On the other hand, if, for example, the flip-flop 212D is fixed to the set state due to noise during the write operation, the write timing signal WTIM is fixed at the logical value “1”, and the write request signal WREQ is maintained at the logical value “1”. You. Therefore, apparently, the write operation is not completed, and a hang-up state occurs. In this case, since the counter 212H starts counting from the time when the logical product circuit 212G outputs the logical value "1" (the time when the read operation ends), the write timing signal WTIM maintains the logical value "1". If so, the count is continued, and the stay time in the current state is measured.
[0031]
When the count value CNT reaches the predetermined value TMAX ("N" shown in FIG. 5), the comparator 212J outputs a logical value "1" as the hang-up flag HFLG (step S6; YES). In this case, the output signals of the OR circuits 212A and 212B shown in FIG. 4 are forcibly set to the logical value "1" by the hang-up flag HFLG, so that the flip-flops 212C and 212D for inputting this to the reset terminal are forced. Reset. As a result, as shown in FIG. 5, the read timing signal RTIM and the write timing signal WTIM are both set to the logical value “0” and the state is returned to the initial state. As a result, the state machine returns from the hang-up state, and a series of control operations is restarted from the first state. The hang-up flag HFLG is taken into the flip-flop 212K and supplied to the CPU 10 as an error flag EFLG. Thereby, the CPU 10 can recognize later that the recovery from the hang-up has been performed inside the image processing unit 20, and reflect it in the subsequent control as necessary.
[0032]
If the write operation (step S5) does not fall into the hang-up state, the write timing signal is output from the flip-flop 212D before the counter value CNT reaches the predetermined value TMAX ("N" shown in FIG. 5). Since the logical value “0” is output as WTIM, the output signal of the AND circuit 212G is set to the logical value “0”, and the count value CNT of the counter 212H is reset. Therefore, in this case, the hang-up flag HFLG is maintained at the logical value "0", the write request signal WREQ becomes the logical value "0" in response to the normal write end signal WEND, and the write operation ends normally (step S1). S7; YES). After that, the state of the state machine becomes an idle state (step S1), and waits for the occurrence of a new event.
[0033]
As described above, according to this embodiment, the write operation time of the memory 230 (the stay time of the write state) is measured, so that it is possible to grasp the hang-up of the FIFO controller 212 in this write operation. Thus, the FIFO controller 212 can be reset. Therefore, even if the FIFO controller 212 constituting the state machine is in a hang-up state during the play of the gaming machine, it is possible to return from the hang-up state and avoid a situation in which the game is stopped due to the hang-up. It becomes possible.
Further, in the above-described embodiment, the configuration is made to deal with the hang-up in the write operation. However, the present invention is not limited to this, and it may be possible to deal with the hang-up in any state.
[0034]
【The invention's effect】
As described above, according to the semiconductor integrated circuit of the present invention, the state of the state machine is detected and the staying time of the state is counted, and whether or not the state machine is in the hang-up state is determined based on the counted staying time. Since the reset is performed by judging whether or not it is possible, it is possible to return from the hang-up state by itself irrespective of software reset.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example of a control system of a gaming machine to which a semiconductor integrated circuit according to an embodiment of the present invention is applied.
FIG. 2 is a block diagram illustrating a configuration of an image processing unit configured as a semiconductor integrated circuit according to the embodiment of the present invention;
FIG. 3 is a block diagram showing a configuration of a data transfer module according to the embodiment of the present invention.
FIG. 4 is a block diagram showing a configuration of a FIFO controller according to the embodiment of the present invention.
FIG. 5 is a waveform chart for explaining an operation of the FIFO controller according to the embodiment of the present invention;
FIG. 6 is a flowchart illustrating a flow of an operation of the image processing unit according to the embodiment of the present invention.
[Explanation of symbols]
Reference Signs List 20 image processing unit, 21 CPU interface, 22 CRT controller, 23 image data generation unit, 24 decompression processing unit, 25 memory, 26 pattern memory, 27 image memory, 28 color conversion unit, 29 ... bus, 29A, 29B ... control bus, 80 ... memory, 212 ... FIFO controller, 212A, 212B ... logical sum circuit, 212C, 212D, 212K ... flip-flop, 212E, 212F ... signal generator, 212G ... logical product circuit 212H: counter, 212J: comparator.

Claims (3)

In a semiconductor integrated circuit configured to function as a state machine,
Detecting means for detecting a state of the state machine;
Clocking means for clocking the stay time of the state detected by the detecting means,
Judgment means for judging whether or not the state machine is in a hang-up state from the stay time measured by the time measurement means,
Resetting means for resetting the state machine when a result of the judgment by the judging means indicates a hang-up state;
A semiconductor integrated circuit comprising: The timing means includes a logic circuit for detecting the start of the state of the state machine, and a counter that starts counting with an output signal of the logic circuit as a trigger,
2. The semiconductor integrated circuit according to claim 1, wherein the determination unit includes a comparator that compares a count value of the counter with a predetermined value set as a maximum value of the stay time. A first storage unit for storing image data;
An image data generation unit having a second storage unit for temporarily storing the image data, and generating display image data from the image data stored in the second storage unit;
Data transfer for transferring the image data stored in the first storage unit to the second storage unit by reading out the image data stored in the first storage unit and writing the image data in the second storage unit Department and
After the data transfer unit finishes reading the image data from the first storage unit, a timing unit that counts the time during which the image data is being written to the second storage unit;
Determining means for determining whether or not the data transfer unit is in a hang-up state from the time measured by the time measuring means;
Resetting means for resetting the data transfer unit when the result of the judgment by the judging means indicates a hang-up state;
An image processing apparatus comprising:

Images