JP2002351696A - Debugging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a debugging device preventing overflows in a trace buffer. SOLUTION: A judgment circuit 21 detects a trace event generated in a debugging object 1 and the trace buffer 22 stores the value of internal data 13 as trace data when the trace event is detected by the judgment circuit 21. A trace data selection circuit 23a is provided with a register inside and reads the trace data at a position specified by the register from the trace buffer 22 and outputs them to an ICE(in-circuit emulator) 3. Thus, the ICE acquires only desired trace data by writing the value to the register and the overflows in the trace buffer are prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CPU (Central
The present invention relates to a debugging device used for debugging of a processing unit and software, and more particularly to a debugging device that prevents a trace buffer from overflowing due to occurrence of a plurality of trace events.

[0002]

2. Description of the Related Art In recent years, CPUs have been widely used in information devices such as personal computers and home electric appliances. ICE (In-Circuit Emulator) is used for debugging hardware and software in the development of the CPU itself and in the development of information equipment and home appliances equipped with the CPU. Generally, a debugging device is connected between the debug target and the ICE to perform debugging.

FIG. 15 is a block diagram showing a schematic configuration of a system using a conventional debugging device. This system includes a debug target 101, a debug device 102,
ICE103. FIG. 15 shows a case where the debug target 101 is a CPU core including a CPU 111 and an internal bus 112.

The debug device 102 includes a determination circuit 121 for determining the occurrence of a trace event, a trace buffer 122 for storing trace data, and a clock signal 126.
And a selector 125 that selects and outputs m-bit trace data output from the trace buffer 122 according to the value of the counter 123.
And

[0005] The determination circuit 121 monitors the signal output from the CPU 111 and the internal bus 112, and upon detecting coincidence with a predetermined trace event, a trace buffer write enable signal (hereinafter abbreviated as WE signal). )
A high level (hereinafter, referred to as an H level) is output to 124. For example, when a trace event occurs when data is read from a predetermined address while CPU 111 is executing a program, such a condition is set in determination circuit 121. When detecting that the set condition matches the state of the internal bus 112 or the like, the determination circuit 121 outputs an H level to the WE signal 124.

[0006] The trace buffer 122 stores the WE signal 12
When 4 goes to the H level, the values of the internal data 113 output from the debug target 101 are sequentially captured. The internal data 113 includes a data bus, an address bus, a control signal, an interrupt signal, and the like in the debug target 101. As described later, the trace buffer 122 stores the internal data 1
The value of 13 is taken in N times. That is, when a trace event occurs once, the value of the internal data 113 is fetched N times as m-bit data.

When the WE signal 124 goes high, the counter 123 is reset. The counter 123 has I
The clock signal 126 is input in synchronization with the timing at which the CE 103 reads the trace data stored in the trace buffer 122. The counter 123 counts the clock signal 126 and outputs the count value to the selector 125.
Output to The clock signal 126 may be generated by the ICE 103 in synchronization with the timing of reading the trace data, or may be generated by the debug device 102.

[0008] The selector 125 operates according to the count value output from the counter 123 to the trace buffer 122.
Select the trace data output from the
Output to The ICE 103 reads m-bit trace data N times in synchronization with the clock signal 126 to read trace data corresponding to one trace event.

FIG. 16 is a diagram showing a configuration example of the trace buffer 122. This trace buffer 122
It has a capacity to store trace data corresponding to the number of trace events, that is, a capacity to store N pieces of m-bit data.

FIG. 17 is a diagram showing the timing at which the ICE 103 reads trace data from the trace buffer 122. As shown in FIG. 17, the ICE 103 reads the trace data (data 1 to data N) output from the selector 125 N times in synchronization with the clock signal 126 and acquires the trace data corresponding to one trace event. .

[0011]

However, in the above-described conventional debugging apparatus 102, when a trace event occurs, trace data corresponding to the trace event is stored in the trace buffer 122, and the ICE 103 is stored in the trace buffer 122. If another trace event occurs before all the trace data has been read out, the counter 123 is reset and trace data corresponding to another trace event is sequentially written into the trace buffer 122. Therefore, the trace buffer 122
In this case, an overflow occurs and the count value of the counter 123 is reset, so that the ICE 103 cannot read the trace data corresponding to the first trace event.

The present invention has been made to solve the above problems, and a first object of the present invention is to provide a debugging device capable of preventing occurrence of overflow in a trace buffer.

A second object is to provide a debugging device capable of acquiring only desired trace data from trace data stored in a trace buffer.

[0014]

According to a first aspect of the present invention, there is provided a debugging device, comprising: detecting means for detecting a trace event occurring in a debug target; and detecting a trace event when the detecting means detects the trace event. Storage means for storing a value as trace data, designating means for designating an arbitrary position of the trace data stored by the storage means, and storage means according to the position of the trace data designated by the designating means And selecting means for selecting and outputting the trace data stored in the.

The selection means selects and outputs the trace data stored in the storage means in accordance with the position of the trace data designated by the designation means. Can be obtained.

According to a second aspect of the present invention, there is provided the debugging device according to the first aspect, wherein the storage means includes a first storage means for storing a value of internal data as trace data; A second storage unit for transferring and storing the trace data stored in the storage unit, wherein the selection unit stores the trace data in the second storage unit according to the position of the trace data specified by the specification unit. The selected trace data is selected and output.

Since the second storage means transfers and stores the trace data stored in the first storage means, even if another trace event occurs, the trace data corresponding to the previous trace event can be obtained. Can be prevented from being lost,
Trace data can be prevented from overflowing.

According to a third aspect of the present invention, in the debugging apparatus according to the second aspect, the selecting means selects an arbitrary one-bit data from the trace data stored in the second storing means. And output.

Therefore, I connected to the debug device
The CE can acquire desired 1-bit trace data from the trace data in one cycle.
It is possible to further prevent overflow of trace data.

A debug device according to a fourth aspect is the debug device according to any one of the first to third aspects, further including an operation unit for performing an operation on the trace data stored in the storage unit.

Since the arithmetic means performs an arithmetic operation on the trace data stored in the storage means, for example, by adding all the predetermined bits of the trace data and outputting the result as parity bits, the ICE can detect missing trace data or the like. Becomes possible.

According to a fifth aspect of the present invention, there is provided a debugging device, comprising: detecting means for detecting a trace event occurring in a debug target; and when the detecting means detects the trace event, storing a value of internal data as trace data. Storage means for performing the counting, a counting means for counting the trace events detected by the detection means, and a selection for selecting and outputting the trace data stored in the storage means in accordance with the counting result by the counting means. And a re-execution requesting means for requesting the debug target to re-execute a program from a predetermined address when a trace event is detected by the detection means.

The re-execution requesting unit requests the debug target to re-execute the program from a predetermined address when the detecting unit detects the trace event, so that the trace data corresponding to one trace event is transmitted a plurality of times. And can be stored in the trace buffer.

According to a sixth aspect of the present invention, in the debugging apparatus of the fifth aspect, the storage means includes a first storage means for storing a value of internal data as trace data; A second storage unit for transferring and storing the trace data stored in the storage unit, wherein the selection unit converts the trace data stored in the second storage unit in accordance with the counting result by the counting unit. Select and output.

Since the second storage means transfers and stores the trace data stored in the first storage means, even if another trace event occurs, the trace data corresponding to the previous trace event can be obtained. Can be prevented from being lost,
Trace data can be prevented from overflowing.

According to a seventh aspect of the present invention, there is provided a debugging device, comprising: first detecting means for detecting a trace event occurring in a debug target; and when the first detecting means detects the trace event, the internal data of the internal data is detected. Storage means for storing a value as trace data; designation means for designating an arbitrary position of the trace data stored by the storage means; and counting means for counting the number of times of reading the trace data stored in the storage means. Counting means, second detection means for detecting overflow in the storage means,
When the overflow is not detected by the second detecting means, the counting result of the counting means is selected. When the overflow is detected by the second detecting means, the position of the trace data specified by the specifying means is selected. And a second selection unit for selecting and outputting the trace data stored in the storage unit according to the output from the first selection unit.

The second selecting means selects and outputs the trace data stored in the storing means in accordance with the output from the first selecting means. The connected ICE can arbitrarily designate and read trace data that has not yet been read.

[0028] According to an eighth aspect of the present invention, in the debugging apparatus of the seventh aspect, the storage means includes: first storage means for storing the value of internal data as trace data; Second storage means for transferring and storing the trace data stored in the storage means, wherein the second selection means responds to an output from the first selection means,
The trace data stored in the second storage means is selected and output.

Since the second storage means transfers and stores the trace data stored in the first storage means, even if another trace event occurs, the trace data corresponding to the previous trace event can be obtained. Can be prevented from being lost,
Trace data can be prevented from overflowing.

According to a ninth aspect of the present invention, there is provided a debugging device, comprising: detecting means for detecting a trace event occurring in a debug target; first counting means for counting the trace events detected by the detecting means; A storage unit for storing the value of the internal data as trace data when the count result of the first counting unit reaches a predetermined value, and a second unit for counting the number of times the trace data stored in the storage unit is read. And a selection means for selecting and outputting the trace data stored in the storage means according to the counting result by the second counting means.

The storage means stores the value of the internal data as trace data when the result of counting by the first counting means has reached a predetermined value. Therefore, even when trace events frequently occur, the trace data is stored. Can be prevented from overflowing.

[0032]

(Embodiment 1) FIG. 1 is a block diagram showing a schematic configuration of a system using a debugging device according to Embodiment 1 of the present invention. This system is
A debug target 1, a debug device 2 a, and an ICE 3 are included. Note that the case of the CPU core including the CPU 11 and the internal bus 12 is shown as the debug target 1,
It is not limited to this.

The debug device 2a selects a determination circuit 21 for determining the occurrence of a trace event, a trace buffer 22 in which trace data is stored, and trace data stored in the trace buffer 22, and outputs the selected data as 1-bit data. And a trace data selection circuit 23a.

The judging circuit 21 monitors the signal output from the CPU 11 and the internal bus 12. When detecting a coincidence with a preset trace event, the WE signal 24
Output the H level. For example, when a trace event is generated when a predetermined interrupt occurs while the CPU 11 is executing a program, such a condition is set in the determination circuit 21. When determining that the set condition matches the state of the internal bus 12 or the like, the determination circuit 21 outputs an H level to the WE signal 24.

When the WE signal 24 goes high, the trace buffer 22 sequentially takes in the value of the internal data 13 output from the debug target 1. The internal data 13 includes a data bus, an address bus, a control signal, an interrupt signal, and the like in the debug target 1. Trace buffer 2
2 indicates that when a trace event occurs once, the internal data 13
Is fetched N times as m-bit data.

FIG. 2 is a block diagram for explaining details of the trace data selection circuit 23a shown in FIG. The trace data selection circuit 23a includes a secondary trace buffer 231 having a capacity of m × N bits and a register 2 in which an arbitrary value (bit position) is set by the ICE3.
And a selector 23 for selecting and outputting 1-bit data corresponding to the bit position set in the register 232
3a.

The secondary trace buffer 231 has the same capacity of m × N bits as the trace buffer 22, but has a configuration in which N m-bit data are arranged in a horizontal line as shown in FIG. Thus, m × N bits of data are output at one time by one reading. The values written to the trace buffer 22 are sequentially written to the secondary trace buffer 231 in synchronization with the timing at which the value of the internal data 13 is written to the trace buffer 22.

The selector 233a selects 1-bit data corresponding to the bit position set in the register 232 from the m × N-bit data output from the secondary trace buffer 231 and outputs it to the ICE3.

The value of the register 232a is set by ICE3. The ICE 3 can select and read 1-bit data at an arbitrary bit position from m × N-bit data by writing an arbitrary value to the register 232a. As described above, the ICE 232 can read 1-bit data at an arbitrary bit position from m × N-bit data in one cycle.

The debug device according to the present embodiment provides 1-bit data from the values of internal data 13, for example,
Predetermined 1-bit data of the data bus and the value of the interrupt signal,
Is effective when it is possible to determine the trace event simply by reading out.

As described above, according to the debugger of this embodiment, when the value of internal data 13 is written to trace buffer 22, the value of internal data 13 is also written to secondary trace buffer 231. Output 1-bit data corresponding to an arbitrary bit position set in register 232 to ICE3.
No. 3 can acquire desired 1-bit data in one cycle. Therefore, even when trace events occur frequently, the ICE 3 can acquire desired data without causing an overflow in the trace buffer 22.

(Embodiment 2) FIG. 4 is a block diagram showing a schematic configuration of a system using a debugging device according to Embodiment 2 of the present invention. This system includes a debug target 1, a debug device 2b, and an ICE3. Since debug target 1 and ICE 3 are the same as those described in the first embodiment, detailed description will not be repeated.

The debug device 2b selects a determination circuit 21 for determining the occurrence of a trace event, a trace buffer 22 for storing trace data, and a trace data stored in the trace buffer 22, and outputs the selected data as m-bit data. And a trace data selection circuit 23b.
Since determination circuit 21 and trace buffer 22 are the same as those described in the first embodiment, detailed description will not be repeated.

FIG. 5 is a block diagram for explaining details of the trace data selection circuit 23b shown in FIG. The trace data selection circuit 23b includes a secondary trace buffer 234 having a capacity of m × N bits, a register 232 in which an arbitrary value (m-bit data position) is set by the ICE 3, and a value set in the register 232. Selector 2 for selecting and outputting m-bit data corresponding to
33b.

The secondary trace buffer 234 has the same capacity of m × N bits as the trace buffer 22.
Arbitrary m-bit data is output from N m-bit data. The trace buffer 2 is stored in the secondary trace buffer 234 in synchronization with the timing at which the value of the internal data 13 is written to the trace buffer 22.
The values written to 2 are sequentially written.

The selector 233b selects m-bit data corresponding to the position set in the register 232 from the N m-bit data output from the secondary trace buffer 234, and outputs the selected data to the ICE3.

The ICE 3 can select and read m-bit data at an arbitrary position from N m-bit data by writing an arbitrary value to the register 232. As described above, the ICE 3 can read m-bit data at an arbitrary position from N m-bit data in one cycle.

The debugging device according to the present embodiment provides m-bit data, eg,
This is effective when a trace event can be determined only by reading predetermined m-bit data on the data bus.

As described above, according to the debugging device of the present embodiment, when the value of internal data 13 is written to trace buffer 22, the value of internal data 13 is also written to secondary trace buffer 234. , M-bit data at an arbitrary position set in the register 232
Since the data is output to E3, ICE3 can acquire desired m-bit data in one cycle. Therefore, even when trace events occur frequently, the ICE 3 can acquire desired data without causing an overflow in the trace buffer 22.

(Embodiment 3) FIG. 6 is a block diagram showing a schematic configuration of a system using a debugging device according to Embodiment 3 of the present invention. This system includes a debug target 1, a debug device 2c, and an ICE 3. Since debug target 1 and ICE 3 are the same as those described in the first embodiment, detailed description will not be repeated.

The debug device 2c selects a determination circuit 21 for determining the occurrence of a trace event, a trace buffer 22 for storing trace data, and a trace data stored in the trace buffer 22, and outputs the selected data as m-bit data. And a trace data selection circuit 23c.
The trace data selection circuit 23c outputs a repeat signal 25 to the CPU 11 and performs processing while requesting re-execution of a program from a predetermined address. The determination circuit 21 and the trace buffer 22 are the same as those in the first embodiment.
Since they are the same as those described above, detailed description will not be repeated.

FIG. 7 is a block diagram for explaining details of the trace data selection circuit 23c shown in FIG. The trace data selection circuit 23c includes a secondary trace buffer 234 having a capacity of m × N bits and a WE signal 2
Counter 235 that counts the number of times that 4 goes to H level
A selector 233 for selecting the trace data stored in the secondary trace buffer 234 according to the count value of the counter 235; a comparison circuit 236 for comparing the count value of the counter 235 with a predetermined value N; And an AND circuit 237 for outputting a repeat signal to the CPU 11 in response to the output signal.

The secondary trace buffer 234 has the same capacity of m × N bits as the trace buffer 22.
Arbitrary m-bit data is output from N m-bit data. The trace buffer 2 is stored in the secondary trace buffer 234 in synchronization with the timing at which the value of the internal data 13 is written to the trace buffer 22.
The values written to 2 are sequentially written.

The comparison circuit 236 compares the count value of the counter 235 with a predetermined value N, and outputs a low level (hereinafter referred to as L level) when the count value is different from the predetermined value N, and outputs the count value. And when the predetermined value N is the same, an H level is output.

The counter 235 counts the number of times the WE signal goes high, that is, the number of m-bit trace data stored in the trace buffer 22. Until the count value of the counter 235 reaches the predetermined value N, each time the WE signal goes high, the AND circuit 237
Outputs a high level, and the repeat signal 25 output to the CPU 11 goes high.

When the count value of the counter 235 reaches the predetermined value N, the comparator circuit 236 outputs an H level, and the counter 235 is reset. After the counter 235 is reset, writing of trace data by a new trace event becomes possible.

When the CPU 11 receives the repeat signal,
Re-execute the program from the predetermined address. As described above, it is necessary to write m × N-bit trace data into the trace buffer 22 by one occurrence of a trace event. However, only one m-bit trace data is written by one write to the trace buffer 22. I can't. Therefore, a repeat signal is output to the CPU 11 N times, and the same process is repeated N times to obtain m × N-bit trace data.

The selector 233 selects one of N m-bit data output from the secondary trace buffer 234 from
The m-bit data corresponding to the count value of the counter 235 is selected and output to the ICE3. The ICE 3 can acquire trace data corresponding to one trace event by reading the m-bit data output from the selector 233 N times.

As described above, according to the debugger of the present embodiment, the trace data is written to the trace buffer 22 while the repeat signal is output to the CPU 11 N times. The ICE 3 can obtain desired trace data without causing an overflow in the trace buffer 22.

(Embodiment 4) FIG. 8 is a block diagram showing a schematic configuration of a system using a debugging device according to Embodiment 4 of the present invention. This system includes a debug target 1, a debug device 2d, and an ICE3. Since debug target 1 and ICE 3 are the same as those described in the first embodiment, detailed description will not be repeated.

The debug device 2d selects a judgment circuit 21 for judging the occurrence of a trace event, a trace buffer 22 for storing trace data, and a trace data stored in the trace buffer 22, and outputs the selected data as m-bit data. And a trace data selection circuit 23d.

FIG. 9 is a block diagram for explaining details of the trace data selection circuit 23d shown in FIG. The trace data selection circuit 23d includes a secondary trace buffer 234 having a capacity of m × N bits, a register 232 in which an arbitrary value (m-bit data position) is set by the ICE 3, and the WE signal 24 being set to the H level. A counter 235 for counting the number of times, a selector 233 for selecting the trace data stored in the secondary trace buffer 234 according to the count value of the counter 235, and a comparison circuit for comparing the count value of the counter 235 with a predetermined value N 236, an overflow detection circuit 239 for detecting an overflow of the trace buffer 22, and a register 23 according to a signal output from the overflow detection circuit 239.
2, a selector 238 for selecting and outputting the value stored in the counter 2 or the count value of the counter 235, an OR circuit 240 for masking the clock signal 26 input to the counter 235 according to the output signal of the comparator 236, and a comparator 23
6 and an AND circuit 241 that outputs a reset signal to the counter 235 in response to the output signal of the counter 235.

The secondary trace buffer 234 has the same m × N-bit capacity as the trace buffer 22.
Arbitrary m-bit data is output from N m-bit data. The trace buffer 2 is stored in the secondary trace buffer 234 in synchronization with the timing at which the value of the internal data 13 is written to the trace buffer 22.
The values written to 2 are sequentially written.

The comparison circuit 236 compares the count value of the counter 235 with a predetermined value N, outputs an L level when the count value is different from the predetermined value N, and outputs an L level when the count value is equal to the predetermined value N. Output an H level.

The counter 235 counts the number of clock signals 26. The comparison circuit 236 is a counter 2
After detecting that the count value of 35 coincides with the predetermined value N and outputting the H level, when the WE signal 24 goes to the H level, the H level is output from the AND circuit 241 and the counter 235 is reset.

The overflow detection circuit 239 detects an overflow by referring to the count value of the counter 235. When the overflow detection circuit 239 detects no overflow, the selector 238 sets the counter 235
Is controlled to select and output the count value of.
The overflow detection circuit 239 controls the selector 238 to select and output a value stored in the register 232 when an overflow is detected.

The selector 233 selects the trace data stored in the secondary trace buffer 234 according to the value output from the selector 238, and outputs the selected data to the ICE3.

The ICE 3 reads data in synchronization with the clock signal 26 when no overflow occurs. And when an overflow occurs,
The trace data is read from the secondary trace buffer 234 while writing a value to the register 232. In this way, even if an overflow occurs, the register 232
, The trace data which has not been read out can be sequentially read out.

FIG. 10 is a block diagram for explaining details of overflow detection circuit 239 shown in FIG. The overflow detection circuit 239 includes a comparison circuit 2391 that compares the count value of the counter 235 with a predetermined value N,
An AND circuit 2392 that masks the WE signal 23 in accordance with a signal output from the comparison circuit 2391;
Holding circuit 2 for holding and outputting the signal output from 91
393.

The comparison circuit 2391 compares the count value of the counter 235 with a predetermined value N, and compares the count value with the predetermined value N.
If H is different, the H level is output. Further, the comparison circuit 2391 calculates the count value of the counter 235 and the predetermined value N
If L is the same, L level is output.

The AND circuit 2392 is provided with a comparison circuit 2391
The WE signal 24 goes high when the signal output from the second is low, that is, when another trace event occurs before the ICE 3 reads out all the trace data stored in the secondary trace buffer 234. Determines that an overflow has occurred, and outputs an H level signal to holding circuit 2393. In addition, the AND circuit 2392 includes the comparison circuit 2
When the WE signal is at the H level when the signal output from the 391 is at the H level, that is, when another trace event occurs after the ICE 3 has read all the trace data stored in the secondary trace buffer 234, , It is determined that no overflow has occurred and the holding circuit 2393
Output the L level.

The holding circuit 2393 includes an AND circuit 2392
The output (H level) of comparison circuit 2391 is held at the rise of the signal output from, that is, when an overflow occurs. ICE3 detects that an overflow has occurred by reading the signal output from holding circuit 2393. When detecting that an overflow has occurred, the ICE 3 sequentially reads the trace data stored in the secondary trace buffer 234 while setting a value in the register 232.

As described above, according to the debugging device of the present embodiment, the trace data output according to the value of counter 235 is read out until the overflow occurs, and register 23 is read after the overflow occurs.
Since the trace data is read while sequentially setting the value to 2, even if another trace event occurs and an overflow occurs, the trace data corresponding to the previous trace event can be read. This makes it possible to prevent a problem that trace data cannot be read due to an overflow.

(Embodiment 5) FIG. 11 is a block diagram showing a schematic configuration of a system using a debugging device according to Embodiment 5 of the present invention. This system includes a debug target 1, a debug device 2e, and an ICE3.
Note that the debug target 1 and the ICE 3 are the same as those in the first embodiment.
, The detailed description will not be repeated.

The debug device 2e counts the number of times that the determination circuit 21 for determining the occurrence of the trace event, the trace buffer 22 for storing the trace data, and the WE signal 24 output from the determination circuit 21 become H level. When the count value reaches a predetermined value, the trace count circuit 27 outputs the WE2 signal 31. When the trace count circuit 27 outputs the WE2 signal 31,
And a selector 30 for selecting and outputting the trace data stored in the trace buffer 22 in accordance with the count value of the counter 29.

FIG. 12 is a block diagram for describing details of trace count circuit 27 shown in FIG. The trace count circuit 27 includes a counter 271 for counting the number of times that the WE signal 24 is at the H level, a register 272 for setting a cycle of a trace event for acquiring trace data, and a count value of the counter 271 and a register 272. And a comparison circuit 273 that compares the calculated value with the output value and outputs the WE2 signal 31.

An arbitrary value is written to register 272 by ICE3. The comparison circuit 273 includes a counter 271
Is compared with the value set in the register 272, and if the count value is different from the set value, the L level is output. If the count value matches the set value, the H level is output. . When the count value matches the set value, an H level is output to the WE2 signal 31,
The counter 271 is reset.

When the H level is output to the WE2 signal 31, the value of the internal data 13 is written into the trace buffer 22, and the counter 29 is reset to ICE.
3 starts reading trace data. Thus, the trace data corresponding to the trace event for each set value of the register 272 is stored in the trace buffer 22.

The debugging device according to the present embodiment is effective when it is necessary to obtain only trace data corresponding to a trace event of a predetermined cycle among trace events that occur frequently.

As described above, according to the debugging device of the present embodiment, only the trace data corresponding to the trace event for each set value of the register 272 is written in the trace buffer 22. It is possible to acquire only trace data corresponding to a trace event of a predetermined cycle among trace events occurring frequently. Therefore, even when trace events occur frequently, the ICE 3 can acquire desired data without causing an overflow in the trace buffer 22.

(Sixth Embodiment) FIG. 13 is a block diagram showing a schematic configuration of a system using a debugging device according to a sixth embodiment of the present invention. This system includes a debug target 1, a debug device 2f, and an ICE 3.
Note that the debug target 1 and the ICE 3 are the same as those in the first embodiment.
, The detailed description will not be repeated.

The debug device 2f selects a judgment circuit 21 for judging the occurrence of a trace event, a trace buffer 22 for storing trace data, and a trace data stored in the trace buffer 22, and outputs the selected data as m-bit data. And a trace data selection circuit 23f.
Since determination circuit 21 and trace buffer 22 are the same as those described in the first embodiment, detailed description will not be repeated.

FIG. 14 is a block diagram for describing details of trace data selection circuit 23f shown in FIG. The trace data selection circuit 23f includes a secondary trace buffer 234 having a capacity of m × N bits,
A register 232 in which an arbitrary value is set by E3;
A selector 233 for selecting the trace data stored in the secondary trace buffer 234 according to the value set in the register 232, and an arithmetic circuit 242 for performing a predetermined operation on the trace data stored in the secondary trace buffer 234 And

The secondary trace buffer 234 has the same capacity of m × N bits as the trace buffer 22.
Arbitrary m-bit data is output from N m-bit data. The trace buffer 2 is stored in the secondary trace buffer 234 in synchronization with the timing at which the value of the internal data 13 is written to the trace buffer 22.
The values written to 2 are sequentially written.

The value of the register 232 is set by ICE3. The ICE 3 can select and read m-bit data at an arbitrary position from m × N-bit data by writing an arbitrary value to the register 232. The selector 233 selects and outputs the trace data stored in the secondary trace buffer 234 according to the value set in the register 232.

The operation circuit 242 performs an operation on the trace data stored in the secondary trace buffer 234, and
Output to CE3. For example, when the trace data stored in the secondary trace buffer 234 is sequentially read, the arithmetic circuit 242 adds all the 1-bit data at predetermined bit positions of the trace data and outputs the result to the ICE 3 as parity bits. By acquiring the parity bit, the ICE 3 can determine whether or not the m-bit data read out N times is missing. A similar effect can be obtained if the ICE 3 reads the trace data without the arithmetic circuit 242 so that a predetermined bit of the trace data is read at the same time, and the ICE 3 performs the operation. Can be.

As described above, according to the debugging device of the present embodiment, the arithmetic circuit 242 calculates the trace data when the ICE 3 sets the value in the register 232 and sequentially reads the trace data. Because
Trace data can be prevented from being lost, and the reliability of the system can be improved.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0089]

According to the first aspect of the present invention, the selecting means selects and outputs the trace data stored in the storage means in accordance with the position of the trace data specified by the specifying means. The ICE connected to the debug device can acquire only desired trace data.

According to the debugging device of the second aspect,
Since the second storage means transfers and stores the trace data stored in the first storage means, even if another trace event occurs, the trace data corresponding to the previous trace event is lost. And the overflow of trace data can be prevented.

According to the debugging device of the third aspect,
Since the selecting means selects and outputs an arbitrary 1-bit data from the trace data stored in the second storage means, the ICE connected to the debugging device can select a desired 1-bit data from the trace data. Trace data can be acquired in one cycle, and overflow of trace data can be further prevented.

According to the debug device of the fourth aspect,
Since the arithmetic means performs an arithmetic operation on the trace data stored in the storage means, for example, by adding all predetermined bits of the trace data and outputting the result as parity bits, the ICE can detect missing trace data and the like. became.

According to the debugging device of the fifth aspect,
The re-execution requesting unit requests the debug target to re-execute the program from a predetermined address when the detecting unit detects the trace event, so that the trace data corresponding to one trace event is divided into a plurality of times. It can be stored in the trace buffer.

According to the debugging device of the sixth aspect,
Since the second storage means transfers and stores the trace data stored in the first storage means, even if another trace event occurs, the trace data corresponding to the previous trace event is lost. And the overflow of trace data can be prevented.

According to the debugging device of the seventh aspect,
The second selecting means selects and outputs the trace data stored in the storing means in accordance with the output from the first selecting means, so that even if an overflow has occurred, the second selecting means is connected to the debugging device. The ICE can arbitrarily designate and read trace data that has not yet been read.

According to the debugging device of the eighth aspect,
Since the second storage means transfers and stores the trace data stored in the first storage means, even if another trace event occurs, the trace data corresponding to the previous trace event is lost. And the overflow of trace data can be prevented.

According to the debug device of the ninth aspect,
The storage unit stores the value of the internal data as trace data when the count result of the first counting unit reaches a predetermined value, so that even if a trace event occurs frequently, the overflow of the trace data is prevented. It became possible to do.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a system using a debugging device according to a first embodiment of the present invention.

FIG. 2 is a block diagram for explaining details of a trace data selection circuit 23a shown in FIG. 1;

FIG. 3 is a diagram for describing a configuration of a secondary trace buffer 231.

FIG. 4 is a block diagram illustrating a schematic configuration of a system using a debugging device according to a second embodiment of the present invention.

FIG. 5 is a block diagram for explaining details of a trace data selection circuit 23b shown in FIG. 4;

FIG. 6 is a block diagram illustrating a schematic configuration of a system using a debugging device according to a third embodiment of the present invention.

FIG. 7 is a block diagram for explaining details of a trace data selection circuit 23c shown in FIG. 6;

FIG. 8 is a block diagram showing a schematic configuration of a system using a debugging device according to a fourth embodiment of the present invention.

FIG. 9 is a block diagram for explaining details of a trace data selection circuit 23d shown in FIG. 8;

FIG. 10 is a block diagram illustrating details of an overflow detection circuit 239 shown in FIG. 9;

FIG. 11 is a block diagram showing a schematic configuration of a system using a debugging device according to a fifth embodiment of the present invention.

FIG. 12 is a block diagram for describing details of a trace count circuit 27 shown in FIG. 11;

FIG. 13 is a block diagram showing a schematic configuration of a system using a debugging device according to a sixth embodiment of the present invention.

14 is a trace data selection circuit 23 shown in FIG.
It is a block diagram for explaining the detail of f.

FIG. 15 is a block diagram showing a schematic configuration of a system using a conventional debugging device.

FIG. 16 is a diagram showing a configuration example of a trace buffer 122.

FIG. 17 is a diagram showing the timing at which the ICE 103 reads trace data from the trace buffer 122.

[Explanation of symbols]

1 debug target, 2a-2f debug device, 3I
CE, 11 CPU, 12 internal bus, 13 internal data, 21 determination circuit, 22 trace buffer, 23a
~ 23d, 23f Trace data selection circuit, 24W
E signal, 25 repeat signal, 26 clock signal, 27
Trace count circuit, 29,235,271 counter, 30,233a, 233b, 238 selector,
31WE2 signal, 231,234 secondary trace buffer, 232,272 register, 236,273,23
91 comparison circuit, 237, 241, 392 AND circuit, 239 overflow detection circuit, 240 OR circuit, 2393 holding circuit, 242 arithmetic circuit.

Claims (9)

[Claims] A detecting means for detecting a trace event occurring in a debug target; a storage means for storing a value of internal data as trace data when the trace event is detected by the detecting means; A designation unit for designating an arbitrary position of the trace data stored by the storage unit; and selecting the trace data stored in the storage unit according to the position of the trace data designated by the designation unit. And a selecting means for outputting. 2. The first storage means for storing a value of internal data as trace data, and the second storage means for transferring and storing the trace data stored in the first storage means. 2. The storage device according to claim 1, wherein the selection unit selects and outputs the trace data stored in the second storage unit according to the position of the trace data specified by the specification unit. Debug device as described. 3. The debugging device according to claim 2, wherein said selection means selects and outputs an arbitrary 1-bit data from the trace data stored in said second storage means. 4. The debugging device according to claim 1, wherein said debugging device further includes an operation unit for performing an operation on the trace data stored in said storage unit. 5. Detecting means for detecting a trace event occurring in a debug target, and storage means for storing a value of internal data as trace data when the trace event is detected by the detecting means; Counting means for counting the trace events detected by the detection means; selecting means for selecting and outputting the trace data stored in the storage means in accordance with the counting result by the counting means; And a re-execution requesting means for requesting the debug target to re-execute a program from a predetermined address when a trace event is detected by the detection means. 6. A first storage unit for storing a value of internal data as trace data, and a second storage unit for transferring and storing the trace data stored in the first storage unit. 6. The debugging device according to claim 5, further comprising: a second storage unit, wherein the selection unit selects and outputs the trace data stored in the second storage unit according to a counting result by the counting unit. 7. A first detecting means for detecting a trace event occurring in a debug target, and when the trace event is detected by the first detecting means, a value of internal data is stored as trace data. Storage means for specifying the position of the trace data stored by the storage means; specifying means for counting the number of times of reading the trace data stored in the storage means; Second detection means for detecting an overflow in the storage means; and if the overflow is not detected by the second detection means, the counting result of the counting means is selected, and the overflow is detected by the second detection means. Is detected, the position of the trace data designated by the designation means is selected and output. Debugging device comprising a first selection means, in response to an output from said first selecting means, and a second selection means for selecting and outputting trace data stored in the storage unit. 8. The first storage means for storing the value of internal data as trace data, and the second storage means for transferring and storing the trace data stored in the first storage means. 2. The second selecting means, wherein the second selecting means selects and outputs the trace data stored in the second storing means in accordance with an output from the first selecting means. 7. The debugging device according to 7. 9. A detecting means for detecting a trace event occurring in a debug target, a first counting means for counting the trace events detected by the detecting means, and a counting by the first counting means Storage means for storing the value of the internal data as trace data when the result has reached a predetermined value; second counting means for counting the number of times of reading the trace data stored in the storage means; Selecting means for selecting and outputting the trace data stored in the storage means in accordance with the counting result by the second counting means.