JP2004061114A - Self-diagnosis test circuit and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten the inspection time and to improve the inspection mass production yield and the inspection coverage degree, in the inspection of a logic circuit such as a semiconductor integrated circuit. <P>SOLUTION: An SRAM 1017 for storing test setting data for each externally designated test item and a BIST (built-in self-test) controller 1005 for reading out the test setting data stored in the SRAM and for executing the BIST, in parallel with the operation of storing the test setting data in the SRAM, are provided. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a self-diagnosis test circuit and a method for efficiently testing a logic circuit such as a semiconductor integrated circuit.
[0002]
[Prior art]
In recent years, as the circuit scale of semiconductor integrated circuits has increased, it has become difficult to manually create and inspect shipping inspection data necessary for producing high-quality products. Is being adopted. Among them, a scan path test method and a more advanced logic BIST (built-in self test) method are often used as test methods for automating the test of a logic circuit.
[0003]
FIG. 5 is a block diagram showing a configuration of such a conventional self-diagnosis test circuit. In FIG. 5, a test target circuit 1001 including a self-diagnosis test circuit is a semiconductor integrated circuit or a logic circuit system. A logic BIST using a scan path test method is mounted as a self-diagnosis system for a large-scale logic circuit. I have.
[0004]
The basic configuration of the logic BIST is that a data generator 1002 generates a pseudo-random code and outputs it as a scan input data signal 1012, which is applied to a scan path test target circuit 1003 to form a scan register of an internal register. , And by performing capture operation of at least one clock or more, the data passed through the logic combination circuit is accumulated again in the internal register, and output as the scan output data signal 1013. This is input to a data compression circuit 1004 which is a multi-input code compression circuit.
[0005]
The BIST controller 1005, which is a circuit for controlling such a self-diagnosis function, conforms to a boundary scan test method such as JTAG, etc., while minimizing the number of dedicated test terminals such as the boundary scan data input 1007 and connecting the product to the outside. Under the control of the TAP controller 1006 that performs a connection test, a procedure for an internal circuit test is set.
[0006]
The test result stored in the data compression circuit 1004 is passed to the BIST controller 1005 as a data read signal 1014, and is further taken out as a test data read signal 1015 by external control of the TAP controller 1006. The data is taken out as the boundary scan data output 1016.
[0007]
The logic BIST needs to apply data while changing the pattern setting of pseudo-random data many times in order to inspect with higher reliability, and a generated data setting signal for specifying a code to be generated and a generation timing. 1009 is applied from the BIST controller 1005 to the data generator 1002. Also, the BIST controller 1005 needs to receive the designation of the generated data from the outside by the BIST control signal 1008 from the TAP controller 1006.
[0008]
In addition, for the scan shift operation, a scan operation control signal 1010 for fixing the mode to the scan circuit state, switching between the shift and the capture operation, and the like must be applied to the scan path test target circuit 1003.
[0009]
Also, the internal state of the data compression circuit 1004 is initialized at the beginning of the test, and the initialization and data compression timing setting 1011 are transmitted from the BIST controller 1005 so that the compression operation does not change during the period in which the data setting state does not need to be changed. It needs to be provided to the data compression circuit 1004.
[0010]
FIG. 6 is a diagram showing a test procedure in the conventional self-diagnosis test circuit configured as described above. In FIG. 6, the horizontal axis is an inspection time axis 1301 indicating the accumulated inspection time in the inspection procedure.
[0011]
In the first test operation unit time 1302, the first BIST test operation 1307 is performed after the first BIST setting operation 1306. In the second test operation unit time 1303, the second BIST test operation is performed after the second BIST setting operation 1308. 1309, and similarly in the third and subsequent times, in the nth test operation unit time 1304, the nth BIST test operation 1311 is performed after the nth BIST setting operation 1310.
[0012]
As described above, the BIST setting operation and the BIST test operation are sequentially performed once to n times, respectively, and finally, at the test result read time 1305, the compressor monitor operation for reading the test results accumulated in the compressor. Execute 1312 to complete the inspection.
[0013]
[Problems to be solved by the invention]
However, the configuration of the above-described conventional self-diagnosis test circuit has a disadvantage in that it takes too much time to set a boundary scan which is inherently slow, which leads to an increase in inspection time and an increase in inspection cost.
[0014]
In addition, when data is garbled due to timing variations exceeding the design value in data from unnecessary timing paths when an actual circuit is used, all of the compressed data stored in the data compression circuit cannot be used, thereby lowering the yield. And that the inspection coverage is reduced due to deletion of inspection items and the like.
[0015]
Further, in recent semiconductor integrated circuits and the like, it is necessary to design as low power as possible while supplying multiple power supplies and various clocks. However, a method for automating the inspection of such semiconductor integrated circuits has not been provided. Was.
[0016]
The present invention has been made in view of the above circumstances, and in testing a logic circuit such as a semiconductor integrated circuit, reduces the test time, improves the mass production yield of the test and the test coverage, and furthermore, in a multi-power supply and various clock system. Another object of the present invention is to provide a self-diagnosis test circuit and a method which can easily automate the test.
[0017]
[Means for Solving the Problems]
In order to solve this problem, a self-diagnosis test circuit according to claim 1 of the present invention is mounted on a logic circuit such as a semiconductor integrated circuit to be inspected and uses test setting data for each test item specified from the outside. A self-diagnosis test circuit for generating test data and performing a BIST (built-in self test), comprising: a memory for storing the test setting data; and a memory for storing the test setting data in the memory. A BIST controller that reads the test setting data stored in the memory and executes the BIST.
[0018]
According to the above configuration, since the BIST is executed in parallel with the operation of fetching the test setting data for each test item specified from the outside and storing it in the memory, the processing time caused by the external low-speed serial interface is suppressed. , Test time can be reduced.
[0019]
The self-diagnosis test circuit according to claim 2 of the present invention is the self-diagnosis test circuit according to claim 1, wherein the BIST is executed using a plurality of scan paths, and an output of the plurality of scan paths is externally provided. It is provided with a mask circuit capable of setting mask data for each test item.
[0020]
According to the above configuration, since a mask can be set for each test item and each scan path output, an expected value can be masked only for a specific scan line of a specific test number, and the data compression inspection result of another scan line can be obtained. By being able to perform inspection without impairment, stable mass production inspection can be performed in a short period of time without significantly reducing inspection coverage.
[0021]
A self-diagnosis test circuit according to a third aspect of the present invention is the self-diagnosis test circuit according to the first or second aspect, wherein a power supply voltage value and a power on / off or restart timing for an internal circuit block are provided as a normal function. And a BIST controller that controls the execution of the BIST without using the normal function when the BIST is executed, controls the power setting function using the test setting data. .
[0022]
According to the above configuration, since the BIST controller can control the power supply setting function provided as a normal function and execute the BIST, the semiconductor having the power supply setting function which has not been subjected to the automated inspection of the power supply conventionally. The automatic inspection by BIST can be performed also in a logic circuit such as an integrated circuit.
[0023]
A self-diagnosis test circuit according to a fourth aspect of the present invention is the self-diagnosis test circuit according to any one of the first to third aspects, wherein a clock frequency setting or a clock stop for an internal circuit block is performed as a normal function. It has a clock setting function for setting the timing of restarting, etc., and when executing the BIST, the BIST controller that controls the execution of the BIST controls the clock setting function using the test setting data, regardless of the normal function. Is what you do.
[0024]
According to the above configuration, since the BIST controller can control the clock setting function provided as a normal function and execute the BIST, the semiconductor having the clock setting function in which the clock has not been subjected to the automated inspection conventionally has been performed. The automatic inspection by BIST can be performed also in a logic circuit such as an integrated circuit.
[0025]
The self-diagnosis test circuit according to claim 5 of the present invention is the self-diagnosis test circuit according to claim 4, wherein the power supply voltage for the internal circuit block is uniquely determined according to the setting of the clock frequency for the internal circuit block. It has a configuration that can be set.
[0026]
According to the above configuration, the power supply setting function and the clock setting function are provided as normal functions, and the power supply voltage is uniquely set according to the setting of the clock frequency, so that the optimum power supply voltage can be set according to the required processing speed. In a logic circuit such as a semiconductor integrated circuit to be set, an automatic inspection using these functions can be performed by BIST.
[0027]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a self-diagnosis test circuit according to Embodiment 1 of the present invention. 1, the same components as those of the conventional self-diagnosis test circuit shown in FIG. 5 are denoted by the same reference numerals, and detailed description will be omitted.
[0028]
In FIG. 1, the test target circuit 1001 includes a data generator 1002, a scan path test target circuit 1003, a data compressor 1004, a BIST controller 1005, a TAP controller 1006, and an SRAM 1017 connected to the BIST controller 1005. Since a large-scale circuit usually has a plurality of SRAMs mounted thereon, the SRAM 1017 does not need to be mounted exclusively, and may be used for other functions other than shipping inspection.
[0029]
The SRAM 1017 is connected to the BIST controller 1005 by a data write signal 1018 and a data read signal 1019. In the logic BIST mode, the test setting data received by the BIST controller 1005 from the TAP controller 1006 for the setting of the logic BIST is written into the SRAM 1017 to temporarily buffer the SRAM, and the SRAM 1017 is required when the BIST controller 1005 needs the setting data. Is read from the setting data.
[0030]
FIG. 2 is a diagram showing a test procedure in the self-diagnosis test circuit of the present embodiment configured as described above. In FIG. 2, the vertical axis 1400 indicates the number of test items, and the horizontal axis 1401 indicates the test time. The graph shows the relationship between the test item setting and the test item processing time when the SRAM 1017 is used.
[0031]
More specifically, one test item (one scale on the vertical axis) is set per unit time (one scale on the horizontal axis), and when a test item is set, the logic BIST operation is immediately performed inside the circuit to be inspected. The processing is started and the processing time is 2 unit times as an example.
[0032]
In FIG. 2, in the transition of the test item setting number 1402 indicated by the dotted line, the setting time Tset per test item is processed in one unit time, and the setting of five items is completed after five unit times. On the other hand, in the transition of the test item processing count 1403, the processing time Tex per test item is processed in 2 unit times, and the processing is completed after a total of 11 unit times of 5 processing times in addition to the initial set time Tset. ing.
[0033]
When all the setting items have been processed, an operation of reading the inspection result from the JTAG port is required. The read time is set to Tread, and the rough processing time T1 according to the present embodiment and the rough processing according to the conventional example shown in FIG. When the formula for calculating the time T5 is derived, the following is obtained using * as a multiplication symbol.
[0034]
T1 = Tset + (Tex) * (total number of test items) + Tread
T5 = (Tset + Tex) * (total number of test items) + Tread
[0035]
As described above, in the conventional example, the external low-speed serial interface has a large effect on the inspection time. This is because the setting operation time and the inspection operation time are added when there is no buffer for setting data such as the SRAM 1017, whereas when a buffer such as an SRAM that can sufficiently store the number of setting items is connected, This is because the setting operation and the internal inspection processing operation proceed in parallel, so that the processing time caused by the external low-speed serial interface can be suppressed.
[0036]
As described above, according to the present embodiment, in the logic BIST test mode, the memory for the buffer is connected to the controller of the logic BIST, and each test content for the logic BIST can be temporarily stored, so that the test can be performed. Time can be reduced.
[0037]
(Embodiment 2)
FIG. 3 is a block diagram showing a configuration of the self-diagnosis test circuit according to the second embodiment of the present invention. In FIG. 3, the same components as those of the self-diagnosis test circuit of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and detailed description will be omitted.
[0038]
In FIG. 3, the test target circuit 1001 includes a data generator 1002, a scan path test target circuit 1003, a data compressor 1004, a BIST controller 1005, a TAP controller 1006, an SRAM 1017, a scan path test target circuit 1003, and a data compressor 1004. It has a mask circuit 1102 for the scan output data inserted between them. A mask signal 1101 of scan output data for mask-controlling the scan output data from the BIST controller 1005 is connected to the mask circuit 1102.
[0039]
The mask signal 1101 of the scan output data is also composed of k pieces so that the k pieces of scan output data can be masked in 1-bit units, and the mask circuit 1102 of the scan output data is composed of k AND gates. Is done.
[0040]
That is, the LSB AND gate 1103 for LSB receives the LSB bit 1106 of the scan path output and the LSB bit 1105 of the mask signal, outputs the LSB bit 1107 of the mask output, and the AND gate 1104 for MSB similarly outputs the scan path output. The MSB bit 1109 and the MSB bit 1108 of the mask signal are input, and the MSB bit 1110 of the mask output is output.
[0041]
As described above, according to the present embodiment, by providing a mask function that can be set for each scan path from the outside via the BIST controller, the expected value can be masked only for a specific scan line of a specific test number. As a result, timing variations due to unnecessary data can be masked, so that stable mass production inspection can be performed without significantly lowering test coverage and delaying development due to circuit modification. Will be possible.
[0042]
(Embodiment 3)
FIG. 4 is a block diagram showing a configuration of a self-diagnosis test circuit according to Embodiment 3 of the present invention. In FIG. 4, a test target circuit 1201 that is a target of the logic BIST includes a B power supply circuit unit 1202 mounted in an area where power is constantly activated in a normal mode, and an M power supply circuit unit 1203 in the other two power supply areas. And an H power supply circuit section 1204.
[0043]
Further, in a normal use state after the product is shipped, a processor unit 1205 for controlling the clock frequency and the optimum power supply voltage according to the start / stop of the power supply and the processing speed is also mounted on the H power supply circuit unit 1204.
[0044]
A BIST controller 1206, a TAP controller 1006, and an SRAM 1017 described in the embodiment of the logic BIST in the first and second embodiments are different from the first and second embodiments in the B power supply circuit unit 1202 in the area where the constant power supply is activated. The circuits are connected in a similar configuration, but a circuit described below is added for controlling the power supply.
[0045]
A timing control unit 1207 such as a start-up and power supply mask is a circuit for controlling a signal to be transferred between a plurality of power supplies. And a function of supplying a mask signal between power supplies for a certain period of time until the power supply is stabilized even after the supply of power is started.
[0046]
Further, the timing control unit 1207 such as a start-up and power supply mask receives a time setting until the power is stopped and restarted, a power supply voltage value setting, a clock frequency setting according to the power supply voltage, and the like, and further receives a power supply start instruction from outside. A notification signal RSTN 1220 is applied, and a function of generating a signal for inter-power supply masking with an external power supply is required.
[0047]
As a control signal to the timing control unit 1207 such as a start-up and power supply mask, a processor start instruction input signal 1218 is selected under the control of the processor unit 1205 during a normal operation, whereas a BIST controller start instruction input signal is input during a logic BIST mode test. 1219 is selected. Each start instruction input signal is input to the selection circuit 1217 to be selected, and is applied as a start instruction input signal 1216 to the timing control unit 1207 such as start and power mask.
[0048]
The activation control signal 1215 output from the timing control unit 1207 such as activation and power supply mask is connected to the power supply unit 1210, the clock generation unit 1213, and the BIST controller 1206, and is used for protection control between the power supply, the clock, and the power supply.
[0049]
The power supply unit 1210 includes an M power supply output unit 1208 and an H power supply output unit 1209. According to the control of the power supply voltage set value and the turn-on timing from the timing control unit 1207 such as start-up and power supply mask, the VDDM 1223 is supplied to the M power supply circuit unit, VDDH 1224 is supplied with power to the H power supply circuit unit.
[0050]
The clock generation unit 1213 includes a PLL unit 1211 and a frequency dividing circuit 1212. The clock generation unit 1213 controls the clock frequency and application timing according to the power supply voltage from the timing control unit 1207 such as start-up and power supply mask. , And CKH1226 to the H power supply circuit unit.
[0051]
The BIST controller performs a test control and data input / output signal 1221 to the M power circuit section and the H power circuit section based on the power supply state and power supply timing information input from the timing control section 1207 such as the activation and power supply mask. To control or observe the BIST control target circuit located in each power supply circuit unit.
[0052]
In addition, in order to protect signal lines between power supplies other than the B power supply section, the timing control section 1207 such as a start-up and power supply mask supplies an inter-power supply mask signal 1222 to each power supply circuit section.
[0053]
Here, when the internal power supply of the test target circuit 1201 is in the activated state and the external power supply is not activated, the RSTN 1220 supplies the activation and power supply masking timing control unit 1207 from the outside as a signal for notifying the external power supply state. In addition, a necessary mask condition is given to a signal between an external power supply and each internal power supply.
[0054]
Conventionally, a circuit for controlling a power supply and a clock frequency has been verified by fixing the power supply voltage in a constantly activated state to a target of a logic BIST, but it has not been able to accurately inspect a case where the power supply voltage originally fluctuates. .
[0055]
On the other hand, in the self-diagnosis test circuit of the present embodiment described above, the power supply state and even the clock frequency can be easily changed by the serial setting such as JTAG as in the case of the processor control. Since an input selection circuit 1217 is provided and control by the logic BIST controller 1206 is possible in the test state of the logic BIST, the power supply voltage and the clock frequency can be freely adjusted during the inspection without falling into a setting that impairs the reliability of the product. Can be changed.
[0056]
The SRAM described with reference to FIG. 1 stores at least the setting data of the logic BIST. In addition to the initial value information for controlling the generation of the random code, mask bit information of the scan output data of the data compressor and multiple power supplies The setting information such as the start and stop of the power supply of the circuit and the information of the power supply voltage and the designation of the clock frequency may be temporarily buffered.
[0057]
Further, even when the power is restarted after the power is turned off and the logic BIST operation is continued, the data stored in the data compressor 1004 is temporarily stored in the SRAM before the power is turned off without being read out to the outside. Alternatively, by restoring this after restarting the power supply, communication time with the outside may be saved.
[0058]
In addition, each power supply circuit unit in FIG. 4 is divided into circuits to be subjected to the BIST, and a clock is supplied from the clock generation unit to each of the divided circuits so that a test at a necessary and sufficient clock frequency is performed. You can go.
[0059]
Further, the power supply from the power supply unit to each power supply destination may be output once to the outside of the inspection target circuit 1201 and then controlled via external wiring or an external power supply circuit.
[0060]
In the above description, the case where the processor 1205 is inside the circuit under test 1201 is shown, but the processor 1205 may be outside the circuit under test 1201.
[0061]
Further, the BIST controller has a control function of the logic BIST, but may have a function of checking another function macro such as a DRAM.
[0062]
【The invention's effect】
As described above, according to the present invention, the BIST is performed using the test setting data read from the memory in parallel with the operation of accumulating the test setting data for each test item externally set via the serial interface in the memory. Is executed, the processing time caused by the external low-speed serial interface is suppressed, and an excellent effect that the test time can be shortened is obtained.
[0063]
Further, according to the present invention, the expected value can be masked only for a specific scan line of a specific test number, so that inspection can be performed without impairing data compression inspection results of other scan lines, thereby significantly reducing inspection coverage. An excellent effect that a stable mass production inspection can be performed without causing the development or delaying the development due to the modification of the circuit can be obtained.
[0064]
Further, according to the present invention, since the BIST controller can control the power setting function and the clock setting function provided as the normal functions for the low power setting and execute the BIST, the automatic inspection using these processor setting functions can be performed. An excellent effect that it can be performed is obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a self-diagnosis test circuit according to a first embodiment of the present invention.
FIG. 2 is a diagram showing a test procedure in the self-diagnosis test circuit according to the first embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration of a self-diagnosis test circuit according to a second embodiment of the present invention.
FIG. 4 is a block diagram showing a configuration of a self-diagnosis test circuit according to a third embodiment of the present invention.
FIG. 5 is a block diagram showing a configuration of a conventional self-diagnosis test circuit.
FIG. 6 is a diagram showing a test procedure in a conventional self-diagnosis test circuit.
[Explanation of symbols]
1001 Test target circuit 1002 Data generator 1003 Scan path test target circuit 1004 Data compressor 1005 BIST controller 1006 TAP controller 1007 Boundary scan data input 1008 BIST control signal 1009 Generated data setting signal 1010 Scan operation control signal 1011 Initialization and data compression timing Setting 1012 Scan input data signal 1013 Scan output data signal 1014 Data read signal 1015 Test data read signal 1016 Boundary scan data output 1017 SRAM
1018 Data write signal 1019 Data read signal 1101 Scan output data mask signal 1102 Scan output data mask circuit 1103 LSB AND gate 1104 MSB AND gate 1105 Mask signal LSB bit 1106 Scan path output LSB bit 1107 Mask output LSB Bit 1108 MSB bit of mask signal 1109 MSB bit of scan path output 1110 MSB bit of mask output 1201 Test target circuit 1202 B power supply circuit section 1203 M power supply circuit section 1204 H power supply circuit section 1205 Processor section 1206 BIST controller 1207 Startup and power supply mask Equal timing control section 1208 M power output section 1209 H power output section 1210 power supply section 1211 PLL section 1212 frequency dividing circuit 1 13 clock generating unit 1215 start control signal 1216 start instruction input signal 1217 startup instruction input selection circuit 1218 processor start instruction input signal 1219 BIST controller start instruction input signal 1220 RSTN (power activation instruction notification signal from the outside)
1221 Test control and data input / output signal 1222 Power supply mask signal 1223 VDDM
1224 VDDH
1225 CKM
1226 CKH
1301 Inspection time axis 1302 First test operation unit time 1303 Second test operation unit time 1304 Nth test operation unit time 1305 Test result read time 1306 First BIST setting operation 1307 First BIST test operation 1308 Second BIST setting operation 1309 Second BIST test operation 1310 Nth BIST setting operation 1311 Nth BIST test operation 1312 Compressor monitor operation 1400 Number of test items 1401 Test time 1402 Number of set test items 1403 Number of processed test items

Claims (10)

A self-diagnosis test circuit mounted on a logic circuit such as a semiconductor integrated circuit to be inspected, generating test data using test setting data for each test item specified from the outside, and executing a BIST (built-in self test), ,
A memory for storing the test setting data;
A BIST controller that reads the test setting data stored in the memory and executes the BIST in parallel with an operation of storing the test setting data in the memory;
A self-diagnosis test circuit comprising: 2. The BIST according to claim 1, wherein the BIST is executed using a plurality of scan paths, and a mask circuit capable of externally setting mask data for each test item with respect to outputs of the plurality of scan paths. Self-diagnosis test circuit. As a normal function, it has a power supply setting function for setting a power supply voltage value and a power on / off or restart timing for an internal circuit block. When the BIST is executed, the BIST is executed regardless of the normal function 3. The self-diagnosis test circuit according to claim 1, wherein a controlling BIST controller controls the power setting function using the test setting data. As a normal function, it has a clock setting function for setting a clock frequency or setting a clock stop and restart timing for an internal circuit block. When the BIST is executed, the BIST execution is controlled regardless of the normal function. 4. The self-diagnosis test circuit according to claim 1, wherein a BIST controller that controls the clock setting function using the test setting data. 5. The self-diagnosis test circuit according to claim 4, wherein a power supply voltage for said internal circuit block can be uniquely set according to a setting of a clock frequency for said internal circuit block. A self-diagnosis test method for generating test data using test setting data for each test item specified from the outside and executing a BIST (built-in self test),
A self-diagnosis test method, wherein the test setting data stored in the memory is read and the BIST is executed in parallel with the operation of storing the test setting data in the memory. 7. The self-diagnosis test method according to claim 6, wherein the BIST is executed using a plurality of scan paths, and mask data is set externally for each test item with respect to outputs of the plurality of scan paths. As a normal function, a power supply setting function for setting a power supply voltage value and power supply on / off or restart timing for an internal circuit block. The self-diagnosis test method according to claim 6, wherein the power supply setting function is controlled by using the self-diagnosis test function. As a normal function, a clock setting function for setting a clock frequency or a clock stop and restart timing for an internal circuit block is used. When the BIST is executed, the test setting data is used regardless of the normal function. 9. The self-diagnosis test method according to claim 6, wherein the clock setting function is controlled by controlling the clock setting function. 10. The self-diagnosis test method according to claim 9, wherein a power supply voltage for said internal circuit block is uniquely set according to a setting of a clock frequency for said internal circuit block.

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