JP2007035119A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of changing written data by changing only a mask with respect to the data for a ROM while a circuit for test is arranged in a chip. <P>SOLUTION: An inspection circuit 1 for inspecting if the data, stored in a ROM101, is correct, comprises a ROM data read part 102 for reading the data stored in the ROM101, a data holding part 103 for saving the ROM data read by the ROM data reading part 102, a data comparison reference part 104 for comparing the ROM data saved by the data holding part 103 with an expected value data D inputted from the outside, and a result output part 106 for outputting the comparison result by data comparison part 104 to the outside. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a self-diagnosis function.

  The mask ROM is a ROM in which data is written at the time of manufacture, and a test is performed as to whether data is correctly written after manufacture. One of such test methods is called ROM Bist (Build-In Self Test). In the ROM Bist, a test circuit for judging whether data written in the ROM is correct or not is provided on the same chip as the ROM, and the ROM test can be executed only by the chip.

In the conventional ROM Bist, a value (expected value) corresponding to the data written in the ROM is stored in the test circuit, and the ROM data is read and compared with the expected value stored in the test circuit. The expected value stored in the test circuit includes, for example, a result obtained by calculating a value of 1 or 0 stored in the ROM.
When the calculation result is set to an expected value, it is necessary to read the data written in the ROM and perform the calculation in the ROM test. In order to avoid an increase in the amount of data stored in the ROM and an increase in the scale of the arithmetic circuit, in the invention of Patent Document 1, the number of occurrences of 1 or 0 of ROM data is stored in the test circuit. .
JP-A-10-27498

  By the way, in the manufacturing process of the mask ROM, the data written in the ROM can be changed only by changing the mask of the data layer. However, when the conventional ROM Bist is adopted, it is necessary to change the test circuit when the mask ROM data is changed. For this reason, not only the mask of the layer regarding data but the other mask must be changed.

Further, in order to change the test circuit, it may be necessary to change the design of the data processing timing and the like. An increase in the number of masks to be changed or a design change is undesirable because it leads to an increase in the cost for manufacturing the mask ROM and a longer development period.
The present invention has been made in view of the above points, and provides a semiconductor device capable of changing data to be written by changing only a mask related to ROM data while providing a test circuit on a chip. The purpose is to provide.

  In order to solve the above problems, a semiconductor device of the present invention is a semiconductor device including a ROM and an inspection circuit that inspects correctness of data stored in the ROM, and the inspection circuit includes the ROM ROM data reading unit for reading data stored in the ROM, ROM data storage unit for storing ROM data read by the ROM data reading unit, ROM data stored by the ROM data storage unit, and external input And a comparison result output unit for outputting a result of data comparison by the data comparison unit to the outside.

  According to such an invention, it is possible to provide in the semiconductor device a test circuit that inputs data input from the outside and determines the correctness of the ROM data by comparing with the ROM data. For this reason, it is possible to eliminate the need to change the configuration of the inspection circuit in accordance with the ROM data change while taking the Bist form for determining whether the ROM data is correct or not in the chip. Therefore, it is possible to provide a semiconductor device that can change data to be written by changing only a mask related to ROM data while providing a test circuit on the chip.

The semiconductor device according to the present invention further includes an external data reading unit that reads external data, and an external data storage unit that stores external data read by the external data reading unit.
According to such an invention, reading of external data and adjustment of input timing of the read data to the inspection circuit can be executed by the semiconductor device itself.

  In the semiconductor device of the present invention, the ROM data reading unit reads the ROM data for each address, and the ROM data storage unit stores the read ROM data for a plurality of addresses, and the external data reading unit. Reads the external data for each address, the external data storage unit stores the read external data for a plurality of addresses, and the data comparison unit stores the ROM for the plurality of addresses stored in the ROM data storage unit. The data is compared with external data for a plurality of addresses stored in the external data storage unit.

According to such an invention, although there is one terminal for reading ROM data and external data, the time required for comparing the ROM data with the external data is shortened, and thus the time required for testing the ROM data is reduced. It can be shortened.
In the semiconductor device of the present invention, the ROM data reading unit reads the ROM data for each of a plurality of addresses, and the ROM data storage unit stores the read ROM data for a plurality of addresses, and the external data reading unit. Reads the external data for each of a plurality of addresses, and the external data storage unit stores the read external data for a plurality of addresses, and the data comparison unit stores a ROM for the plurality of addresses stored in the ROM data storage unit. The data is compared with external data for a plurality of addresses stored in the external data storage unit.

According to such an invention, the time for reading ROM data and external data can be shortened, and the time required for testing ROM data can be further shortened.
Further, the semiconductor device of the present invention extracts the ROM data for a plurality of addresses stored in the ROM data storage unit and the external data for the plurality of addresses stored in the external data storage unit for each address, and compares the data. The data comparison unit compares the ROM data for one address supplied by the data supply unit with the external data for one address.

According to such an invention, it is possible to suppress an increase in the scale of the circuit configured to compare the ROM data and the external data while shortening the reading time of the ROM data and the external data.
The semiconductor device according to the present invention further includes an address determining unit that determines an address of data read by each input terminal when the ROM data reading unit and the external data reading unit read data using a plurality of input terminals. It is characterized by providing.

  According to such an invention, when data is read using a plurality of input terminals, the data read by each input terminal can be adjusted, and data for a plurality of addresses can be appropriately input.

Embodiments 1 to 4 of a semiconductor device according to the present invention will be described below with reference to the drawings.
(Embodiment 1)
FIG. 1 is a diagram common to the embodiments of the present invention and is a diagram for explaining an outline of a semiconductor device. The semiconductor device according to the first embodiment is an IC including a ROM (Read Only Memory) and an inspection circuit 1 that inspects correctness of data stored in the ROM. The inspection circuit 1 is also a circuit that inspects the correctness of data stored in the ROM 101. The inspection circuit is a Bist circuit that collates the expected value of the ROM 101.

The ROM 101 is a mask ROM, and data is written at the time of manufacture, and the data cannot be changed after manufacture. Data to be written in the ROM 101 is determined by a specific layer pattern. Therefore, the data in the ROM 101 can be changed by changing the mask for patterning this pattern.
The inspection circuit 1 reads data from the outside and compares the read data with the data stored in the ROM 101. In the present embodiment, a storage device 7 that stores expected value data D that is similar to the data stored in the ROM 101 is placed outside, and the expected value data D is supplied to the inspection circuit 1 as external data. The inspection circuit 1 is connected to a verification result output terminal 4 that outputs a correct / incorrect determination result.

When the user reads data from the ROM 101 in order to cause the IC to perform a normal operation other than the test, the user side circuit (user circuit) 6 is connected to the ROM 101. The user circuit 6 has a user terminal 3, and a user supplies a signal to the user circuit 6 via the user terminal 3 to exchange signals with the IC.
A clock terminal 5 is connected to the user circuit 6, and the user circuit 6 operates based on a clock signal supplied from the clock terminal. Since the ROM 101 is designed to read data according to this clock, the present embodiment connects the clock terminal to the test circuit 1 and uses the clock signal supplied from the clock terminal even in the test of the ROM 101. It shall be.

The test mode switching unit 2 switches between the normal operation of the IC and the operation (test mode) for testing the ROM 101. The test mode switching unit 2 is a switch that changes the input / output circuits related to the inspection circuit 1 and the ROM 101 between the normal operation and the test mode.
FIG. 2 is a functional block diagram for explaining the inspection circuit 1 shown in FIG.

  The inspection circuit 1 includes a ROM data reading unit 102 that reads data (ROM data R) stored in the ROM 101, and a data holding unit 103 that sequentially stores the ROM data R read by the ROM data reading unit 102 for each address. I have. Furthermore, the inspection circuit 1 according to the first embodiment includes an external data reading unit 107 that reads the expected value data D, and a data holding unit 105 that sequentially stores the expected value data D read by the external data reading unit 107 for each address. ing.

  Furthermore, the inspection circuit 1 compares the ROM data R stored by the data storage unit 103 with the expected value data D stored by the data storage unit 105 and the data comparison reference unit 104 and the data comparison reference unit 104 And a result output unit 106 for outputting the comparison result to the outside. Note that the comparison reference unit 104 according to the first embodiment sequentially compares the ROM data R and the expected value data D for each address.

The ROM data reading unit 102, the external data reading unit 107, the data holding unit 103 and the data holding unit 105, the data comparison reference unit 104, and the result output unit 106 are all circuits that can realize the respective functions.
The expected value data D is data composed of 1 or 0 similar to the data that should be stored in the ROM 101, and is used to determine whether the data written in the ROM 101 is correct or incorrect. The correctness / incorrectness is determined by the degree of coincidence of 1 or 0 between the expected value data D and the ROM data R. In this embodiment, 1 or 0 data indicated by such external data is referred to as an expected value.

In addition, the inspection circuit of the first embodiment sequentially compares the expected value data D with the ROM data R, so that the external data reading unit 107 that reads the expected value data D and sequentially stores the read expected value data D for each address. A data holding unit 105 is provided, and the expected value data D held by the data holding unit is supplied to the data comparison reference unit 104 for each address.
In the semiconductor device according to the first embodiment configured as described above, the ROM data reading unit 102 sequentially reads the ROM data R from the ROM 101 one by one in the ROM 101 in synchronization with the clock signal. Further, the external data reading unit 107 sequentially reads the expected value data D for each address of the storage device in synchronization with the same clock signal.

  The read ROM data R is held in the data holding unit 103 one address at a time. The expected value data D is held in the data holding unit 105 one address at a time. The retained ROM data R and expected value data D are output to the data comparison reference unit 104 and compared in the data comparison reference unit 104. As a result of the comparison, the data comparison reference unit 104 outputs to the result output unit 106 whether 1 or 0 of the ROM data R and 1 or 0 of the expected value data D match.

The inspection circuit 1 performs the above operation for all of the ROM data R and the expected value data D. The result output unit 106 further outputs the result to the collation result output terminal 4. The user takes out the result of collation from the collation result output terminal 4 and determines whether the ROM data R and the expected value data D coincide with each other according to the degree of coincidence.
In the first embodiment described above, even when the mask for the data in the ROM 101 is changed and the data in the ROM 101 is changed, the expected value data D corresponding to the changed ROM data R is supplied to the inspection circuit 1. The ROM 101 can be tested. For this reason, in the manufacture of the IC, it is not necessary to change the inspection circuit accompanying the change of the mask for data.
(Embodiment 2)
Next, Embodiment 2 of the present invention will be described.

FIG. 3 is a functional block diagram for explaining the inspection circuit according to the second embodiment. In the figure, the same components as those shown in FIG. 2 are denoted by the same reference numerals, and a part of the description will be omitted.
In the semiconductor device according to the second embodiment, as in the first embodiment, the ROM data reading unit 102 reads ROM data for each address, and the external data reading unit 107 reads external data for each address.

However, the semiconductor device according to the second embodiment includes a data storage unit 201 that stores read ROM data R for a plurality of addresses, a data storage unit 203 that stores read expected value data D for a plurality of addresses, and ROM data R and an expectation. The second embodiment is different from the first embodiment in that a data comparison reference unit 202 that compares the value data D with a plurality of addresses is provided.
That is, in the semiconductor device of the second embodiment, the ROM data reading unit 102 sequentially reads the ROM data R from the ROM 101 for each address of the ROM 101 in synchronization with the clock signal. Further, the external data reading unit 107 sequentially reads the expected value data D for each address of the storage device in synchronization with the same clock signal.

The read ROM data R is accumulated for a plurality of addresses in the data storage unit 201. In addition, the expected value data D is accumulated in a plurality of addresses in the data storage unit 203. The stored ROM data R and expected value data D are output to the data comparison reference unit 202 at a time in synchronization with the clock signal.
The data comparison reference unit 202 compares the output ROM data R and expected value data D for a plurality of addresses for each of a plurality of addresses. As a result of the comparison, the data comparison reference unit 202 outputs to the result output unit 106 whether 1 or 0 of the ROM data R and 1 or 0 of the expected value data D match.

According to the second embodiment, the ROM data R and the expected value data D can be compared in a shorter time than the first embodiment. For this reason, the time required for the test can be reduced as compared with the first embodiment.
(Embodiment 3)
Next, a third embodiment of the present invention will be described.

FIG. 4 is a functional block diagram for explaining the inspection circuit according to the third embodiment. In the figure, the same components as those shown in FIGS. 2 and 3 are denoted by the same reference numerals, and the description thereof is partially omitted.
As in the second embodiment, the semiconductor device of the third embodiment includes a data storage unit 201 that stores read ROM data R for a plurality of addresses, a data storage unit 203 that stores read expected value data D for a plurality of addresses, A data comparison reference unit 202 is provided for comparing the ROM data R and the expected value data D for each of a plurality of addresses.

However, the semiconductor device of the third embodiment is different from the second embodiment in that the ROM data reading unit 302 reads the ROM data R for each of a plurality of addresses, and the external data reading unit 303 reads the expected value data D for each of a plurality of addresses. To do.
Such Embodiment 3 can be realized by using the user terminal 3 as a terminal for reading the ROM data R from the ROM 101 and a terminal for reading the expected value data D from the outside during the IC test.

That is, the user terminal 3 is generally composed of dozens to dozens of terminals. In the third embodiment, some of the plurality of terminals also serve as ROM data R reading terminals. A part is also used as a terminal for reading expected value data D.
In such a semiconductor device of the third embodiment, the ROM data reading unit 302 reads ROM data R for a plurality of addresses from the ROM 101 at a time in synchronization with the clock signal. The external data reading unit 303 reads the expected value data D for a plurality of addresses in synchronization with the same clock signal. The read ROM data R is stored for a plurality of addresses read at once in the data storage unit 201. In addition, the expected value data D is stored for a plurality of addresses read at once in the data storage unit 203. The stored ROM data R and expected value data D are output to the data comparison reference unit 202 at a time in synchronization with the clock signal.

The data comparison reference unit 202 compares the output ROM data R and expected value data D for a plurality of addresses for each of a plurality of addresses. As a result of the comparison, the data comparison reference unit 202 outputs to the result output unit 106 whether 1 or 0 of the ROM data R and 1 or 0 of the expected value data D match.
In this embodiment, since the ROM data reading unit 302 and the external data reading unit 303 read data for a plurality of addresses using a plurality of terminals, it is necessary to determine an address to be read from each terminal. In the third embodiment, the address determination unit 301 is provided in the inspection circuit, the address of the data read by each terminal is determined, and the ROM data reading unit 302 and the external data reading unit 303 are notified. The address determination unit 301 is a circuit having a function of switching in synchronization with a clock signal and controlling an address of data read by each terminal. In actual operation, address setting and data reading are performed in two clocks, such as setting an address with the first clock and reading data with the second clock.

According to the third embodiment, ROM data R and expected value data D can be read in a shorter time than in the second embodiment. For this reason, the time required for the test can be further reduced as compared with the second embodiment.
(Embodiment 4)
Next, a fourth embodiment of the present invention will be described.

FIG. 5 is a functional block diagram for explaining the inspection circuit according to the fourth embodiment. In the figure, the same components as those shown in FIGS. 2, 3, and 4 are denoted by the same reference numerals, and the description thereof is partially omitted.
As in the third embodiment, the semiconductor device according to the fourth embodiment includes a ROM data reading unit 302 that reads ROM data R for each of a plurality of addresses, an external data reading unit 303 that reads expected value data D for each of a plurality of addresses, and a read ROM. A data storage unit 201 that stores data R for a plurality of addresses, and a data storage unit 203 that stores the read expected value data D for a plurality of addresses are provided.

  However, the comparison circuit of the semiconductor device of the fourth embodiment is a data comparison reference unit 104 that sequentially compares the ROM data R and the expected value data D by one address. As a matter of course, such a data comparison reference unit 104 is slower in comparison processing than a configuration in which ROM data R and expected value data D can be compared at a time for a plurality of addresses. However, since the circuit that can compare the ROM data R and the expected value data D at the same time for a plurality of addresses tends to increase in circuit size, the comparison reference unit 104 reduces the circuit size of the comparison reference unit and reduces the chip size. It also has the advantage of being advantageous for downsizing.

  The semiconductor device of the fourth embodiment extracts ROM data R for a plurality of addresses stored in the data storage unit 201 and expected value data D for a plurality of addresses stored in the data storage unit 203 for each address, and compares them. A data extraction unit 401 to be supplied to the reference unit 104 is provided. The data extraction unit 401 is configured to function as a data supply unit of the fourth embodiment. The comparison reference unit 104 compares the ROM data R for one address supplied by the data extraction unit 401 with the external data D for one address.

As a result of the comparison, the data comparison reference unit 104 outputs to the result output unit 106 one address at a time whether 1 or 0 of the ROM data R and 1 or 0 of the expected value data D match.
According to the fourth embodiment, a high speed can be obtained in reading the ROM data R and the expected value data D. For this reason, the time required for the test of the ROM 101 can be reduced as compared with the first embodiment. In addition, since the data comparison reference unit 104 having a relatively small circuit scale is provided as a configuration for comparing data, it is possible to suppress an increase in the scale and cost of the inspection circuit.

It is a figure common to embodiment of this invention, Comprising: It is a figure for demonstrating the outline of the semiconductor device of Embodiment 1. FIG. It is a functional block diagram for demonstrating the test | inspection circuit of Embodiment 1 shown in FIG. It is a functional block diagram for demonstrating the test | inspection circuit of Embodiment 2 of this invention. It is a functional block diagram for demonstrating the test | inspection circuit of Embodiment 3 of this invention. It is a functional block diagram for demonstrating the test | inspection circuit of Embodiment 4 of this invention.

Explanation of symbols

1 Test circuit 2 Test mode switching unit 3 User terminal 4 Verification result output terminal
5 clock terminal, 6 user circuit, 7 storage device, 102, 302 ROM data reading unit, 103, 105 data holding unit, 104 data comparison reference unit, 106 result output unit 107, 303 external data reading unit, 201, 203 data storage Section, 301 address determination section, 401 data extraction section

Claims (6)

A semiconductor device comprising a ROM and an inspection circuit for inspecting the correctness of data stored in the ROM,
The inspection circuit includes:
A ROM data reading unit for reading data stored in the ROM;
A ROM data storage unit for storing ROM data read by the ROM data reading unit;
A data comparison unit for comparing the ROM data stored by the ROM data storage unit with external data input from the outside;
A comparison result output unit for outputting the result of data comparison by the data comparison unit to the outside;
A semiconductor device comprising:   The semiconductor device according to claim 1, further comprising: an external data reading unit that reads external data; and an external data storage unit that stores external data read by the external data reading unit. The ROM data reading unit reads the ROM data for each address, and the ROM data storage unit stores the read ROM data for a plurality of addresses, and the external data reading unit stores the external data for each address. The external data storage unit stores the read external data for a plurality of addresses,
The data comparison unit compares the ROM data for a plurality of addresses stored in the ROM data storage unit with the external data for a plurality of addresses stored in the external data storage unit. Semiconductor device. The ROM data reading unit reads the ROM data for each of a plurality of addresses, and the ROM data storage unit stores the read ROM data for a plurality of addresses, and the external data reading unit stores the external data for each of a plurality of addresses. The external data storage unit stores the read external data for a plurality of addresses,
The data comparison unit compares the ROM data for a plurality of addresses stored in the ROM data storage unit with the external data for a plurality of addresses stored in the external data storage unit. Semiconductor device.   A data supply unit that extracts ROM data for a plurality of addresses stored in the ROM data storage unit and external data for a plurality of addresses stored in the external data storage unit for each address and supplies them to the data comparison unit. 5. The semiconductor device according to claim 4, wherein the data comparison unit compares the ROM data for one address supplied by the data supply unit with the external data for one address. 5. The apparatus according to claim 4, further comprising: an address determining unit that determines an address of data read by each input terminal when the ROM data reading unit and the external data reading unit read data using a plurality of input terminals. Or the semiconductor device according to 5;

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