JP2002099504A - Data transfer unit and data transfer method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transfer unit capable of transferring proper graphic data to an image processing equipment like a printer in a case that a large amount of data are transferred by another bus master in a computer system using a bus shared with another bus master. SOLUTION: This data transfer unit is characterized in that it is equipped with a line data input section, a buffer for plural line data, a means for detecting free space that detects buffers having free spaces more than a prescribed value in buffers for above described plural line data, a means for data storage that stores line data to the buffer detected by the means for detecting free space, and a means for data output that outputs line data in order of storage from a line buffer finished storing of line data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device used to output a large amount of data such as image data from a main memory to an image processing device such as a printer via a bus in a computer system. .

[0002]

2. Description of the Related Art Conventionally, when image data stored in a main memory in a computer system is transferred to a printer via a PCI bus which is a general-purpose bus, the above-described printer is used. , A method of sequentially transferring image data for one line, which is a processing unit, in synchronization with a line synchronization signal.

[0003] The PCI bus is also used for data transfer by a bus master other than the printer. Therefore, when the amount of data transferred by another bus master is large, transfer of image data for one line may not be completed before the rising timing of the next line synchronization signal (a so-called underrun state). In this case, the printer cannot perform appropriate print processing.

According to the present invention, even if the amount of data transferred by another bus master is large in a computer system using a bus shared with another bus master, it is possible to provide an image processing apparatus such as a printer with an appropriate device. It is an object of the present invention to provide a data transfer device capable of transferring image data.

[0005]

According to a first data transfer apparatus of the present invention, a line data input section, a plurality of line data buffers, and a plurality of line data buffers having a predetermined value or more. Empty detecting means for detecting a buffer having an empty area, data storing means for storing line data in the buffer detected by the empty detecting means, and a line buffer storing the line data. Data output means for outputting data.

According to a second data transfer device of the present invention, in the first data transfer device, the empty detecting means includes:
It is characterized by detecting that the line data buffer is completely empty.

A third data transfer device according to the present invention is the first data transfer device, further comprising a data buffer for storing burst-transferred data at an input of the line data, and The detecting means detects a buffer having a free area larger than the data transferred in burst from the buffer for line data,
The data storage means stores burst data stored in a data buffer of the input unit in a buffer detected by the empty detection means.

A fourth data transfer device according to the present invention is the first data transfer device, further comprising a selection means for selecting a size of a free area detected by the free space detection means, Is characterized by detecting a buffer having a free area of the size selected by the selection means from among the plurality of line data buffers.

In a first data transfer method according to the present invention, the input line data is sequentially stored in a plurality of line data buffers, and the line data is transferred in the storage order. Out of the line data buffers, a first step of detecting a buffer having a free space equal to or larger than a predetermined value, and a second step of storing the input line data in the detected buffer.

A second data transfer method according to the present invention is the first data transfer method, wherein a completely empty buffer is detected from the plurality of line data buffers in the first step. It is characterized by the following.

A third data transfer method according to the present invention is the first data transfer method described above, further comprising a step of temporarily storing the line data burst-transferred in a data buffer. Among the buffers for the line data, a buffer having a free area larger than the data transferred in burst is detected, and in the second step, the buffer detected by the free space detecting means is stored in the data buffer. The stored burst data is stored.

A fourth data transfer method according to the present invention is the first data transfer method, further comprising a step of selecting a size of a vacant area detected by the vacancy detecting means. And detecting a buffer having a free area of the selected size from among the plurality of line data buffers.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (1) Embodiment 1 Hereinafter, a data transfer system of the present invention will be described in order with reference to the accompanying drawings. FIG. 1 shows a computer system 100 including a data transfer device 4 according to the first embodiment.
FIG. The RAM 2 stores necessary image data. This image data is read from the PCI target 3 line by line, and at a predetermined timing, the PCI bus 1
Is transferred to the data transfer device 4 via the. As described in detail below, the data transfer device 4 includes two line buffers A12 and B15 (see FIG. 2). The data transfer device 4 converts one line of image data input via the PCI bus 1 first. After the image data is stored in the line buffer A12, the image data for the next one line starts to be stored in the line buffer B15, and the data stored in the line buffer A12 is synchronized with the input line synchronization signal LC. Output to the printer 5 connected to the subsequent stage. After storing the line data in the line buffer B15,
Waiting for the end of the data reading from the line buffer A12, the image data for the next one line is transferred to the line buffer A12.
At the same time, the data stored in the line buffer B15 is output to the printer 5 in synchronization with the next line synchronization signal LC. Thereafter, the data transfer device 4 stores the data in the line buffer after the data reading is completed,
The output of the data from the line buffer to the printer 5 after storing the data in synchronization with the line synchronization signal LC is repeatedly performed.

It should be noted that another PCI device 6 is connected to the PCI bus 1. The PCI device 6 transfers necessary data from the RAM 2 via the PCI bus 1 asynchronously with the line synchronization signal LC output from the printer 5.

FIG. 2 is a diagram showing the configuration of the data transfer device 4. The PCI control circuit 10 functions as a bus master, and reads data at an address specified by the DMA 11 from the RAM 2. The DMA 11 transfers the read data to the line buffer A12 and the line buffer B15.
And a predetermined control signal to the line buffer A12, the data input counter A13, the line buffer B15, and the data input counter B16, as described in detail below.

The data input counter A13 and the data input counter B16 set the number of data (the number of words) for one line to be transferred in accordance with the input of the set signal from the DMA 11. The count value is input to the line buffer A12 and the line buffer B15 as a data input address, and is counted down every time one word of data is input to the line buffer A12 and the line buffer B15. When the count value becomes 0, the data input counter A13 and the data input counter B16 output a count end signal to the DMA 11.

The count values of the data output counters A14 and B17 are cleared to 0 in response to a reset signal input from the DMA 11 at the start of data transfer. In the data output counter A14 and the data output counter B17, the number of data (the number of words) for one line to be transferred is set in synchronization with the line synchronization signal LC input from the printer 5. Data output counter A
14. The data output counter B17 has a line buffer A
12, a line buffer B15, which is inputted as a data output address to a line buffer A12, a line buffer B
Each time data of one to 15 words is output, it is counted down. When the count value becomes 0, the data output counter A14 and the data output counter B17 output an end signal to the DMA 11.

The MUX (multiplexer) 18 outputs the data output from the line buffer A12 or the line buffer B15 to the printer 5 as one continuous serial or continuous parallel image data S.

FIG. 3 is a time chart showing the relationship between the line synchronization signal LC at the time of actual data reading and the line data input / output to / from the line buffer A12 and the line buffer B15. Hereinafter, data processing in the data transfer device 4 having the above configuration will be sequentially described with reference to the chart of FIG.

In the data transfer device 4, a line synchronization signal LC (arrow 40) two lines before the data is actually output is output.
) Is set to start data processing in synchronization with the data processing. The number of lines before which the line transfer signal LC starts the data transfer process may be directly settable by the CPU of the computer system 100 (not shown).

The DMA 11, which has received the line data read from the RAM 2 from the PCI control circuit 10, first outputs an input enable signal A to a line buffer A12, and outputs a set signal to a data input counter A13 and a data input counter B16. , Data output counter A1
4. A reset signal is output to the data output counter B17. Data output counter A with reset count value
14, the data output counter B17 outputs the end signal to the DMA
11 is output.

The line buffer A12 stores the line data input via the DMA 11 at the address (count value) input from the data input counter A13 in response to the input of the enable signal A (indicated by an arrow 41). . When data for one line is input and the count value representing the address becomes 0, the data input counter A13
Outputs an end signal to the DMA 11. DMA 11
The input enable signal A is switched to the disable signal A according to the input of the end signal. On condition that the input enable signal A is switched to the disable signal A, the line buffer A12 synchronizes with the line synchronizing signal LC (indicated by the arrow 45) and outputs the data output counter A14.
Is set, and the line data stored at the address (counter value) input from the data output counter A14 is output (indicated by an arrow 46).

The DMA 11 outputs a set signal to the data input counter B16 upon receiving the output of the end signal from the data output counter B17 when the end signal is input from the data input counter A13. The input enable signal B is output to the line buffer B15.

The line buffer B15 stores the line data input via the DMA 11 at the address (count value) input from the data input counter B16 in response to the input of the input enable signal B (arrows 42 and 4).
4). When data for one line is input and the count value representing the address becomes 0, the data input counter B
16 outputs an end signal to the DMA 11. DMA11
Switches the input enable signal B to the disable signal B in response to the input of the end signal. On condition that the input enable signal B is switched to the disable signal B, the line buffer B15
(Shown by an arrow 48) in synchronization with the data output counter B
17 is set, and the line data stored at the address (counter value) input from the data output counter B17 is output (indicated by an arrow 49).

The DMA 11 outputs a set signal to the data input counter A13 in response to the end signal being output from the data output counter A14 on condition that the end signal is input from the data input counter B16. In addition, an input enable signal A is output to the line buffer A12. When the DMA 11 receives the end signal from the data input counter B16 and has not yet output the output signal from the data output counter A14, the DMA 11 determines that the line buffer A12 is not empty, and
It instructs the I control circuit 10 to wait for reading of the next line of image data.

As described above, in the data transfer device 4,
When one line of data is alternately stored in two line buffers, the data is output alternately. However, when outputting the data, be sure to confirm that the storage of one line of data has been completed before the line data is output. Perform output. This allows, for example,
If the DMA 11 cannot receive all the data for the next one line during one cycle of the line synchronization signal LC, it prevents output of incomplete line data.

(2) Embodiment 2 The data transfer device 4 according to Embodiment 1 described above waits, for example, for the data stored in the line buffer A12 to be completely output, and then, The storage of the data of the (second) line to be output from the line buffer A12 has been started. The data transfer device 4 ′ according to the second embodiment, when the line data is output to the other line buffer B <b> 15 and the line data is output, if there is a free space in the line buffer A <b> 12, It is characterized in that the input of the line data is performed. By employing this configuration, the data transfer efficiency is further improved and the occurrence of underrun is effectively prevented.

FIG. 4 is a diagram showing a configuration of a data transfer device 4 'according to the second embodiment. The same components as those of the data transfer device 4 according to the first embodiment are denoted by the same reference numerals, and description thereof will not be repeated. When the count values of the data output counters A14 and B17 are smaller than the count values of the data input counters A13 and B16 by a predetermined value or more,
The data write enable signal is output to the DMA 11. On the other hand, the subtracters 20 and 21 are provided with a data output counter A1.
4. If the count value of the data output counter B17 is not smaller than the count value of the data input counters A13 and B16 by the predetermined value or more, a data write inhibit signal is output to the DMA11. The predetermined value used for determining whether the subtractors 20 and 21 output the data write enable signal or the inhibit signal may be arbitrarily set by the CPU of the computer system 100 (not shown).

The DMA 11 responds to the input of the data write enable signal from the subtracter 20 by the line buffer A1.
It is determined that there is an empty area in 2 and an input enable signal A is output to the line buffer A12. Similarly, the DMA 11 determines that there is an empty area in the line buffer B15 in response to the input of the data write enable signal from the subtracter 21, and outputs an input enable signal B to the line buffer B15. The line buffer A12 or the line buffer B17 stores the data input counter A1 in response to the input of the input enable signal A or B.
3, or write data to the address specified by the data input counter B16.

When data writing progresses and a data write inhibit signal is input from the subtractor 20, the DMA 11
Outputs the disable signal A to the line buffer A12 to continue outputting the interrupted data. Thereafter, writing and reading of data to and from the line buffer A12 are repeatedly performed. Similarly, the subtracter 21
When a data write inhibit signal is input from the
1 indicates that the line buffer B15 has the disable signal B
Is output, and the output of the interrupted data is continued. Thereafter, writing and reading of data to and from the line buffer B15 are repeatedly performed.

It is to be noted that, for example, when data writing and reading are repeatedly performed on the line buffer A12, and when the output of the line data stored in the line buffer A12 is completed, When the count value of the counter A14 becomes 0, the line buffer B15 stores the line data stored in synchronization with the line synchronization signal LC while the data is written in the empty area formed when the data is output. Start output of Thus, the line data is output in the order of storage in the line buffer.

By adopting the above configuration, it becomes possible to quickly store the line data to be input next to the output address in the line buffer. As a result, more rapid writing of line data to the line buffer A12 and the line buffer B15 is realized, and the occurrence of underrun can be effectively suppressed.

FIG. 5 is a time chart showing the relationship between the line synchronization signal LC at the time of actual data reading in the data transfer device 4 'and line data input / output to / from the line buffers A12 and B15.

Similarly to the data transfer device 4 described above, the data transfer device 4 'starts data processing in synchronization with the line synchronization signal LC (indicated by an arrow 60) two lines before the data is actually output. I do. From the PCI control circuit 10,
DM receiving the line data read from RAM 2
A11 first outputs an input enable signal A to the line buffer A12, outputs a set signal to the data input counters A13 and B16, and outputs a reset signal to the data output counters A14 and B17. The data output counters A14 and B17 whose count values have been reset (set to 0) output an end signal to the DMA 11.

In response to the input of the enable signal A, the line buffer A12 sequentially stores the line data input via the DMA 11 in the address (count value) input from the data input counter A13 (indicated by an arrow 61). ). When the data for one line is stored and the count value indicating the address becomes 0, the data input counter A13
Outputs an end signal to the DMA 11. DMA 11
The input enable signal A is switched to the disable signal A according to the input of the end signal. On condition that the input enable signal A is switched to the disable signal A, the line buffer A12 synchronizes with the line synchronization signal LC (indicated by an arrow 65) and outputs the data output counter A14.
Is set, and the line data stored at the address (counter value) input from the data output counter A14 is output (indicated by an arrow 66).

When the DMA 11 receives the end signal from the data output counter B17 when the end signal is input from the data input counter A13, the DMA 11 outputs a set signal to the data input counter B16. The input enable signal B is output to the line buffer B15.

In response to the input of the input enable signal B, the line buffer B15 sequentially stores addresses (count values) input from the data input counter B16 in the DMA 11
Stores the line data input through the arrow (arrow 6)
2, 64). When one line of data is stored and the count value indicating the address becomes 0, the data input counter B 16 outputs an end signal to the DMA 11. DM
A11 switches the input enable signal B to the disable signal B in response to the input of the end signal. On condition that the input enable signal B is switched to the disable signal B, the line buffer B15 sets the data output counter B17 in synchronization with the line synchronizing signal LC (indicated by an arrow 68). The line data stored at the input address (counter value) is output (indicated by an arrow 69).

When the storing of data in the line buffer B15 is completed and an end signal is output from the data input counter B16, the DMA 11 switches the enable signal B input to the line buffer B15 to a disabled state, and inputs data. When the counter A13 is set,
When the data write enable signal is input from the subtractor 20, the input enable signal A is output to the line buffer A12, and input of the next line data to be input is started (indicated by an arrow 67).

As described above, the data transfer device 4 '
For example, when the storage of the line data in the line buffer B15 is completed, even if the line buffer A12 is outputting data, the next line data is stored in a free address generated by the output of the data. . By adopting this configuration, quicker storage of line data in the line buffer is realized, and occurrence of underrun can be effectively prevented.

(3) Embodiment 3 In the data transfer device 4 'according to Embodiment 2, the line buffer A12 and the line buffer B15 are
The output of the data and the storage of the data in a free address formed by the output of the data are alternately performed. Since the output of the line data needs to be performed within one cycle of the line synchronization signal LC, the data output process is naturally given priority. However, when data input via the PCI bus 1 is burst-transferred, the data output processing is delayed until the transfer processing is completed.

To solve the above problem, the data transfer device 4 ″ according to the third embodiment uses a DMA transfer as shown in FIG.
A data buffer 30 for storing burst data is provided at a stage subsequent to 11. When the count values of the data output counter A14 and the data output counter B17 are smaller than the count values of the data input counters A13 and B16 by at least the burst data, the subtractors 20 and 21 output the data write enable signal. Is output to the DMA 11. On the other hand, the subtractors 20 and 21
Are data output counter A14, data output counter B
17 is greater than the count values of the data input counters A13 and B16 by the burst data or more, the data write inhibit signal is set to D.
Set to output to MA11. Other configurations are
This is the same as the data transfer device 4 'according to the second embodiment.

The data transfer device 4 ″ holds the burst data in the buffer 30 and outputs the burst data at a high speed at the time of writing the data, thereby shortening the time required for the burst transfer and increasing the data transfer efficiency. This ensures that one line of data is output within one cycle of the line synchronizing signal, and that line data is more quickly stored in the line buffer, thereby effectively preventing the occurrence of underrun. I do.

(4) Fourth Embodiment A data processing device 7 according to a fourth embodiment is based on a selection signal output from a CPU of a computer system 100 (not shown). , A data transfer method executed by the data transfer device 4 ′ according to the second embodiment, and
The line buffer A is simply synchronized with the line synchronization signal LC.
12. Data is alternately input to the line buffer B15,
In addition, a mechanism is adopted in which one data transfer method is selected from the data transfer methods that alternately output data, and the data transfer method is selectively operated.

FIG. 7 is a diagram showing a configuration of the data transfer device 7 according to the fourth embodiment. Embodiments 1 and 2 described above
The same components as those of the data transfer devices 4 and 4 'according to the first embodiment are denoted by the same reference numerals, and description thereof will not be repeated.

The selection circuit 40 has a line synchronization signal LC,
The end signal output from the data output counter A14 and the data write enable / disable signal output from the subtractor 20 are input. The selection circuit 40 outputs one of the three signals according to a selection signal output from a CPU (not shown).
Are output to the DMA 11.

Specifically, when functioning as the data transfer device 4 according to the first embodiment, the end signal output from the data output counter A14 is output to the DMA11. When functioning as the data transfer device 4 ′ according to the second embodiment, the data write enable / disable signal output from the subtractor 20 is transmitted to the DMA 11.
Output to When the line data read by the PCI control circuit 10 is simply stored / output in the line buffer A12 in synchronization with the line synchronization signal LC, the line synchronization signal LC is output to the DMA11.

Similarly, the selection circuit 41 has a line synchronization signal LC, an end signal output from the data output counter B16, and a data write enable / disable output from the subtractor 21.
A prohibition signal is input. The selection circuit 41 includes a C (not shown)
A signal of the same type as that of the selection circuit 40 is output to the DMA 11 among the three signals according to the selection signal output from the PU. Specifically, when functioning as the data transfer device 4 according to the first embodiment, the end signal output from the data output counter B16 is output to the DMA 11. Further, when functioning as the data transfer device 4 ′ according to the above-described second embodiment, a data write enable / disable signal output from the subtractor 21 is output to the DMA 11.

When the line data read by the PCI control circuit 10 is simply stored / output in the line buffer B 15 in synchronization with the line synchronization signal LC, the line synchronization signal LC is output to the DMA 11. In this case, D
MA11 responds to the input line synchronization signal LC,
An input enable signal is output to one of the line buffers A12 and B15, and a disable signal is output to the other. For example, when an input enable signal is output to the line buffer A12, the data input counter A
13 to write a line data by transmitting a set signal to the line buffer B15. On the other hand, the line buffer B15 sets the data output counter B17 in synchronization with the line synchronization signal LC input from the other side, and outputs the stored data.

In the data transfer device 7 having the above configuration, the CPU
, The data transfer method executed by the data transfer device 4 of the first embodiment, the data transfer method executed by the data transfer device 4 ′ of the second embodiment, or the PCI
The data transfer method for outputting the line data read by the control circuit 10 simply in synchronization with the line synchronization signal LC can be selected and executed. By adopting this configuration, for example, after first storing the line data in the line buffer A12 and the line buffer B15 in synchronization with the line synchronization signal, the data transfer device 4 of the first embodiment or the data of the second embodiment is stored. It becomes possible to function as the transfer device 4 '. When transferring color image data, it is also possible to adopt a different data transfer method for each color. Note that a configuration in which the data transfer method is switched according to a selection signal from the printer 5 connected at the subsequent stage may be adopted.

[0050]

The first data transfer device of the present invention, and
According to the data transfer method, even when the line data is discretely input to the input unit, the data is read after the line data is completely stored in the line buffer. As a result, the line data in the discrete state can be output after returning to the original continuous state,
It is possible to prevent the device that processes the line data from causing a malfunction.

According to the second data transfer apparatus and data transfer method of the present invention, even when line data is discretely input to the input section, the line data is completely stored in the line buffer. After that, data reading is performed. As a result, the line data in the discrete state can be output after returning to the original continuous state, and it is possible to prevent an apparatus that processes the line data from malfunctioning.

According to the third data transfer device and data transfer method of the present invention, line data to be burst-transferred can be stored in the line buffer more quickly by using the data buffer. As a result, it is possible to reduce the time for returning the discrete line data to the original continuous state.

According to the fourth data transfer device and the data transfer method of the present invention, the timing of writing data to the line buffer can be adjusted according to the use situation. Even when the line data is discretely input to the input unit, the data is read after the line data is completely stored in the line buffer.
As a result, the line data in the discrete state can be output after returning to the original continuous state, and it is possible to prevent an apparatus that processes the line data from malfunctioning.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a computer system including a data transfer device according to a first embodiment.

FIG. 2 is a configuration diagram of a data transfer device according to the first embodiment.

FIG. 3 is a timing chart illustrating input / output of data to / from a line buffer in the data transfer device.

FIG. 4 is a diagram showing a configuration of a data transfer device according to a second embodiment.

FIG. 5 is a timing chart illustrating input / output of data to / from a line buffer in the data transfer device.

FIG. 6 is a diagram showing a configuration of a data transfer device according to a third embodiment.

FIG. 7 is a diagram showing a configuration of a data transfer device according to a fourth embodiment.

[Explanation of symbols]

1 PCI bus, 2 RAM, 3 PCI target,
4 data transfer device, 5 printer, 10 PCI control circuit, 11 DMA, 12, 15 line buffer, 1
3, 16 data input counter, 14, 17 data output counter, 18 MUX, 20, 21 subtractor, 4
0,41 selection circuit.

Claims (8)

[Claims] A line data input unit; a plurality of line data buffers; a vacancy detecting means for detecting a buffer having a vacant area equal to or greater than a predetermined value among the plurality of line data buffers; Data storage means for storing line data in the buffer detected by the empty detection means, and data output means for outputting line data in the storage order from the line buffer in which the storage of the line data has been completed. Data transfer device. 2. The data transfer device according to claim 1, wherein said empty detecting means detects that the buffer for line data is completely empty. 3. The data transfer device according to claim 1, further comprising: a data buffer for storing data burst-transferred to an input portion of said line data, wherein said empty detection means comprises: A buffer having a free area larger than the burst-transferred data among the buffers for data transfer. The data storage means includes a data buffer provided in the input unit for the buffer detected by the free space detection means. A data transfer device for storing the burst data stored in the memory. 4. The data transfer device according to claim 1, further comprising a selection unit that selects a size of a free area detected by the free space detection unit, wherein the free space detection unit includes the plurality of line data. A data transfer device for detecting a buffer having a free area of the size selected by the selection means among the buffers for use. 5. A line data transfer method for storing input line data in a plurality of line data buffers and outputting data in the order in which the line data is stored. A first step of detecting a buffer having a free space equal to or larger than a value; and a second step of storing the input line data in a buffer for the line data detected in the first step. Transfer method. 6. The data transfer method according to claim 5, wherein the first step detects a completely empty buffer among the plurality of line data buffers. 7. The data transfer method according to claim 5, further comprising a step of temporarily storing the line data that has been burst-transferred in a data buffer. And detecting a buffer having a free area larger than the burst-transferred data. In the second step, the burst data stored in the data buffer is compared with the buffer detected by the free space detecting means. Data transfer method to be stored. 8. The data transfer method according to claim 5, further comprising a step of selecting a size of a vacant area detected by the vacancy detecting means, wherein the first step includes a step of selecting a size of the plurality of line data. A data transfer method for detecting a buffer having a free area of the selected size out of the buffers.