JP4103463B2 - Image processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention The painting The present invention relates to an image processing apparatus, and more particularly to a technique for generating a production image and sound effect in a gaming machine such as a pachinko machine according to the game development status.
[0002]
[Prior art]
Conventionally, in a gaming machine such as a pachinko machine, a control device for controlling the progress of the game, an image processing device for generating an image such as a pattern according to the progress of the game, or a sound effect is generated. An acoustic control device and the like are incorporated. This type of device is configured as a so-called state machine, and the next operation state is determined according to the current operation state.
By the way, since there are many noise sources such as a motor for ball striking and a drive circuit for electric decoration inside the gaming machine, the semiconductor integrated circuit in each device configured as a state machine malfunctions, and the device is May hang up. Therefore, conventionally, this type of apparatus is provided with a function for returning from the hang-up state.
[0003]
Here, as a conventional technique for recovering from the hang-up state, there is a method of resetting a circuit state by so-called software processing (hereinafter referred to as software reset). According to this software reset, a CPU (Central Processing Unit) constituting the device issues a command for resetting the operation of an LSI (Large Scale Integration) that has fallen into a hang-up state, and an internal circuit of the LSI (for example, A state machine including flip-flops and registers is reset. As a software reset method, there are a method using a watchdog timer and a method of resetting when a hang-up is detected by reading a flag indicating that a hang-up has occurred.
[0004]
[Problems to be solved by the invention]
However, according to the above-described software reset, there is a problem that if there is a circuit that cannot be reset in part, the entire circuit is not reset, and the device cannot be recovered from the hang-up state. Further, since the CPU needs to detect that the internal circuit of the LSI has been hung up, the load on the CPU becomes heavy. Furthermore, when the interface circuit of the CPU falls into a hang-up state, the CPU cannot detect the hang-up of the LSI and cannot issue a command for resetting.
[0005]
The present invention has been made in view of the above circumstances, and can recover from a hang-up state by itself regardless of a method such as software reset. Painting An object is to provide an image processing apparatus.
[0006]
[Means for Solving the Problems]
In order to solve the above problems, the present invention has the following configuration.
That is, the invention described in claim 1 An image processing apparatus that operates as a state machine under the control of an external CPU and sequentially executes a read operation and a write operation, and corresponds to a first storage unit (for example, a memory 80 described later) that stores image data. And a second storage unit (for example, a component corresponding to a memory 230 described later) for temporarily storing the image data, and for display from the image data stored in the second storage unit When a start signal is supplied from an image data generation unit (for example, a component corresponding to an image data generation unit 23 described later) that generates image data, and the CPU, the image data stored in the first storage unit is stored. A data transfer unit (for example, a data to be described later) that transfers image data stored in the first storage unit to the second storage unit by reading and writing to the second storage unit. A component corresponding to the transfer module 210) and a stay time of a state in which the image data is written to the second storage unit after the data transfer unit finishes reading the image data from the first storage unit The data transfer unit determines whether the data transfer unit counts time (for example, components corresponding to an AND circuit 212G and a counter 212H described later) and whether the stay time of the state timed by the timekeeping means has reached a predetermined time. Judgment means (for example, a component corresponding to a comparator 212J to be described later) for judging whether or not it is in a hang-up state, and resetting the data transfer unit when the judgment result of the judgment means indicates a hang-up state Reset means (for example, an OR circuit 212A, which will be described later) A component) corresponding to 12B, characterized by comprising as hardware .
[0007]
According to the configuration of the present invention, when the state machine falls into the hang-up state, the hang-up state is grasped from the stay time of the same state by utilizing the fact that the stay time of the same state becomes long. That is, the staying time of the same state is measured by the time measuring means, and it is determined from the time spent staying by the determining means whether or not the state machine is in the hang-up state. When it is determined that the state is in the hang-up state, the state machine is reset by the reset means. In other words, according to this configuration, the state machine is reset on condition that the current state of the state machine does not shift to the next state within the scheduled time. Therefore, for example, the state machine can be returned from the hang-up state without an external operation such as software reset.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows a configuration example of a control circuit system used in a gaming machine such as a pachinko machine to which the semiconductor integrated circuit according to this embodiment is applied. In the figure, a CPU (Central Processing Unit) 10 controls the progress of a series of games. Depending on the development of the game, for example, the probability or jackpot that an attacker of a pachinko machine is fixed in an open state for a predetermined time. It has a function of determining the probability of occurrence. The CPU 10 is connected to an image processing unit 20 that controls a display device (CRT) 30 and a sound source 40 that drives a speaker 50.
[0012]
Connected to the CPU 10 is a ROM (Read Only Memory) 60 for storing a program relating to game control. Further, a RAM (Random Access Memory) 70 for storing temporary data generated in the process of game control is connected to a bus connecting the CPU 10 to the image processing unit 20 and the sound source 40 described above. . Further, the image processing unit 20 is connected to a ROM 80 for storing design material data (image data) to be displayed in accordance with the progress of the game, and control data related to display such as design enlargement / reduction processing. The image processing unit 20 and the ROM 80 constitute an image processing apparatus according to the present invention. Here, the image processing unit 20 generates image data of each frame in accordance with, for example, the NTSC (National Television Systems Committee) standard, and constitutes a semiconductor integrated circuit according to the present invention. The sound source 40 is compliant with the MIDI (Musical Instrument Digital Interface) standard, and generates an acoustic signal for producing a game under the control of the CPU 10.
[0013]
FIG. 2 shows the configuration of the image processing unit 20.
As shown in the figure, the image processing unit 20 functions as a state machine, and an image data generation unit including a CPU interface 21 incorporating a data transfer module 210, a CRT controller 22, and a memory (RAM) 230. 23, a pattern memory interface 26, an image memory (SDRAM) 27, and a color conversion unit 28, which are connected via a bus 29. The data transfer module 210 is connected to the memory 80 via the control bus 29A, the pattern memory interface 26, and a ROM interface 800 described later, and is connected to the memory 230 via the control bus 29B and a RAM interface 231 described later. . Further, a memory (SDRAM) 25 is connected to the image data generation unit 23 via a decompression processing unit 24. The CPU 10 described above is connected to the CPU interface 21, the display device 30 is connected to the CRT controller 22, and the memory 80 is connected to the pattern memory interface 26.
[0014]
Here, the operation of the image processing unit 20 will be briefly described. When displaying an image, under the control of the external CPU 10, the data transfer module 210 reads image control data (program data) and compressed image data from the external memory 80 via the pattern memory interface 26. To write to the memory 230. That is, control data and image data are transferred from the memory 80 to the memory 230. Among these, the image data is decompressed (expanded) by the decompression processing unit 24 and stored in the memory 25.
[0015]
The image data generation unit 23 reads the image data from the memory 25, performs processing according to the control data stored in the memory 230, generates display image data for one frame, and generates the image data for display via the bus 29. Write to. The display image data written in the image memory 27 is color-converted to an RGB image signal by the color conversion unit 28 and output to the display device 30. As described above, the image processing unit 20 functions as a state machine under the control of the CPU 10 and sequentially executes the read operation and the write operation, and causes the display device 30 to display an image.
[0016]
Next, FIG. 3 shows the configuration of the data transfer module 210. The data transfer module 210 is for transferring data read from the memory 80 to the memory 230 in the image data generation unit 23 at an appropriate timing. The FIFO 211, the FIFO controller 212, the address counters 213, 215, Comparators 214 and 216 are provided. The data transfer module 210 is connected to the memory 80 via the ROM interface 800 and is connected to the memory 230 via the RAM interface 231. In FIG. 3, the pattern memory interface 26 shown in FIG. 2 existing between the data transfer module 210 and the ROM interface 800 is omitted.
[0017]
Here, read data RDAT is input from the ROM interface 800 to the FIFO 211, and write data WDAT is output from the FIFO 211 to the RAM interface 231. The read data RDAT is control data or image data read from the memory 80. The write data WDAT has the same contents as the read data RDAT, and is control data or image data transferred by the data transfer module 210 and written to the memory 230. The read request signal RREQ is output from the FIFO controller 212 to the ROM interface 800, and the read data timing signal RDTIM is input from the ROM interface to the FIFO controller 212. On the other hand, the write request signal WREQ is output from the FIFO controller 212 to the RAM interface 231, and the write acknowledge signal WACK is input from the RAM interface 231 to the FIFO controller 212.
[0018]
A read acknowledge signal RACK is input from the ROM interface 800 to the address counter 213, and a read address signal RADR is output from the address counter 213 to the ROM interface 800. The above-described read address RADR is input to the comparator 214, and a read end signal REND is output from the comparator 214 to the ROM interface 800. On the other hand, the above-described write acknowledge signal WACK is input to the address counter 215, and the write address signal WADR is output from the address counter 215 to the RAM interface 231. The above-described write address WADR is input to the comparator 216, and the write end signal WEND is output from the comparator 216 to the RAM interface 231.
[0019]
Here, the operation of the data transfer module 210 will be described.
When transferring data (image data / control data), the FIFO controller 212 outputs a read request signal RREQ to the ROM interface 800. In response to this, the ROM interface 800 outputs a read acknowledge signal RACK to the address counter 213, and the address counter 213 sequentially generates the read address RADR using this as a trigger. At this time, the read data timing signal RDTIM is output from the ROM interface 800 corresponding to the read acknowledge signal RACK, and the read data RDAT is written into the FIFO 211 at the timing specified by the read data timing signal RDTIM. In this way, a read operation is performed, and data is transferred as read data RDAT from the memory 80 to the FIFO 211 via the ROM interface 800. The comparator 214 sequentially compares the read address RADR and the read end address REA, and outputs a read end signal REND when they match. When the read address RADR and the read end address REA match and all the data is transferred to the FIFO 211, a series of read operations is completed.
[0020]
On the other hand, the FIFO controller 212 outputs a write request signal WREQ to the RAM interface 231. In response to this, the RAM interface 231 outputs a write acknowledge signal WACK, and using this as a trigger, the address counter 215 outputs the write address signal WADR, and then increments. As a result, a write operation is performed, and data is transferred as write data WDAT from the FIFO 211 to the memory 230 via the RAM interface 231. The comparator 216 sequentially compares the write address signal WADR and the write end address WEA. When the write address signal WADR matches the write end address WEA, the write end signal WEND is output and a series of write operations is completed.
[0021]
Next, the FIFO controller 212 will be described.
FIG. 4 shows a part of the configuration of the FIFO controller 212. In this configuration, portions related to the present invention are extracted, and as shown in the figure, OR circuits 212A and 212B, RS-type flip-flops (FF) 212C, 212D, and 212K, and a signal generator 212E. 212F, an AND circuit 212G, a counter 212H, and a comparator 212J.
[0022]
This will be specifically described. The above-described read end signal REND and write end signal WEND are input to the OR circuits 212A and 212B, respectively, and a hangup flag HFLG, which will be described later, is input to these OR circuits. Further, the output signals of the OR circuits 212A and 212B are input to the reset terminals of the flip-flops 212C and 212D, respectively, and the start signal STR supplied from the CPU 10 is commonly input to the set terminals.
The output signal of the flip-flop 212C is supplied to the signal generator 212E as the read timing signal RTIM, and the output signal of the flip-flop 212D is supplied to the signal generator 212F as the write timing signal WTIM. Here, the signal generation unit 212E generates the read request signal RREQ according to the read timing signal RTIM and the presence / absence of an empty area in the above-described FIFO 211 or the ratio of the area where data is written, and the signal generation unit 212F The write request signal WREQ is generated according to the write timing signal WTIM and the presence or absence of data in the FIFO 211 or the ratio of the area in which the data is written.
[0023]
The AND circuit 212G has a negative logic input terminal and a positive logic input terminal. The read logic signal RTIM is input to the negative logic input terminal, and the write timing signal WTIM is input to the positive logic terminal. In this embodiment, the AND circuit 212G functions as a decoder, and functions as a detection unit that detects a state from the end of the read operation of the memory 80 to the end of the write operation of the memory 230. .
The output signal of the AND circuit 212G is input in common to the carry-in terminal (Ci) and the negative reset terminal (RN) of the counter 212H. The counter 212H is configured to start counting when a logical value “1” is input as an output signal of the AND circuit 212G, and to reset the count value when a logical value “0” is input. In this embodiment, the counter 212H functions as a time measuring means for measuring the stay time of the state detected by the AND circuit 212G.
[0024]
The output signal (count value CNT) of the counter 212H is supplied to one input terminal of the comparator 212J, and the predetermined value TMAX is supplied to the other input terminal of the comparator 212J. This predetermined value TMAX is the maximum time of the state from the end of the read operation from the memory 80 to the end of the writing of the memory 230, and is a value set in advance as the maximum value of the stay time of such a state It is. The comparator 212J outputs a signal having a logical value “1” as the hang-up flag HFLG when the count value CNT reaches the predetermined value TMAX. Thus, the comparator 212J functions as a determination unit that determines whether or not the hang-up state is present from the stay time counted by the counter 212H, and the determination result is output as the hang-up flag HFLG.
[0025]
The hang-up flag HFLG output from the comparator 212J is supplied to the above-described OR circuits 212A and 212B. In this embodiment, the OR circuits 212A and 212B function as reset means for resetting the state machine when the hangup flag HFLG output from the comparator 212J indicates that the state is in the hangup state. The hang-up flag HFLG is given to the set terminal of the RS flip-flop 212K, and a reset signal from the CPU 10 is given to the reset terminal. The output signal of the flip-flop 212K is supplied to the CPU 10 as an error flag EFLG.
[0026]
The operation of this embodiment will be described below along the flow shown in FIG. 6 with reference to the waveform diagram shown in FIG.
In the initial state, the image processing unit 20 is in an idle state, and the image processing unit 20 remains in an idle state until an event occurs (step S1; NO). When an event occurs in accordance with the progress of the game from the idle state and a series of operations starts under the control of the CPU 10 (step S2; YES), the data transfer module 210 in the image processing unit 20 is shown in FIG. The flip-flops 212C and 212D shown are set by the start signal STR from the CPU 10, and both the read timing signal RTIM and the write timing signal WTIM are set to the logical value “1” as shown in FIG.
[0027]
Subsequently, the signal generation unit 212E sets the logical value “1” as the read request signal RREQ when the condition that the FIFO 211 has an empty area and the read timing signal RTIM is the logical value “1” is satisfied. Output. One signal generation unit 212F outputs a logical value “1” as the write request signal WREQ if data exists in the FIFO 211 and the condition that the write timing signal WTIM is a logical value “1” is satisfied. . In response to this, the ROM interface 800 and the RAM interface 231 output the read acknowledge signal RACK and the write acknowledge signal WACK, respectively, and the read operation of the memory 80 and the write operation of the memory 230 are started (step S3).
[0028]
Subsequently, when the logical value “1” is output as the read end signal REND from the comparator 214 and the control data read operation from the memory 80 is completed (step S4; YES), only the write operation to the memory 230 is continued. (Step S5). Here, when a logical value “1” is input to the logical sum circuit 212A shown in FIG. 4 as the read end signal REND, the flip-flop 212C is reset by the output signal of the logical sum circuit 212A, and the logical value is read as the read timing signal RTIM. The value “0” is output. At this time, since the logical value “0” is held as the write end signal WEND and the flip-flop 212D is not reset, the flip-flop 212D is kept in the set state and the logical value “1” is maintained as the write timing signal WTIM. . For this reason, the AND circuit 212G outputs a logical value “1” as an output signal, thereby detecting that the current state of the state machine is a state in which the read operation is completed and the write operation is not completed. Is done.
[0029]
When a logical value “1” is output as an output signal of the logical product circuit 212G, the counter 212H starts a count operation using this as a trigger, and the time of staying in the current state is started. Here, normally, after the above-described read operation is completed, the write operation is also completed within a predetermined time, and a logical value “1” is output as the write end signal WEND. As a result, the flip-flop 212D is reset and a logical value “0” is output as the write timing signal WTIM, and a logical value “0” is output as the write request signal WREQ from the signal processing unit 212F that receives this. Further, the logical product circuit 212G outputs a logical value “0”, and the counter 212H stops counting. As a result, a series of write operations is completed, and the state machine shifts to the next state.
[0030]
On the other hand, when the flip-flop 212D is fixed to the set state by noise during the write operation, the write timing signal WTIM is fixed to the logical value “1”, and the write request signal WREQ is maintained at the logical value “1”. The For this reason, the write operation does not end in appearance, and a hang-up state occurs. In this case, since the counter 212H starts counting from the time when the logical product 212G outputs the logical value “1” (when the read operation is completed), the write timing signal WTIM maintains the logical value “1”. If so, the count continues and the time spent in the current state is timed.
[0031]
When the count value CNT reaches the predetermined value TMAX (“N” shown in FIG. 5), the comparator 212J outputs a logical value “1” as the hang-up flag HFLG (step S6; YES). In this case, since the output signals of the OR circuits 212A and 212B shown in FIG. 4 are forcibly set to the logical value “1” by the hang-up flag HFLG, the flip-flops 212C and 212D that input this to the reset terminal are forced. Reset automatically. As a result, as shown in FIG. 5, both the read timing signal RTIM and the write timing signal WTIM are set to the logical value “0” and returned to the initial state. As a result, the state machine returns from the hang-up state, and a series of control operations are restarted from the first state. The hangup flag HFLG is taken into the flip-flop 212K and supplied to the CPU 10 as an error flag EFLG. As a result, the CPU 10 can grasp later that the return from the hang-up has been performed inside the image processing unit 20, and can reflect it in the subsequent control as necessary.
[0032]
If the hang-up state does not occur in the write operation (step S5), the write timing signal is sent from the flip-flop 212D before the counter value CNT reaches the predetermined value TMAX (“N” shown in FIG. 5). Since the logic value “0” is output as WTIM, the output signal of the AND circuit 212G is set to the logic value “0”, and the count value CNT of the counter 212H is reset. Accordingly, in this case, the hang-up flag HFLG is maintained at the logical value “0”, the write request signal WREQ becomes the logical value “0” in response to the normal write end signal WEND, and the write operation ends normally (step S7; YES). After that, the state of the state machine becomes an idle state (step S1) and waits for the occurrence of a new event.
[0033]
As described above, according to this embodiment, the write operation time (stay state of the write state) of the memory 230 is counted, so that the hang-up of the FIFO controller 212 in this write operation can be grasped. And the FIFO controller 212 can be reset. Therefore, even if the FIFO controller 212 constituting the state machine is in a hang-up state during a game machine play, it is possible to return from this hang-up state and avoid a situation where the game is stopped due to the hang-up. It becomes possible.
In the above-described embodiment, the hang-up in the write operation is dealt with. However, the present invention is not limited to this, and the hang-up in any state may be dealt with.
[0034]
【The invention's effect】
As described above, according to the present invention Image processing device According to the above, the state machine's state is detected, the state stay time is counted, and it is determined whether or not the state machine is in the hang-up state based on the counted stay time. It is possible to return from the hang-up state by itself without resetting.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example of a control system of a gaming machine to which a semiconductor integrated circuit according to an embodiment of the present invention is applied.
FIG. 2 is a block diagram showing a configuration of an image processing unit configured as a semiconductor integrated circuit according to the embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration of a data transfer module according to the embodiment of the present invention.
FIG. 4 is a block diagram showing a configuration of a FIFO controller according to the embodiment of the present invention.
FIG. 5 is a waveform diagram for explaining the operation of the FIFO controller according to the embodiment of the present invention.
FIG. 6 is a flowchart showing a flow of operation of the image processing unit according to the embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 20 ... Image processing part, 21 ... CPU interface, 22 ... CRT controller, 23 ... Image data generation part, 24 ... Decompression processing part, 25 ... Memory, 26 ... Pattern memory, 27 ... Image memory, 28 ... Color conversion part, 29 ... bus, 29A, 29B ... control bus, 80 ... memory, 212 ... FIFO controller, 212A, 212B ... logical sum circuit, 212C, 212D, 212K ... flip-flop, 212E, 212F ... signal generator, 212G ... logical product circuit, 212H: Counter, 212J: Comparator.

Claims (1)

An image processing apparatus that operates as a state machine under the control of an external CPU,
A first storage unit for storing image data;
An image data generation unit that has a second storage unit for temporarily storing the image data, and generates display image data from the image data stored in the second storage unit;
When a start signal is supplied from the CPU, the image data stored in the first storage unit is read out and written into the second storage unit, whereby the image data stored in the first storage unit is read out. A data transfer unit for transferring to the second storage unit;
Timing means the data transfer unit that measures after completion of the reading of the image data, the residence time of the second row cormorants state to write image data in the storage unit from the first storage unit,
Determining means for determining whether or not the data transfer unit is in a hang-up state depending on whether or not the stay time of the state timed by the time measuring means has reached a predetermined time ;
Resetting the data transfer unit to indicate that the determination result of said determination means is hung-up state, and reset means to restart the series of operations to return to the initial state,
An image processing apparatus comprising: as hardware.

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