JP2003506909A - PLL Noise Smoothing Using Interleaving by Dual Modulus - Google Patents

Abstract

(57) [Summary] In general, the present invention realizes signal dispersion in a PLL using a plurality of modulus prescalers by interleaving modulos to be divided. Within a given cycle, "1st place" and "10th place" are not all counted consecutively, but "1st place" and "10th place" are interleaved instead. In one embodiment according to the present invention, the R count is doubled and the output of the R counter alternates between a high state and a low state in a toggle fashion (the Q counter may remain unchanged). ). In another embodiment according to the present invention, “1st” and “10th” are interleaved according to the ratio of q: r. By interleaving the modulus in this way, it is possible to obtain an effect of spreading the noise generated by the output signal of the dual modulus prescaler over a wider frequency band. The noise level of the prescaler can be significantly reduced, especially in the frequency band of the reference frequency.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD OF THE INVENTION

  The present invention relates to phase locked loops (PLLs).

[0002]

[Prior art]

In fact, all modern signal generators and wireless communication devices have widespread applications for PLLs. A known PLL is shown in FIG. Reference frequency f _in is provided to the phase detector or phase / frequency detector, which is applied to a feedback signal derived from the output frequency signal f _{o ut} of the PLL. The detector produces an error signal, which is filtered by the loop filter. The output of the loop filter is
Applied to a voltage controlled oscillator (VCO), an output signal f _out is generated. In general, a programmable divide-by-N counter divides the output frequency signal f _out to generate a lower frequency signal and applies this signal to a detector. In this way, the output signal can be generated by multiplexing several frequencies. Such N frequency division counter is typically realized by CMOS.

However, at very high frequencies (such as those used in mobile phones), even with the speed capabilities of high speed CMOS circuits, their speed is excessive. In this case, a dual-modulus prescaler (dual-modulus) such that the difference between one division modulus (P) and the other division modulus (P-1) is 1. prescaler) is used. In such a configuration as shown in FIG. 2, a high speed (eg ECL) dual modulus counter is followed by a low speed (eg CMOS) programmable counter. The low speed counter controls which of the dual-modulus prescalers is active at a given time via the modulus control signal MC. By using a large number of moduli, it is possible to obtain effective divisors in a wide range.

[0004]   One configuration of such a circuit is shown in FIG. Here is a dual modus coun
Followed by a pair of low speed (eg CMOS) programmable counters.
It is arranged. In the circuit of FIG. 3, the reference frequency and output frequency are as follows.
It is a relationship. f_out= Nf_in = (QP + R) f_in = ((Q-R) P + R (P + 1)) f_in   Where Q is the quotient of N / P integer division, and R is N / P.
It is the remainder of the integer division of P. The value of Q is (so-called, the result is modular P
Used to preset the "tens" counter, where R is
Preset the "ones" counter (the result is not multiplied by the modulus)
Used to do. The value of Q must be greater than or equal to the value of R. To this limit
Is the smallest fraction that can guarantee a contiguous range of possible integer divisors N.
The division ratio is generally P (P-1).

For example, assume that a 10/11 dual modulus prescaler (P = 10) is used and the desired output frequency is 197 times the reference frequency. Using the above equation, Q can be 19 and R can be 7 (note that R <P always). These values are preset in the respective counters. At the start of the cycle, (P-1
), The dual-modulus prescaler is set. (The duration of the cycle is given by the reciprocal of the reference frequency.) The output of the dual modulus prescaler steps both counters. When the R counter reaches zero, it stops counting and the dual modulo prescaler
Set to divide by P. Then only the Q counter is incremented. Such a cycle is shown in FIG. When the Q counter reaches zero, the counter is reloaded with the initial value and the next cycle begins.

In such a circuit, since the period of the modulus control signal is the same as the period of the PLL reference signal, the modulus control signal for controlling the dual modulus prescaler has a considerable noise within the frequency band of the reference frequency. May occur. As shown in FIG. 3, it can be coupled by parasitic capacitance to the VCO input, resulting in frequency jitter. In addition, similar noise, which may cause variations in the prescaler input impedance, is input to the dual-modulus prescaler and V
Frequency pulling due to CO occurs. In order to reduce the frequency pull-in, as shown by the broken line in FIG. 3, the VC to the dual-modulus prescaler is
The O output signal may be buffered. With such buffering,
Size and complexity are added to the PLL. Various filter strategies have been used to solve this noise problem. An effective and low cost solution to this problem has long been a challenge.

[0007]

[Outline of the Invention]

Broadly speaking, the present invention implements signal dispersion in a PLL that utilizes multiple modular prescalers by interleaving the divided moduli. Within a given cycle, all "1st" and "10th" are not counted consecutively, instead "1st" and "10th" are interleaved.
In one embodiment of the invention, the R count is doubled and the output of the R counter alternates between high and low states (the Q counter may be left unchanged). ). In another embodiment of the present invention, "1st place" and "10th place" are interleaved according to the ratio of q: r. By interleaving the moduli in this way, it is possible to obtain the effect of diffusing the noise generated by the output signal of the dual-modulus prescaler over a wider frequency band. The noise level of the prescaler can be significantly reduced, especially in the frequency band of the reference frequency.

[0008]

Detailed Description of the Preferred Embodiments

The modulo interleaving method of the present invention can be used in various forms by changing the degree of sophistication and complexity. FIG. 5 shows a simple but effective application of modulus interleaving. In this example, the Q count and Q counter are left unchanged. The R count is doubled and the R counter toggles in a toggle fashion. For example, an R counter typically counts by 2 when the counter output is held low at 15 counts.
Doubled to 30. Instead of being kept low continuously, the output of the counter alternates in a toggle fashion: low count 1 count, high count 1 count, low count 1 count ... Referring again to the above equation, the overall result is the same as the conventional case, and the result is that R should be replaced by 2R / 2. The difference is that the energy spectrum of the modulus control signal is shifted upwards,
It is away from the PLL reference frequency. If desired, Q may be done with the same measure. Generally, R (and Q if desired) is replaced by mR / m. Here, m is the number of prescaler moduli. In the dual-modulus prescaler, m = 2.

In other arrangements, it may be advantageous to be able to change the distribution of the pulses in the modulus control signal. Referring to FIG. 6, P according to another embodiment of the present invention.
The LL circuit is shown. Compared to the PLL circuit of FIG. 2, the R counter and Q
The counter has been modified by the addition of the r and q counters. As a result, the R counter counts r at one time, and counts R as a whole. Also,
As a result, the Q counter counts q at a time, and counts Q as a whole.
According to the illustrated embodiment, the device operates as follows.

As in the prior art circuit, the R counter is loaded with a non-zero value and at the beginning of the cycle the dual modulus prescaler is set to divide by (P + 1). The output from the dual modulus prescaler increments both counters. When the r counter reaches zero, the R counter stops counting and sets the dual modulus prescaler to divide by P. Then only the Q counter is incremented. When the q counter reaches zero, the initial value r
And q are again loaded into the counter and the next subcycle is started. During the last subcycle, the R counter counts down to zero and then the Q counter counts down to zero. (R, r) = (7,1) and (Q, q) =
Such an operation for the case of (8,1) is shown in FIG. It should be noted that r and q do not have to be 1, but merely satisfy the conditions of R ≦ Q, r ≦ R and q ≦ Q (where r = R and q = Q). The case represents a typical way of working).

The noise diffusion effect of this modulo interleaving technique can be observed by comparing FIGS. 8 and 9. FIG. 8 is a plot of the energy in the signal appearing on the modulus control line according to the typical modulus control setup of FIGS. 3 and 4. With the exception of zero hertz (Hz), the noise margin at the first noise peak is -5dbm. FIG. 9 is a plot of the energy in the signal appearing on the modulus control line according to the modular control setup according to the invention shown in FIGS. 6 and 7. With the exception of zero hertz, the noise margin at the first noise peak is -25dbm. Thus, this example demonstrates a 20 dB reduction in noise from the modulus control signal at the reference frequency, alleviating the noise problem experienced in the prior art. It should be noted that there are no additional components or extra filters required by this method. The increase in cost by incorporating the present invention basically does not occur. Furthermore, VCO
The need to buffer the output signal is mitigated or eliminated. Furthermore, it should be noted that this interleaving can easily be extended to good high-order multi-modulus prescaling, such as the 3-modulus prescaler and the 4-modulus prescaler.

Those skilled in the art will appreciate that the invention can be embodied in other specific forms without departing from the spirit or essence of the invention. The examples disclosed herein are
Therefore, all of them are considered to be illustrative and not restrictive. The scope of the present invention is shown not by the above description but by the appended claims, and all modifications that come within the meaning and range of equivalents thereof are included in the scope of the present invention.

[Brief description of drawings]

FIG. 1 is a block diagram of a typical PLL using a divide-by-N counter.

FIG. 2 is a typical PL using a dual-modulus prescaler.
It is a block diagram of L.

FIG. 3 is a more detailed block diagram embodying the circuit of FIG.

FIG. 4 is a timing diagram illustrating the operation of the PLL of FIG.

FIG. 5 is a diagram illustrating the principle of the present invention according to an embodiment of the present invention.

FIG. 6 is a block diagram of a PLL according to an embodiment of the present invention.

FIG. 7 is a timing diagram illustrating the operation of the PLL of FIG.

FIG. 8 is a waveform display showing a noise level using a typical PLL circuit.

FIG. 9 is a brush display showing a noise level using a PLL circuit according to the present invention.

─────────────────────────────────────────────────── ─── Continued front page    (81) Designated countries EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, I T, LU, MC, NL, PT, SE), OA (BF, BJ , CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, GM, K E, LS, MW, MZ, SD, SL, SZ, TZ, UG , ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, BZ, C A, CH, CN, CR, CU, CZ, DE, DK, DM , DZ, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, K E, KG, KP, KR, KZ, LC, LK, LR, LS , LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PL, PT, RO, R U, SD, SE, SG, SI, SL, TJ, TM, TR , TT, TZ, UA, UG, US, UZ, VN, YU, ZA, ZW (72) Inventor McCune Earl W             near             United States California             95050 Santa Clara Sutter Abe             New 2252 F term (reference) 5J106 PP03 QQ06 QQ08 RR18

Claims (8)

[Claims] 1. A method of operating a plurality of modulus prescalers having at least a modulus P and controlled by counting the transitions of an applied frequency signal, the method comprising: dividing N / P (where desired) Output frequency of N is N times the input reference frequency) and at least one of the integer part Q and the remainder part R is determined, and the maximum count number provided in the state where the modulus control signal is applied is smaller than R. And, alternating at least a portion of the modulus control signal between a high state and a low state. 2. The method of claim 1 further comprising alternating modulo control signals on a count-by-count basis between the states. 3. Operates by calculating the transition of the applied frequency signal,
A plurality of modular prescalers and associated control circuitry, including a first counter for counting transitions of an applied frequency signal, including means for storing a first preset count, and a second preset count A second counter for counting the transitions of the applied frequency signal, including means for controlling, wherein at least one counter produces an output signal that transitions multiple times during the counting of the preset count. Prescaler and control circuit. 4. A method of operating a plurality of modulus prescalers, the method comprising: on a cycle basis, controlling a selection between at least a first modulus and a second modulus, wherein the prescaler comprises a first cycle of the cycle. In the first part, the applied frequency signal is divided by the first modulus, and in the second part of the cycle, the applied frequency signal is divided by the second modulus, on a sub-cycle basis. Controlling a selection between at least a first modulus and a second modulus, and over a sub-cycle, the prescaler divides the applied frequency signal by the first modulus in the first part of the sub-cycle. And
A method of dividing the applied frequency signal by a second modulus in a second portion of the cycle. 5. The method of claim 4, wherein the cycle has multiple sub-cycles. 6. A method of operating a phase locked loop having a plurality of modulus prescalers for receiving a reference frequency and generating an output frequency, the method comprising: a first modulus for a predetermined output signal during the period. Is used,
Determining a portion of the first period, defined by the reciprocal of the input frequency, and a portion of the second period in which the second modulus is used, controlling the modulus, A method characterized in that a desired output frequency is obtained by changing the modulus multiple times. 7. A control circuit for a plurality of modular prescalers, comprising: a first counter that counts r at a time and counts R in total; and a count circuit that counts q at a time and Q in total. And a control circuit for sequentially and repeatedly selecting a first modulus for counting r, and a second modulus for counting q. . 8. A reference frequency signal, a detector connected to the reference frequency signal, a loop filter connected to the output signal of the detector, and a loop filter connected to the output signal of the loop filter to generate an output frequency signal. A frequency divider circuit for generating a feedback signal to be applied to a detector in response to a controlled oscillator and an output frequency signal, comprising a plurality of modulus prescalers, counting r at a time, and counting R in total 1 , A second counter for counting q at a time and a total of Q, a first modulus for counting r, and a second modulus for counting q And a control circuit for selecting the phase locked loop.