CN1371549A - PLL noise smoothing using dual-modulus interleaving - Google Patents
PLL noise smoothing using dual-modulus interleaving Download PDFInfo
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- CN1371549A CN1371549A CN00812059A CN00812059A CN1371549A CN 1371549 A CN1371549 A CN 1371549A CN 00812059 A CN00812059 A CN 00812059A CN 00812059 A CN00812059 A CN 00812059A CN 1371549 A CN1371549 A CN 1371549A
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- prescaling
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- 238000009499 grossing Methods 0.000 title description 2
- 238000000034 method Methods 0.000 claims description 11
- 230000007704 transition Effects 0.000 claims 5
- 238000004321 preservation Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 6
- 241001274660 Modulus Species 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 238000001914 filtration Methods 0.000 description 2
- 230000001413 cellular effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
- H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
- H03K23/667—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by switching the base during a counting cycle
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/193—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
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Abstract
The present invention, generally speaking, achieves noise spreading within a PLL using a dual-modulus prescaler by interleaving the division moduli. Within a given cycle, 'ones' and 'tens' are not all counted consecutively. Instead, ones and tens are interleaved. In one embodiment of the invention, the R count is doubled and the output of the R counter is toggled between high and low states. (The Q counter may remain unmodified.) In another embodiment of the invention, ones and tens are interleaved in accordance with a ratio q:r. By so interleaving the modulus, the effect is to spread the noise resulting from the output signal of the dual-modulus prescaler over a wider frequency range. The prescaler noise level is greatly reduced, particularly within the frequency band of the reference frequency.
Description
Technical field
The present invention relates to phase-locked loop (PLL).
Background technology
In fact, all modern signal generators and Wireless Telecom Equipment all are extensive use of PLL.Fig. 1 represents a kind of known PLL.With reference frequency f
InBe applied to phase place or phase/frequency detector, wherein will be according to the output frequency signal f of PLL
OutThe feedback signal that derives is applied to detector.Detector generates an error signal, utilizes loop filter filter error signal.The output signal of loop filter is applied to voltage-controlled oscillator (VCO), and the latter generates output frequency signal f
OutUsually, able to programmely divide output frequency signal f for one divided by the N counter
Out, to generate a low frequency signals that is applied to detector.Like this, generating one is the output frequency signal of reference frequency several times.Usually realize divided by the N counter with CMOS.
Yet, in very high frequency(VHF) (frequency of using in as cellular radio), the very fast speed ability of quick cmos circuit that surpasses.In this example, use antithesis modulus prescaling usually, one of them distributes modulus (P) and another to distribute the difference between the modulus (P-1) is 1.In structure shown in Figure 2, at a high speed (as, ECL) low speed of dual module counter heel is (as, CMOS) programmable counter.The low speed counter controls is via modulus control signal MC, and which modulus in the control antithesis modulus prescaling is effective in preset time.By using many moduluses, obtain the effective divisor in all scopes.
Fig. 3 represents a kind of structure of this type of circuit, and wherein a pair of low speed of antithesis counter heel is (as, CMOS) programmable counter.In the circuit of Fig. 3, the pass of reference frequency and output frequency is:
f＝N·f
in
＝(QP+R)f
in
=((Q-R) P+R (P+1)) f
InWherein Q is the merchant of dividing exactly N/P, and R is the remainder of dividing exactly N/P.Value Q is used to preset " ten " counter (so the reason of appellation is that its effect is to multiply by modulus P), and R is used to preset " one " counter (its effect is not to multiply by modulus).Value Q must be more than or equal to value R.By above restriction, be generally P (P-1) for guaranteeing the smallest scale ratio that covering continuously uses the possible integer divisor N of above circuit to realize.
For example, suppose and use 10/11 antithesis modulus prescaling (P=10), and required output frequency is 197 times of reference frequency.By using above-mentioned formula, Q can be 19, and R can be 7.(notice that R＜P always sets up.) above each value is preset in each counter.By a nonzero value is loaded in the R counter, at the beginning of the cycle, antithesis modulus prescaling is set to divided by P+1.(inverse by reference frequency is determined cycle period.) output of antithesis modulus prescaling is to two counter timing.When the R counter is zero, stop counting, and antithesis modulus prescaling is set to divided by P.Then only to the timing of Q counter.Fig. 4 represents this type of circulation.When the Q counter is zero, once more initial value is loaded in the counter, and next circulation beginning.
In above circuit, being used to control antithesis modulus prescaling modulus control signal may produce much noise in the frequency band of reference signal, and its reason is that the cycle of modulus signal equals the cycle of PLL reference signal.As shown in Figure 3, perhaps parasitic capacitance is imported this coupling noise to VCO, thereby causes frequency fluctuation.In addition, this noise is input in the antithesis modulus prescaling, can causes that the input impedance of prescaling changes, cause near the frequency pulling of VCO.Shown in the dotted line among Fig. 3,, can cushion and arrive the output signal that dual module is counted the VCO of prescaling in order to alleviate frequency pulling.Above-mentioned buffered has increased the size and sophistication of PLL.Use various filtering policys to solve above-mentioned noise problem.Effective, the low cost solution of the problems referred to above remain long-standing needs.
Summary of the invention
Generally speaking, the present invention realizes noise transmission by staggered division modulus in the PLL that uses antithesis modulus prescaling.In period demand, not continuous calculating " one " and " ten ".But staggered one and ten.In one embodiment of the invention, the R counting is doubled the output of counter-rotating R counter between high state and low state then.(the Q counter remains unchanged.) in another embodiment of the invention, according to staggered one and ten of ratio q: r.By the modulus that interlocks in a manner described, reach the purpose of the noise of the output signal generation of in wider frequency range, propagating antithesis modulus prescaling.Thereby special in the frequency band of reference frequency, reduce the prescaling noise level greatly.
Description of drawings
By read following explanation together with accompanying drawing, will understand the present invention more.Wherein accompanying drawing is:
Fig. 1 is to use the block diagram divided by the conventional PLL of N counter;
Fig. 2 is to use the block diagram of the conventional PLL of antithesis modulus prescaling;
Fig. 3 is the detailed diagram of a kind of implementation of circuit shown in Figure 2;
Fig. 4 is a sequential chart, the operation of the PLL of presentation graphs 2;
Fig. 5 represents the principle of the present invention of a certain execution mode according to the present invention;
Fig. 6 is the block diagram of the PLL in a certain respect according to the present invention;
Fig. 7 is a sequential chart, the operation of the PLL of presentation graphs 6;
Fig. 8 is a waveform, and the noise level of conventional PLL circuit is used in expression; And
Fig. 9 is a waveform, and the noise level of this PLL circuit is used in expression.
Embodiment
By changing complicated degree and complexity, can use modulus interleaving technique of the present invention in every way.Fig. 5 represents a kind of simply implementation but effective modulus interlocks.In this implementation, keep Q counting and Q counter constant.The R counting is doubled, and counter-rotating R counter.For example, when counter output kept low state to reach 15 countings, the R counting was generally 15, then this counting is doubled as 30.The output of counter-rotating counter, promptly low 1 counting of state, 1 one countings of high state, 1 counting of low state etc., rather than keep low state continuously.Total result is identical with regular situation-refer again to following formula, and its objective is and utilize 2R/2 to replace R.Its difference is, the power spectrum of the modulus control signal that moves up is with away from the PLL reference frequency.If necessary, also can take same procedure to Q.Generally speaking, (and Q, if necessary), wherein m is the number of the modulus of prescaling can to utilize mR/m to replace R.For antithesis modulus prescaling, m=2.
In other structures, if can then be favourable in the distribution of modulus control signal inner control pulse.Referring now to Fig. 6, the figure shows the block diagram of the PLL circuit of another kind of execution mode according to the present invention.Compare with the PLL circuit of Fig. 2,, revise R counter and Q counter by increasing a r counter and a q counter respectively.Synthetic R counter calculates R tale r simultaneously.Synthetic Q counter calculates Q tale q simultaneously.According to exemplary embodiment, the mode of operation of this device is as follows.
As in prior art circuits, by a nonzero value is loaded in the R counter, at the beginning of the cycle, antithesis modulus prescaling is set to divided by P+1.The output of antithesis modulus prescaling is to two counter timing.When the r counter was zero, the R counter stopped counting, and antithesis modulus prescaling is set to divided by P.Then only to the timing of Q counter.When the q counter is zero, once more initial value r and q are loaded in the counter, and next subcycle begins.In the end a sub-cycle period, the R counter counts down is to zero, and after this Q counter counts down is to zero.Fig. 7 represents aforesaid operations, wherein (R, r)=(7,1) and (Q, q)=(8,1).Note that it is 1 that r and q need not, its unique requirement is R≤Q, r≤R, and q≤Q.(r=R and q=Q represent the routine operation method.)
By comparison diagram 8 and Fig. 9, can observe the noise transmission effect of modulus interleaving technique of the present invention.Fig. 8 represents the energy of the signal that exists on the modulus control line according to traditional modulus control setting of Fig. 3 and Fig. 4.Except that zero hertz, the noise margin of first noise peak is about-5dbm.Fig. 9 represents the energy of the signal that exists on the modulus control line according to the modulus control setting of the present invention of Fig. 6 and Fig. 7.Except that zero hertz, the noise margin of first noise peak is about-25dbm.Therefore, this example reduces 20dB with the noise of the modulus control signal of reference frequency, and this has alleviated the noise problem that runs in the prior art greatly.Note that this method and without any need for add ons or extra filtration treatment.Therefore, can not increase the cost that embodies PLL circuit of the present invention in essence.In addition, can loosen or cancel the buffered requirement of VCO output signal.Note that the high-order multimode prescaling processing that above staggered processing can be expanded to easily such as 3 moduluses and 4 modulus prescalings in addition.
Those skilled in the art are appreciated that and can embody the present invention and not deviate from its essence and substantive characteristics with other ad hoc fashions.Therefore, no matter from that, disclosed execution mode all is illustrative, rather than restrictive.Define scope of the present invention by the appended claims book rather than by above-mentioned explanation, and claims comprise all changes in its implication of equal value and the scope.
Claims (8)
1. an operation has at least one modulus P and counts the method for prescaling by the multimode that the transition of calculating applied frequency signal is controlled, and comprising:
Determine at least one integer part Q and a remainder part R of divide operations N/P, the N that wherein required output frequency is the input reference frequency doubly;
In at least a portion modulus control signal, modulus control signal alternately between high state and low state so that in the maximum count of given state internal mold numerical control system signal preservation less than R.
2. the method for claim 1 also comprises each is counted all counter-rotating modulus control signals between each state.
3. a multimode is counted prescaling and relevant controlling circuit, operates by the transition of calculating applied frequency signal, comprising:
First counter comprises the device that is used to store first preset count and is used to calculate the transition of institute's applying frequency; And
Second counter comprises the device that is used to store second preset count and is used to calculate the transition of institute's applying frequency;
Wherein preset the computing interval in calculating, at least one counter generates transition output signal many times.
4. operate the method that multimode is counted prescaling for one kind, comprising:
With the cycle is that the selection between at least one first modulus and second modulus is controlled on the basis, so that during this cycle, prescaling in the first in this cycle with first modulus divided by applied frequency signal, and in the second portion in this cycle with second modulus divided by applied frequency signal; And
With the subcycle is that the selection between at least one first modulus and second modulus is controlled on the basis, so that during this subcycle, prescaling in the first of this subcycle with first modulus divided by applied frequency signal, and in the second portion of this subcycle with second modulus divided by applied frequency signal.
5. the method for claim 4, the wherein said cycle comprises many subcycles.
6. method of operating phase-locked loop, phase-locked loop receives a reference frequency and also generates an output frequency, and this phase-locked loop comprises that a multimode counts prescaling, and this method may further comprise the steps:
Determine the first in the cycle of required output frequency, by the delimiting period reciprocal of incoming frequency, in first, use first modulus, and determine the second portion in this cycle, in second portion, use second modulus; And
Control above modulus, so that in one-period, repeatedly change modulus, thereby obtain required output frequency.
7. one kind is used for the control circuit that multimode is counted prescaling, comprising:
One first counter, this counter calculate R tale r simultaneously;
One second counter, this counter calculate Q tale q simultaneously; And
A control circuit, this circuit repeat to select to be used for first modulus of r counting and be used for second modulus that q counts successively.
8. phase-locked loop comprises:
A reference frequency signal;
A detector that links to each other with reference frequency signal;
A loop filter that links to each other with the output signal of detector;
A controlled oscillator that links to each other with the output signal of loop filter, controlled oscillator generates an output frequency; And
A frequency division circuit, this circuit response output frequency signal generates one and is applied to the detector feedback signal, and this frequency division circuit comprises:
A multimode is counted prescaling;
One first counter, this counter calculate R tale r simultaneously;
One second counter, this counter calculate Q tale q simultaneously; And
A control circuit, this circuit repeat to select to be used for first modulus of r counting and be used for second modulus that q counts successively.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US36267099A | 1999-07-29 | 1999-07-29 | |
| US09/362,670 | 1999-07-29 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2005100669825A Division CN1667955A (en) | 1999-07-29 | 2000-07-31 | PLL noise smoothing using dual-modulus interleaving |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1371549A true CN1371549A (en) | 2002-09-25 |
| CN1207845C CN1207845C (en) | 2005-06-22 |
Family
ID=23427049
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB008120595A Expired - Fee Related CN1207845C (en) | 1999-07-29 | 2000-07-31 | PLL noise smoothing using dual-modulus interleaving |
| CNA2005100669825A Pending CN1667955A (en) | 1999-07-29 | 2000-07-31 | PLL noise smoothing using dual-modulus interleaving |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2005100669825A Pending CN1667955A (en) | 1999-07-29 | 2000-07-31 | PLL noise smoothing using dual-modulus interleaving |
Country Status (6)
| Country | Link |
|---|---|
| EP (1) | EP1201034A1 (en) |
| JP (1) | JP2003506909A (en) |
| KR (1) | KR20020019582A (en) |
| CN (2) | CN1207845C (en) |
| AU (1) | AU6503000A (en) |
| WO (1) | WO2001010028A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101436860B (en) * | 2007-11-15 | 2011-03-30 | 天钰科技股份有限公司 | Phase-locked loop circuit and corresponding frequency translation method |
| GB2533557A (en) * | 2014-12-16 | 2016-06-29 | Nordic Semiconductor Asa | Frequency divider |
| CN111478696B (en) * | 2020-05-07 | 2024-05-31 | 上海磐启微电子有限公司 | Control method of four-mode prescaler and four-mode prescaler applying same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3521288A1 (en) * | 1985-06-13 | 1986-12-18 | Siemens AG, 1000 Berlin und 8000 München | Arrangement for digital division of an input cycle |
| FR2716053B1 (en) * | 1994-02-09 | 1996-04-26 | Sat | Method for generating a specific frequency by dividing a reference frequency. |
-
2000
- 2000-07-31 WO PCT/US2000/020749 patent/WO2001010028A1/en not_active Application Discontinuation
- 2000-07-31 CN CNB008120595A patent/CN1207845C/en not_active Expired - Fee Related
- 2000-07-31 CN CNA2005100669825A patent/CN1667955A/en active Pending
- 2000-07-31 AU AU65030/00A patent/AU6503000A/en not_active Abandoned
- 2000-07-31 EP EP00952306A patent/EP1201034A1/en not_active Withdrawn
- 2000-07-31 KR KR1020027001156A patent/KR20020019582A/en not_active Application Discontinuation
- 2000-07-31 JP JP2001513812A patent/JP2003506909A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JP2003506909A (en) | 2003-02-18 |
| CN1667955A (en) | 2005-09-14 |
| EP1201034A1 (en) | 2002-05-02 |
| CN1207845C (en) | 2005-06-22 |
| KR20020019582A (en) | 2002-03-12 |
| AU6503000A (en) | 2001-02-19 |
| WO2001010028A1 (en) | 2001-02-08 |
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Owner name: PANASONIC ELECTRIC EQUIPMENT INDUSTRIAL CO.,LTD. Free format text: FORMER OWNER: TROPIAN, INC. Effective date: 20070209 |
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