JPH0669793A - Pll snthesizer circuit - Google Patents

Abstract

PURPOSE:To provide a PLL synthesizer circuit capable of shortening a lock-up time by letting the frequency of a reference signal be high without reducing the number of usable channels. CONSTITUTION:The output signals phiR and phiP of a phase comparator 3 based on the phase difference between a reference signal fr and a comparing signal fp are converted to an analog voltage signal SCP by a charge pump 5, an output signal SCP is outputted to VCO 7 via a LPF 6 and the output signal fVCO of VCO 7 is ouputted to a comparing frequency divider 4 so as to operate to let the frequencies and the phases of both signals fr and fp be coincident. A control circuit 13 starting the frequency dividing operation of a swallow counter 10 at the time of counting the frequency dividing operation of a main counter 9 plural times is connected to the swallow counter 10 of the comparing divider 4. Then, the frequency of the output signal fVCO of VCO 7 is raised to a frequency by the counting number-fold of a controller 13 by a multiplier 12 and inputted to a pre-scaler 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL synthesizer circuit which operates so that an output signal frequency always matches a set frequency.

A PLL synthesizer circuit is a negative feedback circuit which operates so as to match a set frequency with an output signal frequency. In recent years, PLL synthesizer circuits have been used for mobile communication such as car phones and mobile phones, and in order to shorten the access time, it is required to shorten the time required for the output signal frequency to be fixed at a set frequency. There is.

[0003]

2. Description of the Related Art An example of a conventional PLL synthesizer circuit will be described with reference to FIG. 4. A crystal oscillator 1 outputs a reference clock signal CK having a natural frequency based on the oscillation of a crystal oscillator to a reference frequency divider 2 for reference frequency division. The device 2 divides the reference clock signal CK based on the set frequency set from the outside and outputs the reference signal fr to the phase comparator 3. A comparison signal fp is output from the comparison frequency divider 4 described later to the phase comparator 3, and the phase comparator 3 outputs pulse signals ΦR and ΦP according to the frequency difference and the phase difference between the reference signal fr and the comparison signal fp. Is output to the charge pump 5.

The charge pump 5 outputs an output signal SCP based on the pulse signals ΦR and ΦP output from the phase comparator 3.
To a low pass filter (hereinafter referred to as LPF) 6. This output signal SCP includes a pulse component in the DC component, and the DC component is the pulse signal ΦR,
The pulse component moves up and down with the frequency variation of ΦP, and the pulse component changes based on the phase difference between the pulse signals ΦR and ΦP.

The LPF 6 is an output signal S of the charge pump 5.
Output signal SLPF with CP smoothed to remove high frequency components
To a voltage controlled oscillator (hereinafter referred to as VCO) 7,
The CO 7 outputs an output signal fvco having a frequency corresponding to the voltage value of the output signal SLPF of the LPF 6 to an external circuit and also to the comparison frequency divider 4. The comparison frequency divider 4 frequency-divides the output signal fvco of the VCO 7 and outputs it to the phase comparator 3.

The pulse signal ΦR output from the phase comparator 3 is output to the lock detecting circuit 8 as a pulse signal fΔ, and the lock detecting circuit 8 outputs the pulse signal fΔ when the pulse width of the pulse signal fΔ becomes a predetermined value or less. Same pulse signal f
When Δ is not output at all, the H level lock signal LD is output, and when the output signal fvco of the VCO 7 fluctuates and the pulse width of the pulse signal fΔ is a certain value or more, the L level unlock signal LD is output. Is output.

In the PLL synthesizer circuit configured as described above, if the setting of the comparison signal fp is changed and the frequency thereof is lowered from the locked state where the frequency and phase of the reference signal fr and the comparison signal fp match, the reference signal fr becomes The frequency and the phase of the comparison signal fp are deviated, and the phase comparator 3 outputs the pulse signals ΦR and ΦP and outputs the L-level unlock signal LD.

The output signal SC of the charge pump 5
As the DC component of P fluctuates, a pulse component is generated, and the output signal SLP of the LPF 6 is generated based on the output signal SCP.
The voltage level of F decreases, and eventually the output signal S of the LPF 6
The LPF converges to the voltage level corresponding to the newly set comparison signal fp and returns to the locked state.

In the PLL synthesizer circuit as described above, it is necessary to increase the frequency of the reference signal fr in order to shorten the lockup time from the change of the setting of the comparison signal fp to the convergence of the frequency of the output signal fvco of the VCO 7. There is. Further, it is necessary to improve the channel separation with the reference signal fr raised.

In order to satisfy such requirements, there is a type in which the comparison frequency divider 4 has a pulse swallow method. That is, the pulse swallow type comparison frequency divider 4 will be explained. The output signal fvco of the VCO 7 is input to the dual modulus prescaler 11 and the prescaler 11
Outputs the frequency of the input signal fvco to the main counter 9 and the swallow counter 10 by dividing the frequency by P or P + 1.

The swallow counter 10 includes a prescaler 11
The swallow counter 1 controls the frequency division ratio of
While 0 counts the pulses of the output signal of the prescaler 11, the prescaler 11 operates at P + 1 frequency division, and when the swallow counter 10 counts A pulses, the prescaler 11 operates at P frequency division.

The main counter 9 includes a prescaler 11
The output signal of 1 is frequency-divided by N to be output to the phase comparator 3, and an activation signal is output to the swallow counter at each frequency of N.

Therefore, the frequency division ratio of the comparison frequency divider 4 is A /
The time of N operates with the division ratio of 1 / (P + 1) · N, and (N
-A) / N time operates with a division ratio of 1 / P · N. With such an operation, the output signal fp of the comparison frequency divider 4
Is

[0014]

[Equation 1]

The output signal fvco of the VCO 7 is

[0016]

[Equation 2]

[0017] However, in the above equations, N>
It is necessary that A and N> P. Also, according to the above formula

[0018]

[Equation 3]

It becomes Therefore, in the PLL synthesizer circuit, the swallow counter 10 operates to count the output signal of the prescaler 11 every time the main counter 9 divides the output signal of the prescaler 11 by N, as shown in FIG.

[0020]

In the PLL synthesizer circuit using the conventional pulse swallow-type comparison frequency divider as described above, since the frequency division ratio of the comparison frequency divider 4 is P · N + A, the swallow counter 10 is used. When the frequency division ratio A of is changed by "1", the output signal fvco of the VCO 7 changes at intervals of the reference signal fr.

That is, the channel step changes at the frequency interval of the reference signal fr. However, in recent mobile communication, the used channel interval tends to be narrowed in order to effectively use the frequency. Therefore, if the frequency of the reference signal fr is increased, the channel step is expanded and the number of usable channels is decreased.
There is a problem that the frequency of r cannot be set high.

An object of the present invention is to provide a PLL synthesizer circuit capable of increasing the frequency of a reference signal and shortening the lockup time without reducing the number of usable channels.

[0023]

FIG. 1 is a diagram for explaining the principle of the present invention. That is, the reference signal fr output from the reference frequency divider 2 and the comparison signal fp output from the comparison frequency divider 4 are input to the phase comparator 3 and the positions of the two signals fr and fp are output from the phase comparator 3. Output signals ΦR and ΦP whose pulse widths increase and decrease based on the phase difference are output, the output signals ΦR and ΦP of the phase comparator 3 are converted into analog voltage signals SCP by the charge pump 5, and the output signal S of the charge pump 5 is converted.
CP is output to the voltage controlled oscillator 7 through the low pass filter 6, and the output signal fvco of the voltage controlled oscillator 7 is output to the comparison frequency divider 4 to match the frequency and phase of the reference signal fr and the comparison signal fp. The negative feedback operation is performed so that

The comparison frequency divider 4 is constituted by a swallow counter system consisting of a prescaler 11, a swallow counter 10 and a main counter 9, and the swallow counter 10 counts the frequency dividing operation of the main counter 9 a plurality of times. At this time, a control circuit 13 for starting the frequency dividing operation of the swallow counter 10 is connected, and the frequency of the output signal fvco of the voltage controlled oscillator 7 is equal to the count number of the control circuit 13 by the multiplier 12 in the prescaler 11. It is input after being multiplied by multiple times.

[0025]

When the swallow counter 10 is operated every time the control circuit 13 counts the frequency dividing operation of the main counter 9 a plurality of times, the channel step of the PLL synthesizer circuit is a reference if the count number of the control circuit 13 is n. It becomes 1 / n of the frequency of the signal fr.

Therefore, if the frequency of the reference signal fr is raised to n times and the input signal frequency of the prescaler 11 is multiplied by n by the multiplier 12, the frequency of the reference signal fr can be raised without changing the channel step. Become.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment embodying the present invention will now be described with reference to FIG.
3 and FIG. The PLL synthesizer circuit of this embodiment is obtained by adding a multiplier 12 and a counter circuit 13 to the conventional PLL synthesizer circuit shown in FIG. 4, and the same components as those of the conventional example are designated by the same reference numerals. explain.

That is, the multiplier 12 has the VCO
The output signal fvco of No. 7 is input, and the multiplier 11 doubles the frequency of the output signal fvco, for example, and outputs it to the prescaler 11.

The counter circuit 13 counts the number of times the main counter 9 divides the output signal of the prescaler 11 by N. For example, the main counter 9 repeats dividing the output signal of the prescaler 11 by N twice. At this time, a signal for starting the frequency dividing operation is output to the swallow counter 10.

In the PLL synthesizer circuit configured as described above, when the main counter 9 repeats dividing by N twice by the operation of the counter circuit 13, the swallow counter 10 operates, so that the comparison dividing operation is performed. The frequency division ratio of the unit 4 is as shown in the following equation.

[0031]

[Equation 4]

It becomes Further, when the input signal of the prescaler 11 is fin and the comparison signal output to the phase comparator 3 based on the frequency division ratio is fpx,

[0033]

[Equation 5]

It becomes On the other hand, the comparison signal fp output from the main counter 9 according to the frequency division ratio of the conventional example is

[0035]

[Equation 6]

The relationship is as follows. When the output signal fvco of the VCO 7 is in the locked state, the frequency of the comparison signal fp and the frequency of the reference signal fr match,

[0037]

[Equation 7]

[0038] Therefore, the input signal fin of the prescaler 8 is

[0039]

[Equation 8]

It becomes From this formula, swallow counter 1
When the frequency division ratio of 0 is changed by "1", the channel step becomes fr / 2. Therefore, since the interval is 1/2 of the channel step of the conventional example, the frequency of the reference signal fr can be doubled if the channel steps have the same interval as the conventional example.

When the frequency of the reference signal fr is doubled and the channel step is kept the same as in the conventional example, the frequency of the output signal fvco of the VCO 7 is doubled by the multiplier 12 to prescale 2fvco. If the signal is input to 11 as the input signal fin, the above equation can be satisfied.

As described above, in this PLL synthesizer circuit, the lockup time can be shortened by raising the frequency of the reference signal fr without changing the used channel interval.

Although the reference signal fr is doubled in the above embodiment, the counter circuit 13 uses the main counter 9
If the input signal frequency of the prescaler 11 is increased to n times by the multiplier 12, the swallow counter 10 is operated by counting the N frequency divisions n times, and the reference signal fr can be increased to n times.

[0044]

As described above in detail, according to the present invention, the lockup time can be shortened by increasing the frequency of the reference signal without decreasing the number of usable channels.
It has an excellent effect of being able to provide the L synthesizer circuit.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing an embodiment.

FIG. 3 is an explanatory diagram showing an operation of one embodiment.

FIG. 4 is a block diagram showing a conventional example.

FIG. 5 is an explanatory diagram showing an operation of a conventional example.

[Explanation of symbols]

 2 Reference divider 3 Phase comparator 4 Comparison divider 5 Charge pump 6 Low pass filter 7 Voltage controlled oscillator 9 Main counter 10 Swallow counter 11 Prescaler 12 Multiplier 13 Control circuit fr Reference signal fp Comparison signal ΦR, ΦP Output signal SCP Analog voltage signal fvco output signal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shinji Saito 2-1844, Kozoji-cho, Kasugai-shi, Aichi Prefecture Fujitsu Vielle SII Co., Ltd. (72) Masayuki Yonekawa 2-1844-2 Kozoji-cho, Kasugai-shi, Aichi Fujitsu (72) Inventor Tetsuya Aisaka 2-1844, Kozoji-cho, Kasugai-shi, Aichi FUJITSU VIEL-SII Co., Ltd.

Claims (1)

[Claims] 1. A reference signal (fr) output from a reference frequency divider (2) and a comparison signal (fp) output from a comparison frequency divider (4) are input to a phase comparator (3). The phase comparator (3) outputs an output signal (ΦR, ΦP) whose pulse width increases or decreases based on the phase difference between the two signals (fr, fp), and outputs the output signal (ΦR, ΦP) of the phase comparator 3. Is converted into an analog voltage signal (SCP) by a charge pump (5), and the output signal (SCP) of the charge pump (5) is passed through a low pass filter (6) to a voltage controlled oscillator (7).
To the output signal of the voltage controlled oscillator (7) (fvc
o) is output to the comparison frequency divider (4) to perform negative feedback operation so as to match the frequency and phase of the reference signal (fr) and the comparison signal (fp) with each other. The frequency divider (4) is configured by a swallow counter system including a prescaler (11), a swallow counter (10) and a main counter (9), and the swallow counter (10) divides the main counter (9). Is connected to a control circuit (13) for starting the frequency dividing operation of the swallow counter (10), and the prescaler (11) is connected to the frequency of the output signal (fvco) of the voltage controlled oscillator (7). Is multiplied by a multiplier (12) to a plurality of times equal to the count number of the control circuit (13) and is input.