JPH06152393A - Phase synchronizing oscillator - Google Patents
Phase synchronizing oscillatorInfo
- Publication number
- JPH06152393A JPH06152393A JP4291855A JP29185592A JPH06152393A JP H06152393 A JPH06152393 A JP H06152393A JP 4291855 A JP4291855 A JP 4291855A JP 29185592 A JP29185592 A JP 29185592A JP H06152393 A JPH06152393 A JP H06152393A
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- Prior art keywords
- frequency
- frequency division
- phase
- signal
- output
- Prior art date
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- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、無線通信装置の周波数
変換部分で使用する位相同期発振器に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked oscillator used in a frequency conversion part of a wireless communication device.
【０００２】近年、無線通信の分野では需要の増大に対
処する為、多値化による伝送容量の向上や多チャネル化
の為のチャネルスペーシングの狭帯域化が実施されてい
る。これに伴い機器に使用される発振器には高い安定度
と信号純度が要求されているので、高い周波数で使用し
ても位相雑音の低い位相同期発振器の提供が必要であ
る。[0002] In recent years, in the field of wireless communication, in order to cope with the increase in demand, the transmission capacity has been improved by multi-leveling and the channel spacing band has been narrowed for multi-channeling. Accompanying this, high stability and signal purity are required for oscillators used in equipment, so it is necessary to provide a phase locked oscillator with low phase noise even when used at high frequencies.
【０００３】[0003]
【従来の技術】図５は従来例の構成図、図６はスペクト
ラム純度説明図である。以下、出力信号の周波数F0＝12
80MHz として図５，図６の説明をする。2. Description of the Related Art FIG. 5 is a block diagram of a conventional example, and FIG. 6 is an explanatory diagram of spectrum purity. Below, the frequency of the output signal F 0 = 12
5 and 6 will be described assuming that the frequency is 80 MHz.
【０００４】先ず、図５において、位相比較器12は、基
準発振器11からの基準周波数(FREF)10MHzの信号と、分
周器14でN 分周した電圧制御発振器２の出力周波数(F0)
の信号との位相を比較して位相差に対応した位相差電圧
を取り出し、低域通過フイルタ13を介して制御電圧とし
て電圧制御発振器２に加える。First, in FIG. 5, a phase comparator 12 outputs a signal of a reference frequency (F REF ) of 10 MHz from a reference oscillator 11 and an output frequency (F 0 of the voltage controlled oscillator 2 divided by N by a frequency divider 14). )
The phase difference voltage corresponding to the phase difference is extracted by comparing the phase with the signal of (1) and is applied to the voltage controlled oscillator 2 as a control voltage via the low pass filter 13.
【０００５】ここで、出力周波数が基準周波数に同期し
た状態では位相同期ループ(PLL) 回路の出力周波数(F0)
との間には、 F0＝N ・ FREF ・・・・(1) の関係が成り立つので、 N ＝128 となる。Here, when the output frequency is synchronized with the reference frequency, the output frequency (F 0 ) of the phase locked loop (PLL) circuit is
The relation F 0 = N · F REF ··· (1) holds between and, so N = 128.
【０００６】従って、位相比較器12は、10MHz の信号位
相と128 分周された電圧制御発振器の出力信号位相とを
比較することにより、相互の位相を同期させている。な
お、分周器14は入力周波数が1280MHz と高い為、通常は
ECL(エミッタカップルドトランジスタ) 等の高速デバイ
スが使用される。また、位相比較器12は動作周波数が10
MHz である為、消費電力, 雑音余裕の点よりC-MOS とす
るのが一般的である。Therefore, the phase comparator 12 synchronizes the mutual phase by comparing the signal phase of 10 MHz with the output signal phase of the voltage controlled oscillator divided by 128. Since the input frequency of the frequency divider 14 is as high as 1280 MHz, it is normally
High-speed devices such as ECL (emitter coupled transistor) are used. The phase comparator 12 has an operating frequency of 10
Since it is MHz, it is general to use C-MOS in terms of power consumption and noise margin.
【０００７】ところで、位相同期発振器のスペクトラム
純度はしばしば, 位相雑音で評価されるが、低雑音化を
主眼とした場合の雑音特性を決定する要因としては図６
に示に領域Ａ, 領域Ｂ, 領域Ｃの３つに大きく分けられ
る。領域Ａで支配的なのは基準発振器で発生する雑音で
あり、領域Ｂは雑音フロアにより、領域Ｃは電圧制御発
振器で発生する雑音である。By the way, the spectrum purity of the phase-locked oscillator is often evaluated by the phase noise, and as a factor that determines the noise characteristics when the main purpose is to reduce the noise, FIG.
The area is roughly divided into three areas, area A, area B, and area C. The dominant in the area A is the noise generated in the reference oscillator, the area B is the noise floor, and the area C is the noise generated in the voltage controlled oscillator.
【０００８】今回、問題となるのは領域Ｂの雑音である
が、その位相雑音はデバイスのフロア雑音( 後述する)
により決定され、 L OUT =L D＋20 log N (dB) ・・・(2) と表される。This time, the problem is the noise in the area B, but the phase noise is the floor noise of the device (described later).
Is determined by L OUT = L D +20 log N (dB) (2).
【０００９】ここで、L D は位相比較器12及び分周器14
のフロア雑音であり、N はその分周数である。つまり、
出力の位相雑音には20 log N dB の劣化が発生する。そ
れぞれのデバイスのフロア雑音は、デバイス自身のプロ
セスによるところが大きく、一般に消費電力の大きいデ
バイスや、出力レベルの小さいデバイスは雑音が大きい
とされている。各デバイスの代表的な値は各種文献にも
発表されてはいるが, かなり差がある。Here, L D is a phase comparator 12 and a frequency divider 14
Is the floor noise of and N is its frequency division factor. That is,
The output phase noise is degraded by 20 log N dB. The floor noise of each device largely depends on the process of the device itself, and it is generally said that the device with large power consumption and the device with low output level have large noise. Although typical values for each device have been published in various documents, there are considerable differences.
【００１０】ここでは、説明の為にC-MOS プロセスであ
る位相比較器12のフロア雑音 LPD=−150dBc/Hz, ECLの
分周器14によるフロア雑音 LDIV = −140dBc/Hz とす
る。これにより、出力の位相雑音 LOPD は位相比較器に
より、 L OPD = L PD＋20 log N =−150 ＋20log 128 = −107.9 dBc/Hz ・・・ (3) 次に、分周器14により、 LODIV= L DIV ＋20log N1= − 97.9 dBc/Hz・・・(4) 全体では上記の電力加算となり LO = −97.5 dBc/ Hz となる。Here, for the sake of explanation, it is assumed that the floor noise L PD of the phase comparator 12 which is a C-MOS process is −150 dBc / Hz and the floor noise L DIV of the ECL divider 14 is −140 dBc / Hz. As a result, the output phase noise L OPD is calculated by the phase comparator, L OPD = L PD +20 log N = −150 +20 log 128 = −107.9 dBc / Hz (3) Next, by the frequency divider 14, ODIV = L DIV ＋ 20log N 1 = −97.9 dBc / Hz (4) Overall, the above power addition results and L O = −97.5 dBc / Hz.
【００１１】なお、−97.5dBc/Hzの値は低速データを伝
送するには問題ないが、高速データを伝送する際には誤
り率に影響を与える。Although the value of -97.5 dBc / Hz is not a problem for transmitting low speed data, it affects the error rate when transmitting high speed data.
【００１２】[0012]
【発明が解決しようとする課題】従って、PLL 帯域内に
おいては: デバイスにより決まるフロア雑音量より低雑
音化することはできないが、更にその雑音が複数のデバ
イスのうちのより雑音の悪いデバイスにほぼ支配されて
しまうと云う欠点を生じていた。Therefore, in the PLL band, it is impossible to lower the floor noise amount determined by: the device, but the noise is almost the same as that of the device with less noise among a plurality of devices. It had the drawback of being ruled.
【００１３】特に、数100 MHz を越える様な周波数を無
線周波数として使用する場合、使用可能な素子として雑
音特性の余り良くないECL 等に限定される為、必ず上記
と同様な問題が発生すると言える。In particular, when a frequency exceeding several hundred MHz is used as a radio frequency, usable elements are limited to ECL or the like having a poor noise characteristic, so that it can be said that the same problem as described above will always occur. .
【００１４】本発明は、数 100MHz を越える周波数帯に
おいてもフロア雑音を改善し、高い周波数で使用しても
位相雑音の低い位相同期発振器の提供を図ることを目的
とする。It is an object of the present invention to improve a floor noise even in a frequency band exceeding several hundred MHz and to provide a phase locked oscillator having a low phase noise even when used at a high frequency.
【００１５】[0015]
【課題を解決するための手段】図１は本発明の原理構成
図である。図中、１は入力する所定周波数の基準信号と
比較信号の位相を比較して位相差分を取り出し、低域通
過フイルタを介して制御信号として送出する位相比較
部、２は入力する該制御信号に対応する周波数の出力信
号を送出する電圧制御発振器、３は該出力信号を分周す
る第１の分周部分と該第１の分周部分の出力を更に分周
して該比較信号として送出する第２の分周部分とを具備
するＮ分周部である。FIG. 1 is a block diagram showing the principle of the present invention. In the figure, 1 is a phase comparison unit that compares the phase of a reference signal having a predetermined frequency and the phase of a comparison signal, extracts the phase difference, and sends it as a control signal via a low-pass filter, and 2 is a control signal that is input. The voltage controlled oscillator 3 which outputs the output signal of the corresponding frequency further divides the frequency division of the output signal and the output of the first frequency division portion and outputs the divided signal as the comparison signal. And a second frequency dividing portion.
【００１６】そして、第１の分周部分の分周比は、該第
１の分周部分の出力周波数が該第２の分周部分の動作周
波数範囲内となる値に設定し、該第２の分周部分は、該
第１の分周部分より低速動作の素子を使用し、分周比は
Ｎ／（第１の分周部分の分周比）に設定する。The frequency division ratio of the first frequency division portion is set to a value such that the output frequency of the first frequency division portion falls within the operating frequency range of the second frequency division portion, For the frequency division part, a device operating at a slower speed than the first frequency division part is used, and the frequency division ratio is set to N / (frequency division ratio of the first frequency division part).
【００１７】[0017]
【作用】本発明では、第１の分周部分31と第２の分周部
分32とを縦続接続し、それぞれの分周数の組合せにより
全体の分周数を得ている。ここで、第１の分周部分31の
入力周波数は出力周波数と同一の為、高速の分周動作が
必要であるが、第２の分周部分32は第１の分周部分によ
り分周された信号が入力される為、低速の分周動作でよ
い。In the present invention, the first frequency division part 31 and the second frequency division part 32 are connected in cascade, and the total frequency division number is obtained by combining the respective frequency division numbers. Here, since the input frequency of the first frequency division part 31 is the same as the output frequency, high-speed frequency division operation is necessary, but the second frequency division part 32 is frequency-divided by the first frequency division part. Signal is input, a low-speed frequency division operation is sufficient.
【００１８】従って、高速ではあるが雑音の大きいECL
等のデバイスは第１の分周部分のみに使用すればよく、
第２の分周部分には低雑音のC-MOS などが使用可能とな
る。出力信号中のフロア雑音は、位相比較部, 第１の分
周部分，第２の分周部分の雑音の加算となるが、支配的
であった第１の分周部分の雑音は第２の分周部分による
分周の効果により低減されており（または、N2の分だけ
N1の分周数が下がる) 、出力におけるフロア雑音は改善
される。Therefore, the ECL is fast but noisy.
The device like, etc. should be used only for the first frequency division,
A low noise C-MOS can be used for the second frequency division. The floor noise in the output signal is the addition of the noises of the phase comparison unit, the first frequency division part, and the second frequency division part, but the dominant noise of the first frequency division part is the second noise. It is reduced by the effect of the frequency division (or only N 2
Frequency division number N 1 is lowered), the floor noise at the output is improved.
【００１９】ここで、従来例との比較の為、基準周波数
FREF =10MHz, 出力周波数 FOUT =1280 MHzすると、全
体の分周数 Ntotal = N1・N2 =128 となるので、第１の
分周部分の分周数 N1=64, 第２の分周数 N2=２とする。Here, for comparison with the conventional example, the reference frequency
When F REF = 10MHz and output frequency F OUT = 1280 MHz, the total frequency division number N total = N 1 · N 2 = 128, so the frequency division number of the first frequency division N 1 = 64, 2nd The frequency division number of N 2 = 2.
【００２０】第１の分周部分の入力は1280 MHzと高い周
波数であるので、ECL 等のデバイス使用する必要がある
が、第２の分周部分については(1280/64 )=20MHzとなる
為C-MOS デバイスによる分周が可能となる。Since the input of the first frequency division part has a high frequency of 1280 MHz, it is necessary to use a device such as ECL, but (1280/64) = 20 MHz for the second frequency division part. It becomes possible to divide by C-MOS device.
【００２１】従来例と同様に出力信号中のフロア雑音を
計算すると、(3) 式から位相比較器１による雑音は L OPD =−150 ＋20log 128 = −107.9 dBc/Hz 第１の分周部分では、 LODIV-31= (L DIV-31−20log N2) ＋20 log Ntotal = −103.9 dBc/Hz または、 LODIV-31= L DIV-31＋20log N1 =−103.9 dB
c/Hz 第２の分周部分では、 LODIV-32= L DIV-32＋20 log N total = −107.9 dBc/Hz 全体の雑音( 出力側で見た雑音) は上記の電力加算だか
ら LO = −101.4 dBc/Hz となり、従来例の−97.5dBc/Hzと比較して約3.86 dB の
改善が得られる。When the floor noise in the output signal is calculated in the same manner as in the conventional example, the noise due to the phase comparator 1 is L OPD = −150 + 20log 128 = −107.9 dBc / Hz from the equation (3) in the first frequency division part. , L ODIV-31 = (L DIV-31 −20log N 2 ) +20 log N total = −103.9 dBc / Hz or L ODIV-31 = L DIV-31 + 20log N 1 = −103.9 dB
c / Hz In the 2nd frequency division, L ODIV-32 = L DIV-32 +20 log N total = −107.9 dBc / Hz The total noise (noise seen at the output side) is the above power addition, so L O = It is -101.4 dBc / Hz, which is an improvement of about 3.86 dB compared to the conventional example of -97.5 dBc / Hz.
【００２２】ここで、N1= 32とし、N2 =４とすれば、 L
O = − 103.7dBc/Hzとなり、更に、2.3dB の改善が得ら
れるが、第２の分周部分の入力周波数が40MHz と高くな
って一般的な高速C-MOS の保証範囲を越える。ただし、
ゲートアレイ等では100 MHz付近まで動作するICも存在
する為、不可能ではない。If N 1 = 32 and N 2 = 4, then L
O = -103.7dBc / Hz, and an improvement of 2.3dB can be obtained, but the input frequency of the second frequency division becomes as high as 40MHz, which exceeds the guaranteed range of general high-speed C-MOS. However,
There are ICs that operate up to around 100 MHz in gate arrays, so this is not impossible.
【００２３】N1を小さくし、N2を大きくすれば第１の分
周部分の雑音は改善されるが、第２の分周部分の入力周
波数の限界や第２の分周部分の消費電力増加が発生す
る。また、ある程度改善されれば、出力の雑音を支配す
る素子が第２の分周部分から他の部分に移ってしまう
為、分周器を分割すると云う効果は次第に小さくなる傾
向にある。If N 1 is made small and N 2 is made large, the noise in the first frequency division portion will be improved, but the input frequency limit of the second frequency division portion and the power consumption in the second frequency division portion will be improved. Increase occurs. Further, if it is improved to some extent, the element that governs the output noise moves from the second frequency division part to another part, so that the effect of dividing the frequency divider tends to gradually decrease.
【００２４】[0024]
【実施例】図２は本発明の実施例の構成図、図３は本発
明の別の実施例の構成図、図４は本発明を適用したパル
ススワロー方式構成図である。2 is a block diagram of an embodiment of the present invention, FIG. 3 is a block diagram of another embodiment of the present invention, and FIG. 4 is a pulse swallow system configuration diagram to which the present invention is applied.
【００２５】ここで、全図を通じて同一符号は同一対象
物を示す。以下、図２〜図４の動作を順次、説明する。
図２において、低域通過フイルタ13は抵抗とコンデンサ
を有するラグリードタイプのフイルタで構成され、第１
の分周部分31はフリップフロップ( 以下, D-FFと省略す
る) を６段接続し、64分周を得る非同期形の分周器とし
ているが、分周器の構成はこの限りではなく、同期形を
用いてもよい。第２の分周部分32は１段のD-FFで２分周
を得るものである。Here, the same reference numerals denote the same objects throughout the drawings. Hereinafter, the operations of FIGS. 2 to 4 will be sequentially described.
In FIG. 2, the low-pass filter 13 is composed of a lag lead type filter having a resistor and a capacitor.
The frequency division part 31 is an asynchronous frequency divider that connects 6 stages of flip-flops (hereinafter abbreviated as D-FF) to obtain 64 frequency division, but the frequency divider configuration is not limited to this. A synchronous type may be used. The second frequency division portion 32 is for obtaining a frequency division by 2 with one stage of D-FF.
【００２６】そして、第１の分周部分31は高速動作用の
ECL を使用し、第２の分周部分32は低雑音のC-MOS を使
用した場合、入出力信号レベルが異なるのでレベル合わ
せの為にレベル変換器33が設けられている。The first frequency division portion 31 is for high speed operation.
When the ECL is used and the second frequency dividing portion 32 is a low noise C-MOS, the input / output signal levels are different, so that the level converter 33 is provided for level adjustment.
【００２７】なお、レベル変換器として反転ゲートを利
用した回路を例としているが、同様の機能をもつもので
あればこれに限らない。この構成においては、全体の分
周数は Ntotal = N1・N2 = 64 ×２ = 128 また、出力周波数は F0 = Ntotal ・ FREF = 128 × 10MHz = 1280MHz が実現できる。Although a circuit using an inverting gate as the level converter is taken as an example, the level converter is not limited to this as long as it has a similar function. In this configuration, the total frequency division number is N total = N 1 · N 2 = 64 × 2 = 128, and the output frequency can be F 0 = N total · F REF = 128 × 10 MHz = 1280 MHz.
【００２８】図３において、第１の分周部分31´を構成
するD-FFの段数を５段にし、N1 =32としている。また、
第２の分周部分32´は２段のD-FFとし、N2= ４としてい
る。これにより、 Ntotal = 128 , F0 = 1280MHzを得る
ものである。In FIG. 3, the number of stages of D-FFs constituting the first frequency division portion 31 'is set to 5 and N 1 = 32. Also,
The second divider portion 32 'is a two-stage D-FF, is set to N 2 = 4. As a result, N total = 128 and F 0 = 1280 MHz are obtained.
【００２９】ここで、図２，図３は分周器として分周数
固定の構成としたが、シンセサイザ化する際には公知の
パルススワロー方式を用いることが多い。今、基準周波
数 FREF =10MHz, 出力周波数 F0 = 1280MHz, Ntotal =1
28とすると本方式の動作条件よりN1≦11となる。回路の
実現の容易さ、低消費電力化等を考えると第１の分周部
分34と第２の分周部分35との間のインタフェース周波数
はできるだけ低い方がよく、図４の構成とするのが一般
的であり、N10=10, N20=12, A0=8とすると、 Ntotal =
N10 ・N20 ＋A0=128となる。Although FIGS. 2 and 3 have a configuration in which the frequency division number is fixed as the frequency divider, a well-known pulse swallow method is often used when a synthesizer is used. Now, the reference frequency F REF = 10MHz, output frequency F 0 = 1280MHz, N total = 1
At 28, N 1 ≤ 11 due to the operating conditions of this method. Considering the ease of realizing the circuit and the reduction of power consumption, the interface frequency between the first frequency dividing portion 34 and the second frequency dividing portion 35 is preferably as low as possible. Is general, and N 10 = 10, N 20 = 12, A 0 = 8, N total =
N 10 and N 20 + A 0 = 128.
【００３０】なお、N10, N11, N12 は第１の分周部分34
の分周数、N20, N21, N22 は第２の分周部分35の分周
数、A0, A1はA カウンタ36の分周数とする。ここで、上
記２例と同様な考え方により、N10 を小さく、N20 を大
きくする。Note that N 10 , N 11, and N 12 are the first frequency division portion 34.
, N 20 , N 21, N 22 are frequency division numbers of the second frequency division part 35, and A 0 , A 1 are frequency division numbers of the A counter 36. Here, N 10 is made small and N 20 is made large by the same idea as the above two examples.
【００３１】例えば、N11=８とするとN21=16, A1= ０と
なる。また、N12=５とするとN22=25, A2= ３となる。そ
れぞれの場合における分周器３のフロア雑音改善量は、 N10 →N11 と10から８に変えた時、20 log( N21/ N20)=
20 log ( 16/12)= 2.5dBとなり、 N10 →N12 と10から５に変えた時、20 log( N22/ N20)=
20 log ( 25/12)= 3.2dBとなる。For example, if N 11 = 8, then N 21 = 16 and A 1 = 0. If N 12 = 5, then N 22 = 25 and A 2 = 3. The floor noise improvement amount of the frequency divider 3 in each case is 20 log (N 21 / N 20 ) = when changing from N 10 → N 11 and 10 to 8.
20 log (16/12) = 2.5 dB, and when changing from N 10 → N 12 and 10 to 5, 20 log (N 22 / N 20 ) =
20 log (25/12) = 3.2 dB.
【００３２】上記の様に、全分周数を複数の分周器の分
周数の組合せとして得ることにより、高速ではあるが雑
音特性の悪いデバイスを使用しても、出力のフロア雑音
の劣化を抑圧することができ、低位相雑音の位相同期発
振器の実現が可能となり、この様な位相同期発振器の性
能向上に寄与するところが大きい。As described above, by obtaining the total frequency division number as a combination of frequency division numbers of a plurality of frequency dividers, even if a device having a high speed but poor noise characteristics is used, the output floor noise is deteriorated. Can be suppressed, and a phase-locked oscillator with low phase noise can be realized, which largely contributes to the performance improvement of such a phase-locked oscillator.
【００３３】[0033]
【発明の効果】以上詳細に説明した様に本発明によれ
ば、高い周波数で使用しても位相雑音の低い位相同期発
振器の提供ができると云う効果がある。As described in detail above, according to the present invention, there is an effect that it is possible to provide a phase locked oscillator having low phase noise even when used at a high frequency.
【図１】本発明の原理構成図である。FIG. 1 is a principle configuration diagram of the present invention.
【図２】本発明の実施例の構成図である。FIG. 2 is a configuration diagram of an embodiment of the present invention.
【図３】本発明の別の実施例の構成図である。FIG. 3 is a configuration diagram of another embodiment of the present invention.
【図４】本発明を適用したパルススワロー方式構成図で
ある。FIG. 4 is a block diagram of a pulse swallow system to which the present invention is applied.
【図５】従来例の構成図である。FIG. 5 is a configuration diagram of a conventional example.
【図６】スペクトラム純度説明図である。FIG. 6 is an explanatory diagram of spectrum purity.
１ 位相比較部 ２ 電圧制御
発振器 ３ Ｎ分周部 31 第１の分
周部分 32 第２の分周部分1 phase comparator 2 voltage controlled oscillator 3 N divider 31 first divider 32 second divider
Claims (1)
号の位相を比較して位相差分を取り出し、低域通過フイ
ルタを介して制御信号として送出する位相比較部(1)
と、入力する該制御信号に対応する周波数の出力信号を
送出する電圧制御発振器(2) と、該出力信号を分周する
第１の分周部分と該第１の分周部分の出力を更に分周し
て該比較信号として送出する第２の分周部分とを具備す
るＮ分周部(3) とを有する位相同期発振器において、 該第１の分周部分(31)の分周比は、該第１の分周部分の
出力周波数が該第２の分周部分の動作周波数範囲内とな
る値に設定し、該第２の分周部分(32)は、該第１の分周
部分より低速動作の素子を使用し、分周比はＮ／（第１
の分周部分の分周比）に設定することを特徴とする位相
同期発振器。1. A phase comparison unit (1) for comparing a phase of a reference signal having a predetermined frequency and a phase of a comparison signal to extract a phase difference and transmitting the phase difference as a control signal via a low-pass filter.
A voltage controlled oscillator (2) for transmitting an output signal having a frequency corresponding to the input control signal, a first frequency division portion for dividing the output signal, and an output of the first frequency division portion. In a phase-locked oscillator having an N frequency division section (3) having a second frequency division section for frequency division and transmitting as the comparison signal, the frequency division ratio of the first frequency division section (31) is , The output frequency of the first frequency division portion is set to a value within the operating frequency range of the second frequency division portion, and the second frequency division portion (32) is set to the first frequency division portion. A device operating at a lower speed is used, and the division ratio is N / (first
The division ratio of the frequency division part of the) is set.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4291855A JPH06152393A (en) | 1992-10-30 | 1992-10-30 | Phase synchronizing oscillator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4291855A JPH06152393A (en) | 1992-10-30 | 1992-10-30 | Phase synchronizing oscillator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06152393A true JPH06152393A (en) | 1994-05-31 |
Family
ID=17774298
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4291855A Withdrawn JPH06152393A (en) | 1992-10-30 | 1992-10-30 | Phase synchronizing oscillator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06152393A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005136630A (en) * | 2003-10-29 | 2005-05-26 | Mitsubishi Electric Corp | High frequency switch |
| JP2010034851A (en) * | 2008-07-29 | 2010-02-12 | Mitsubishi Electric Corp | Pll circuit |
-
1992
- 1992-10-30 JP JP4291855A patent/JPH06152393A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005136630A (en) * | 2003-10-29 | 2005-05-26 | Mitsubishi Electric Corp | High frequency switch |
| JP4518776B2 (en) * | 2003-10-29 | 2010-08-04 | 三菱電機株式会社 | High frequency switch and high frequency switch device |
| JP2010034851A (en) * | 2008-07-29 | 2010-02-12 | Mitsubishi Electric Corp | Pll circuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20000104 |